X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32_dmaacc.c;h=220ea94f92405dc0671b1b84c2f7643397341591;hp=9194bf6176f6070c1e7520c3f63d0c86a48ad7ee;hb=f19ac83152b54a204b8148815a538d868973e1e1;hpb=3c2eabd20f5182c53f0bfb0c6f2a9f2595434e87 diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index 9194bf6176..220ea94f92 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -18,16 +18,29 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "mips32_dmaacc.h" - +#include + +static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint8_t *buf); +static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint16_t *buf); +static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint32_t *buf); + +static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint8_t *buf); +static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint16_t *buf); +static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, const uint32_t *buf); /* * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick @@ -39,7 +52,23 @@ * displaying/modifying memory and memory mapped registers. */ -static int ejtag_dma_read(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t *data) +static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info) +{ + uint32_t ejtag_ctrl; + int64_t start = timeval_ms(); + + do { + if (timeval_ms() - start > 1000) { + LOG_ERROR("DMA time out"); + return -ETIMEDOUT; + } + ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); + return 0; +} + +static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data) { uint32_t v; uint32_t ejtag_ctrl; @@ -49,43 +78,38 @@ begin_ejtag_dma_read: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, data); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read; - } - else - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; } -static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint16_t *data) +static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data) { uint32_t v; uint32_t ejtag_ctrl; @@ -95,36 +119,32 @@ begin_ejtag_dma_read_h: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | + EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_h; - } - else - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -137,7 +157,7 @@ begin_ejtag_dma_read_h: return ERROR_OK; } -static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint8_t *data) +static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data) { uint32_t v; uint32_t ejtag_ctrl; @@ -147,36 +167,31 @@ begin_ejtag_dma_read_b: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Read Data */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_b; - } - else - LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); + } else + LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -191,7 +206,7 @@ begin_ejtag_dma_read_b: case 2: *data = (v >> 16) & 0xff; break; - case 3: + case 3: *data = (v >> 24) & 0xff; break; } @@ -199,7 +214,7 @@ begin_ejtag_dma_read_b: return ERROR_OK; } -static int ejtag_dma_write(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) +static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data) { uint32_t v; uint32_t ejtag_ctrl; @@ -209,44 +224,39 @@ begin_ejtag_dma_write: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write; - } - else - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; } -static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) +static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data) { uint32_t v; uint32_t ejtag_ctrl; @@ -260,44 +270,39 @@ begin_ejtag_dma_write_h: /* Setup Address */ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_h; - } - else - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; } -static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data) +static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data) { uint32_t v; uint32_t ejtag_ctrl; @@ -312,145 +317,144 @@ begin_ejtag_dma_write_b: /* Setup Address*/ v = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); mips_ejtag_drscan_32(ejtag_info, &v); /* Setup Data */ v = data; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Write & set DSTRT */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ - do { - ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + ejtag_dma_dstrt_poll(ejtag_info); /* Clear DMA & Check DERR */ - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr); + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_b; - } - else - LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr); + } else + LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; } -int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf) +int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); case 2: - return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf); + return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); case 4: - return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; } -int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf) +static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) { int i; int retval; - for (i=0; i