X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=d9d84b729b128fdc54311f70858d01a45327c41c;hp=24cd7d954a973d2743da415c4e2f7b6ea09fb721;hb=16b6b5e7a86353dbc0c4823fe3d772c0faca7c1c;hpb=ee17d5c48eaca42438663405ff6d090a391fc9e6

diff --git a/src/target/mips32.c b/src/target/mips32.c
index 24cd7d954a..d9d84b729b 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -7,6 +7,9 @@
  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
+ *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
+ *   drasko.draskovic@gmail.com                                            *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -143,15 +146,13 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 static int mips32_read_core_reg(struct target *target, int num)
 {
 	uint32_t reg_value;
-	struct mips32_core_reg *mips_core_reg;
 
 	/* get pointers to arch-specific information */
 	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 	reg_value = mips32->core_regs[num];
 	buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
 	mips32->core_cache->reg_list[num].valid = 1;
@@ -163,16 +164,14 @@ static int mips32_read_core_reg(struct target *target, int num)
 static int mips32_write_core_reg(struct target *target, int num)
 {
 	uint32_t reg_value;
-	struct mips32_core_reg *mips_core_reg;
 
 	/* get pointers to arch-specific information */
 	struct mips32_common *mips32 = target_to_mips32(target);
 
 	if ((num < 0) || (num >= MIPS32NUMCOREREGS))
-		return ERROR_INVALID_ARGUMENTS;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
-	mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 	mips32->core_regs[num] = reg_value;
 	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 	mips32->core_cache->reg_list[num].valid = 1;
@@ -309,6 +308,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
 {
 	target->arch_info = mips32;
 	mips32->common_magic = MIPS32_COMMON_MAGIC;
+	mips32->fast_data_area = NULL;
 
 	/* has breakpoint/watchpint unit been scanned */
 	mips32->bp_scanned = 0;
@@ -350,7 +350,7 @@ static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
 	pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 	if (exit_point && (pc != exit_point))
 	{
-		LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+		LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
 		return ERROR_TARGET_TIMEOUT;
 	}
 
@@ -411,14 +411,14 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
 		if (!reg)
 		{
 			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		if (reg->size != reg_params[i].size)
 		{
 			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
 					reg_params[i].reg_name);
-			return ERROR_INVALID_ARGUMENTS;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		mips32_set_core_reg(reg, reg_params[i].value);
@@ -451,14 +451,14 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
 			if (!reg)
 			{
 				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			}
 
 			if (reg->size != reg_params[i].size)
 			{
 				LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
 						reg_params[i].reg_name);
-				return ERROR_INVALID_ARGUMENTS;
+				return ERROR_COMMAND_SYNTAX_ERROR;
 			}
 
 			buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
@@ -558,6 +558,13 @@ int mips32_configure_break_unit(struct target *target)
 			return retval;
 	}
 
+	/* check if target endianness settings matches debug control register */
+	if ( (  (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) ||
+		( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)    ) )
+	{
+		LOG_WARNING("DCR endianness settings does not match target settings");
+	}
+
 	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
 			mips32->num_data_bpoints);
 
@@ -613,6 +620,8 @@ int mips32_checksum_memory(struct target *target, uint32_t address,
 	int retval;
 	uint32_t i;
 
+	/* see contib/loaders/checksum/mips32.s for src */
+
 	static const uint32_t mips_crc_code[] =
 	{
 		0x248C0000,		/* addiu 	$t4, $a0, 0 */
@@ -752,3 +761,106 @@ int mips32_blank_check_memory(struct target *target,
 
 	return ERROR_OK;
 }
+
+static int mips32_verify_pointer(struct command_context *cmd_ctx,
+		struct mips32_common *mips32)
+{
+	if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
+		command_print(cmd_ctx, "target is not an MIPS32");
+		return ERROR_TARGET_INVALID;
+	}
+	return ERROR_OK;
+}
+
+/**
+ * MIPS32 targets expose command interface
+ * to manipulate CP0 registers
+ */
+COMMAND_HANDLER(mips32_handle_cp0_command)
+{
+	int retval;
+	struct target *target = get_current_target(CMD_CTX);
+	struct mips32_common *mips32 = target_to_mips32(target);
+	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+
+
+	retval = mips32_verify_pointer(CMD_CTX, mips32);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (target->state != TARGET_HALTED)
+	{
+		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		return ERROR_OK;
+	}
+
+	/* two or more argument, access a single register/select (write if third argument is given) */
+	if (CMD_ARGC < 2)
+	{
+	    return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+	else
+	{
+		uint32_t cp0_reg, cp0_sel;
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
+
+		if (CMD_ARGC == 2)
+		{
+			uint32_t value;
+
+			if ((retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel)) != ERROR_OK)
+			{
+				command_print(CMD_CTX,
+						"couldn't access reg %" PRIi32,
+						cp0_reg);
+				return ERROR_OK;
+			}
+			if ((retval = jtag_execute_queue()) != ERROR_OK)
+			{
+				return retval;
+			}
+
+			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+					cp0_reg, cp0_sel, value);
+		}
+		else if (CMD_ARGC == 3)
+		{
+			uint32_t value;
+			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+			if ((retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel)) != ERROR_OK)
+			{
+				command_print(CMD_CTX,
+						"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+						cp0_reg,  cp0_sel);
+				return ERROR_OK;
+			}
+			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+					cp0_reg, cp0_sel, value);
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static const struct command_registration mips32_exec_command_handlers[] = {
+	{
+		.name = "cp0",
+		.handler = mips32_handle_cp0_command,
+		.mode = COMMAND_EXEC,
+		.usage = "regnum select [value]",
+		.help = "display/modify cp0 register",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration mips32_command_handlers[] = {
+	{
+		.name = "mips32",
+		.mode = COMMAND_ANY,
+		.help = "mips32 command group",
+		.chain = mips32_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+