X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=533701aaafde0e35f9c0053d34c6be7842e43920;hp=d1722c1ab06ea847a9844d3a1c845ccdd1bb4df0;hb=4617cd0f911d64a460d99d25c531ddc55f2452ca;hpb=42ef503d37b18d907da16d26e99167566d5aabd1 diff --git a/src/target/mips32.c b/src/target/mips32.c index d1722c1ab0..533701aaaf 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -27,9 +27,11 @@ #endif #include "mips32.h" +#include "breakpoints.h" +#include "algorithm.h" +#include "register.h" - -char* mips32_core_reg_list[] = +static char* mips32_core_reg_list[] = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", @@ -38,7 +40,12 @@ char* mips32_core_reg_list[] = "status", "lo", "hi", "badvaddr", "cause", "pc" }; -mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = +static const char *mips_isa_strings[] = +{ + "MIPS32", "MIPS16e" +}; + +static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = { {0, NULL, NULL}, {1, NULL, NULL}, @@ -86,21 +93,24 @@ mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = #define MIPS32NUMFPREGS 34 + 18 -uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; +static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -reg_t mips32_gdb_dummy_fp_reg = +static struct reg mips32_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point register", + .value = mips32_gdb_dummy_fp_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, }; -int mips32_core_reg_arch_type = -1; - -int mips32_get_core_reg(reg_t *reg) +static int mips32_get_core_reg(struct reg *reg) { int retval; - mips32_core_reg_t *mips32_reg = reg->arch_info; - target_t *target = mips32_reg->target; - mips32_common_t *mips32_target = target->arch_info; + struct mips32_core_reg *mips32_reg = reg->arch_info; + struct target *target = mips32_reg->target; + struct mips32_common *mips32_target = target_to_mips32(target); if (target->state != TARGET_HALTED) { @@ -112,10 +122,10 @@ int mips32_get_core_reg(reg_t *reg) return retval; } -int mips32_set_core_reg(reg_t *reg, uint8_t *buf) +static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) { - mips32_core_reg_t *mips32_reg = reg->arch_info; - target_t *target = mips32_reg->target; + struct mips32_core_reg *mips32_reg = reg->arch_info; + struct target *target = mips32_reg->target; uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -130,13 +140,13 @@ int mips32_set_core_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int mips32_read_core_reg(struct target_s *target, int num) +static int mips32_read_core_reg(struct target *target, int num) { uint32_t reg_value; - mips32_core_reg_t *mips_core_reg; + struct mips32_core_reg *mips_core_reg; /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); if ((num < 0) || (num >= MIPS32NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; @@ -150,13 +160,13 @@ int mips32_read_core_reg(struct target_s *target, int num) return ERROR_OK; } -int mips32_write_core_reg(struct target_s *target, int num) +static int mips32_write_core_reg(struct target *target, int num) { uint32_t reg_value; - mips32_core_reg_t *mips_core_reg; + struct mips32_core_reg *mips_core_reg; /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); if ((num < 0) || (num >= MIPS32NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; @@ -171,30 +181,15 @@ int mips32_write_core_reg(struct target_s *target, int num) return ERROR_OK; } -int mips32_invalidate_core_regs(target_t *target) -{ - /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - int i; - - for (i = 0; i < mips32->core_cache->num_regs; i++) - { - mips32->core_cache->reg_list[i].valid = 0; - mips32->core_cache->reg_list[i].dirty = 0; - } - - return ERROR_OK; -} - -int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) +int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); int i; /* include floating point registers */ *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; - *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); for (i = 0; i < MIPS32NUMCOREREGS; i++) { @@ -210,13 +205,13 @@ int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ return ERROR_OK; } -int mips32_save_context(target_t *target) +int mips32_save_context(struct target *target) { int i; /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; /* read core registers */ mips32_pracc_read_regs(ejtag_info, mips32->core_regs); @@ -232,13 +227,13 @@ int mips32_save_context(target_t *target) return ERROR_OK; } -int mips32_restore_context(target_t *target) +int mips32_restore_context(struct target *target) { int i; /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; - mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; for (i = 0; i < MIPS32NUMCOREREGS; i++) { @@ -254,38 +249,35 @@ int mips32_restore_context(target_t *target) return ERROR_OK; } -int mips32_arch_state(struct target_s *target) +int mips32_arch_state(struct target *target) { - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); - if (mips32->common_magic != MIPS32_COMMON_MAGIC) - { - LOG_ERROR("BUG: called for a non-MIPS32 target"); - exit(-1); - } - - LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "", - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , + LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "", + mips_isa_strings[mips32->isa_mode], + debug_reason_name(target), buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)); return ERROR_OK; } -reg_cache_t *mips32_build_reg_cache(target_t *target) +static const struct reg_arch_type mips32_reg_type = { + .get = mips32_get_core_reg, + .set = mips32_set_core_reg, +}; + +struct reg_cache *mips32_build_reg_cache(struct target *target) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); int num_regs = MIPS32NUMCOREREGS; - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - mips32_core_reg_t *arch_info = malloc(sizeof(mips32_core_reg_t) * num_regs); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); + struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs); int i; - if (mips32_core_reg_arch_type == -1) - mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg); - register_init_dummy(&mips32_gdb_dummy_fp_reg); /* Build the process context cache */ @@ -306,16 +298,14 @@ reg_cache_t *mips32_build_reg_cache(target_t *target) reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; - reg_list[i].arch_type = mips32_core_reg_arch_type; + reg_list[i].type = &mips32_reg_type; reg_list[i].arch_info = &arch_info[i]; } return cache; } -int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, struct jtag_tap *tap) +int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap) { target->arch_info = mips32; mips32->common_magic = MIPS32_COMMON_MAGIC; @@ -331,20 +321,174 @@ int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, struct jtag return ERROR_OK; } -int mips32_register_commands(struct command_context_s *cmd_ctx) +/* run to exit point. return error if exit point was not reached. */ +static int mips32_run_and_wait(struct target *target, uint32_t entry_point, + int timeout_ms, uint32_t exit_point, struct mips32_common *mips32) { + uint32_t pc; + int retval; + /* This code relies on the target specific resume() and poll()->debug_entry() + * sequence to write register values to the processor and the read them back */ + if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK) + { + return retval; + } + + retval = target_wait_state(target, TARGET_HALTED, timeout_ms); + /* If the target fails to halt due to the breakpoint, force a halt */ + if (retval != ERROR_OK || target->state != TARGET_HALTED) + { + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) + { + return retval; + } + return ERROR_TARGET_TIMEOUT; + } + + pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); + if (exit_point && (pc != exit_point)) + { + LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc); + return ERROR_TARGET_TIMEOUT; + } + return ERROR_OK; } -int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +int mips32_run_algorithm(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_params, uint32_t entry_point, + uint32_t exit_point, int timeout_ms, void *arch_info) { - /*TODO*/ + struct mips32_common *mips32 = target_to_mips32(target); + struct mips32_algorithm *mips32_algorithm_info = arch_info; + enum mips32_isa_mode isa_mode = mips32->isa_mode; + + uint32_t context[MIPS32NUMCOREREGS]; + int i; + int retval = ERROR_OK; + + LOG_DEBUG("Running algorithm"); + + /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint + * at the exit point */ + + if (mips32->common_magic != MIPS32_COMMON_MAGIC) + { + LOG_ERROR("current target isn't a MIPS32 target"); + return ERROR_TARGET_INVALID; + } + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* refresh core register cache */ + for (i = 0; i < MIPS32NUMCOREREGS; i++) + { + if (!mips32->core_cache->reg_list[i].valid) + mips32->read_core_reg(target, i); + context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); + } + + for (i = 0; i < num_mem_params; i++) + { + if ((retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, mem_params[i].value)) != ERROR_OK) + { + return retval; + } + } + + for (i = 0; i < num_reg_params; i++) + { + struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); + + if (!reg) + { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + return ERROR_INVALID_ARGUMENTS; + } + + if (reg->size != reg_params[i].size) + { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); + return ERROR_INVALID_ARGUMENTS; + } + + mips32_set_core_reg(reg, reg_params[i].value); + } + + mips32->isa_mode = mips32_algorithm_info->isa_mode; + + retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32); + + if (retval != ERROR_OK) + return retval; + + for (i = 0; i < num_mem_params; i++) + { + if (mem_params[i].direction != PARAM_OUT) + { + if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, + mem_params[i].value)) != ERROR_OK) + { + return retval; + } + } + } + + for (i = 0; i < num_reg_params; i++) + { + if (reg_params[i].direction != PARAM_OUT) + { + struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); + if (!reg) + { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + return ERROR_INVALID_ARGUMENTS; + } + + if (reg->size != reg_params[i].size) + { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); + return ERROR_INVALID_ARGUMENTS; + } + + buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); + } + } + + /* restore everything we saved before */ + for (i = 0; i < MIPS32NUMCOREREGS; i++) + { + uint32_t regvalue; + regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); + if (regvalue != context[i]) + { + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, + mips32->core_cache->reg_list[i].name, context[i]); + buf_set_u32(mips32->core_cache->reg_list[i].value, + 0, 32, context[i]); + mips32->core_cache->reg_list[i].valid = 1; + mips32->core_cache->reg_list[i].dirty = 1; + } + } + + mips32->isa_mode = isa_mode; + return ERROR_OK; } -int mips32_examine(struct target_s *target) +int mips32_examine(struct target *target) { - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); if (!target_was_examined(target)) { @@ -361,10 +505,10 @@ int mips32_examine(struct target_s *target) return ERROR_OK; } -int mips32_configure_break_unit(struct target_s *target) +int mips32_configure_break_unit(struct target *target) { /* get pointers to arch-specific information */ - mips32_common_t *mips32 = target->arch_info; + struct mips32_common *mips32 = target_to_mips32(target); int retval; uint32_t dcr, bpinfo; int i; @@ -376,7 +520,7 @@ int mips32_configure_break_unit(struct target_s *target) if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) return retval; - if (dcr & (1 << 16)) + if (dcr & EJTAG_DCR_IB) { /* get number of inst breakpoints */ if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK) @@ -384,7 +528,7 @@ int mips32_configure_break_unit(struct target_s *target) mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F; mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints; - mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t)); + mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator)); for (i = 0; i < mips32->num_inst_bpoints; i++) { mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i); @@ -395,7 +539,7 @@ int mips32_configure_break_unit(struct target_s *target) return retval; } - if (dcr & (1 << 17)) + if (dcr & EJTAG_DCR_DB) { /* get number of data breakpoints */ if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK) @@ -403,7 +547,7 @@ int mips32_configure_break_unit(struct target_s *target) mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F; mips32->num_data_bpoints_avail = mips32->num_data_bpoints; - mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t)); + mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator)); for (i = 0; i < mips32->num_data_bpoints; i++) { mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i); @@ -414,14 +558,15 @@ int mips32_configure_break_unit(struct target_s *target) return retval; } - LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints); + LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, + mips32->num_data_bpoints); mips32->bp_scanned = 1; return ERROR_OK; } -int mips32_enable_interrupts(struct target_s *target, int enable) +int mips32_enable_interrupts(struct target *target, int enable) { int retval; int update = 0; @@ -433,19 +578,19 @@ int mips32_enable_interrupts(struct target_s *target, int enable) if (enable) { - if (!(dcr & (1 << 4))) + if (!(dcr & EJTAG_DCR_INTE)) { /* enable interrupts */ - dcr |= (1 << 4); + dcr |= EJTAG_DCR_INTE; update = 1; } } else { - if (dcr & (1 << 4)) + if (dcr & EJTAG_DCR_INTE) { /* disable interrupts */ - dcr &= ~(1 << 4); + dcr &= ~EJTAG_DCR_INTE; update = 1; } } @@ -458,3 +603,154 @@ int mips32_enable_interrupts(struct target_s *target, int enable) return ERROR_OK; } + +int mips32_checksum_memory(struct target *target, uint32_t address, + uint32_t count, uint32_t* checksum) +{ + struct working_area *crc_algorithm; + struct reg_param reg_params[2]; + struct mips32_algorithm mips32_info; + int retval; + uint32_t i; + + /* see contib/loaders/checksum/mips32.s for src */ + + static const uint32_t mips_crc_code[] = + { + 0x248C0000, /* addiu $t4, $a0, 0 */ + 0x24AA0000, /* addiu $t2, $a1, 0 */ + 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */ + 0x10000010, /* beq $zero, $zero, ncomp */ + 0x240B0000, /* addiu $t3, $zero, 0 */ + /* nbyte: */ + 0x81850000, /* lb $a1, ($t4) */ + 0x218C0001, /* addi $t4, $t4, 1 */ + 0x00052E00, /* sll $a1, $a1, 24 */ + 0x3C0204C1, /* lui $v0, 0x04c1 */ + 0x00852026, /* xor $a0, $a0, $a1 */ + 0x34471DB7, /* ori $a3, $v0, 0x1db7 */ + 0x00003021, /* addu $a2, $zero, $zero */ + /* loop: */ + 0x00044040, /* sll $t0, $a0, 1 */ + 0x24C60001, /* addiu $a2, $a2, 1 */ + 0x28840000, /* slti $a0, $a0, 0 */ + 0x01074826, /* xor $t1, $t0, $a3 */ + 0x0124400B, /* movn $t0, $t1, $a0 */ + 0x28C30008, /* slti $v1, $a2, 8 */ + 0x1460FFF9, /* bne $v1, $zero, loop */ + 0x01002021, /* addu $a0, $t0, $zero */ + /* ncomp: */ + 0x154BFFF0, /* bne $t2, $t3, nbyte */ + 0x256B0001, /* addiu $t3, $t3, 1 */ + 0x7000003F, /* sdbbp */ + }; + + /* make sure we have a working area */ + if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK) + { + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* convert flash writing code into a buffer in target endianness */ + for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++) + target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]); + + mips32_info.common_magic = MIPS32_COMMON_MAGIC; + mips32_info.isa_mode = MIPS32_ISA_MIPS32; + + init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[0].value, 0, 32, address); + + init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, count); + + int timeout = 20000 * (1 + (count / (1024 * 1024))); + + if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, + crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout, + &mips32_info)) != ERROR_OK) + { + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + target_free_working_area(target, crc_algorithm); + return 0; + } + + *checksum = buf_get_u32(reg_params[0].value, 0, 32); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + + target_free_working_area(target, crc_algorithm); + + return ERROR_OK; +} + +/** Checks whether a memory region is zeroed. */ +int mips32_blank_check_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* blank) +{ + struct working_area *erase_check_algorithm; + struct reg_param reg_params[3]; + struct mips32_algorithm mips32_info; + int retval; + uint32_t i; + + static const uint32_t erase_check_code[] = + { + /* nbyte: */ + 0x80880000, /* lb $t0, ($a0) */ + 0x00C83024, /* and $a2, $a2, $t0 */ + 0x24A5FFFF, /* addiu $a1, $a1, -1 */ + 0x14A0FFFC, /* bne $a1, $zero, nbyte */ + 0x24840001, /* addiu $a0, $a0, 1 */ + 0x7000003F /* sdbbp */ + }; + + /* make sure we have a working area */ + if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) + { + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* convert flash writing code into a buffer in target endianness */ + for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) + { + target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), + erase_check_code[i]); + } + + mips32_info.common_magic = MIPS32_COMMON_MAGIC; + mips32_info.isa_mode = MIPS32_ISA_MIPS32; + + init_reg_param(®_params[0], "a0", 32, PARAM_OUT); + buf_set_u32(reg_params[0].value, 0, 32, address); + + init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, count); + + init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, 0xff); + + if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, + erase_check_algorithm->address, + erase_check_algorithm->address + (sizeof(erase_check_code)-2), + 10000, &mips32_info)) != ERROR_OK) + { + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + target_free_working_area(target, erase_check_algorithm); + return 0; + } + + *blank = buf_get_u32(reg_params[2].value, 0, 32); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + + target_free_working_area(target, erase_check_algorithm); + + return ERROR_OK; +}