X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fmips32.c;h=5260032164e3fb59f005003fa0328fce303409b6;hp=11f39fea881d6b1c43944c8a97236314c38eddf8;hb=5fbf4d4cc3f67ec8b2fb3d8a789117583a84e1a1;hpb=bc1340cf0b9aa28c03d1b07c54b6e0bf4a483351 diff --git a/src/target/mips32.c b/src/target/mips32.c index 11f39fea88..5260032164 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -21,9 +21,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -36,70 +34,137 @@ #include "register.h" static const char *mips_isa_strings[] = { - "MIPS32", "MIPS16e" + "MIPS32", "MIPS16", "", "MICRO MIPS32", }; +#define MIPS32_GDB_DUMMY_FP_REG 1 + +/* + * GDB registers + * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml + */ static const struct { unsigned id; const char *name; -} mips32_regs[MIPS32NUMCOREREGS] = { - { 0, "zero", }, - { 1, "at", }, - { 2, "v0", }, - { 3, "v1", }, - { 4, "a0", }, - { 5, "a1", }, - { 6, "a2", }, - { 7, "a3", }, - { 8, "t0", }, - { 9, "t1", }, - { 10, "t2", }, - { 11, "t3", }, - { 12, "t4", }, - { 13, "t5", }, - { 14, "t6", }, - { 15, "t7", }, - { 16, "s0", }, - { 17, "s1", }, - { 18, "s2", }, - { 19, "s3", }, - { 20, "s4", }, - { 21, "s5", }, - { 22, "s6", }, - { 23, "s7", }, - { 24, "t8", }, - { 25, "t9", }, - { 26, "k0", }, - { 27, "k1", }, - { 28, "gp", }, - { 29, "sp", }, - { 30, "fp", }, - { 31, "ra", }, - - { 32, "status", }, - { 33, "lo", }, - { 34, "hi", }, - { 35, "badvaddr", }, - { 36, "cause", }, - { 37, "pc" }, + enum reg_type type; + const char *group; + const char *feature; + int flag; +} mips32_regs[] = { + { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + { 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 }, + { 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 }, + + { 38, "f0", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 39, "f1", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 40, "f2", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 41, "f3", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 42, "f4", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 43, "f5", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 44, "f6", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 45, "f7", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 46, "f8", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 47, "f9", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 48, "f10", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 49, "f11", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 50, "f12", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 51, "f13", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 52, "f14", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 53, "f15", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 54, "f16", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 55, "f17", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 56, "f18", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 57, "f19", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 58, "f20", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 59, "f21", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 60, "f22", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 61, "f23", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 62, "f24", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 63, "f25", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 64, "f26", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 65, "f27", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 66, "f28", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 67, "f29", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 68, "f30", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 69, "f31", REG_TYPE_IEEE_SINGLE, NULL, + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 70, "fcsr", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, + { 71, "fir", REG_TYPE_INT, "float", + "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG }, }; -/* number of mips dummy fp regs fp0 - fp31 + fsr and fir - * we also add 18 unknown registers to handle gdb requests */ -#define MIPS32NUMFPREGS (34 + 18) +#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs) static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -static struct reg mips32_gdb_dummy_fp_reg = { - .name = "GDB dummy floating-point register", - .value = mips32_gdb_dummy_fp_value, - .dirty = 0, - .valid = 1, - .size = 32, - .arch_info = NULL, -}; - static int mips32_get_core_reg(struct reg *reg) { int retval; @@ -125,45 +190,45 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } -static int mips32_read_core_reg(struct target *target, int num) +static int mips32_read_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = mips32->core_regs[num]; buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); - mips32->core_cache->reg_list[num].valid = 1; - mips32->core_cache->reg_list[num].dirty = 0; + mips32->core_cache->reg_list[num].valid = true; + mips32->core_cache->reg_list[num].dirty = false; return ERROR_OK; } -static int mips32_write_core_reg(struct target *target, int num) +static int mips32_write_core_reg(struct target *target, unsigned int num) { uint32_t reg_value; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if ((num < 0) || (num >= MIPS32NUMCOREREGS)) + if (num >= MIPS32_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); mips32->core_regs[num] = reg_value; LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); - mips32->core_cache->reg_list[num].valid = 1; - mips32->core_cache->reg_list[num].dirty = 0; + mips32->core_cache->reg_list[num].valid = true; + mips32->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -173,25 +238,21 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], { /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - int i; + unsigned int i; /* include floating point registers */ - *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; + *reg_list_size = MIPS32_NUM_REGS; *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); - for (i = 0; i < MIPS32NUMCOREREGS; i++) + for (i = 0; i < MIPS32_NUM_REGS; i++) (*reg_list)[i] = &mips32->core_cache->reg_list[i]; - /* add dummy floating points regs */ - for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++) - (*reg_list)[i] = &mips32_gdb_dummy_fp_reg; - return ERROR_OK; } int mips32_save_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); @@ -200,7 +261,7 @@ int mips32_save_context(struct target *target) /* read core registers */ mips32_pracc_read_regs(ejtag_info, mips32->core_regs); - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (i = 0; i < MIPS32_NUM_REGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); } @@ -210,13 +271,13 @@ int mips32_save_context(struct target *target) int mips32_restore_context(struct target *target) { - int i; + unsigned int i; /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (i = 0; i < MIPS32_NUM_REGS; i++) { if (mips32->core_cache->reg_list[i].dirty) mips32->write_core_reg(target, i); } @@ -249,15 +310,14 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - int num_regs = MIPS32NUMCOREREGS; + int num_regs = MIPS32_NUM_REGS; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); - struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); + struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs); + struct reg_feature *feature; int i; - register_init_dummy(&mips32_gdb_dummy_fp_reg); - /* Build the process context cache */ cache->name = "mips32 registers"; cache->next = NULL; @@ -273,11 +333,38 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) reg_list[i].name = mips32_regs[i].name; reg_list[i].size = 32; - reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].type = &mips32_reg_type; - reg_list[i].arch_info = &arch_info[i]; + + if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) { + reg_list[i].value = mips32_gdb_dummy_fp_value; + reg_list[i].valid = true; + reg_list[i].arch_info = NULL; + register_init_dummy(®_list[i]); + } else { + reg_list[i].value = calloc(1, 4); + reg_list[i].valid = false; + reg_list[i].type = &mips32_reg_type; + reg_list[i].arch_info = &arch_info[i]; + + reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type)); + if (reg_list[i].reg_data_type) + reg_list[i].reg_data_type->type = mips32_regs[i].type; + else + LOG_ERROR("unable to allocate reg type list"); + } + + reg_list[i].dirty = false; + + reg_list[i].group = mips32_regs[i].group; + reg_list[i].number = i; + reg_list[i].exist = true; + reg_list[i].caller_save = true; /* gdb defaults to true */ + + feature = calloc(1, sizeof(struct reg_feature)); + if (feature) { + feature->name = mips32_regs[i].feature; + reg_list[i].feature = feature; + } else + LOG_ERROR("unable to allocate feature list"); } return cache; @@ -288,24 +375,27 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s target->arch_info = mips32; mips32->common_magic = MIPS32_COMMON_MAGIC; mips32->fast_data_area = NULL; + mips32->isa_imp = MIPS32_ONLY; /* default */ - /* has breakpoint/watchpint unit been scanned */ + /* has breakpoint/watchpoint unit been scanned */ mips32->bp_scanned = 0; mips32->data_break_list = NULL; mips32->ejtag_info.tap = tap; mips32->read_core_reg = mips32_read_core_reg; mips32->write_core_reg = mips32_write_core_reg; - - mips32->ejtag_info.scan_delay = 2000000; /* Initial default value */ + /* if unknown endianness defaults to little endian, 1 */ + mips32->ejtag_info.endianness = target->endianness == TARGET_BIG_ENDIAN ? 0 : 1; + mips32->ejtag_info.scan_delay = MIPS32_SCAN_DELAY_LEGACY_MODE; mips32->ejtag_info.mode = 0; /* Initial default value */ - + mips32->ejtag_info.isa = 0; /* isa on debug mips32, updated by poll function */ + mips32->ejtag_info.config_regs = 0; /* no config register read */ return ERROR_OK; } /* run to exit point. return error if exit point was not reached. */ -static int mips32_run_and_wait(struct target *target, uint32_t entry_point, - int timeout_ms, uint32_t exit_point, struct mips32_common *mips32) +static int mips32_run_and_wait(struct target *target, target_addr_t entry_point, + int timeout_ms, target_addr_t exit_point, struct mips32_common *mips32) { uint32_t pc; int retval; @@ -338,15 +428,14 @@ static int mips32_run_and_wait(struct target *target, uint32_t entry_point, int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, - struct reg_param *reg_params, uint32_t entry_point, - uint32_t exit_point, int timeout_ms, void *arch_info) + struct reg_param *reg_params, target_addr_t entry_point, + target_addr_t exit_point, int timeout_ms, void *arch_info) { struct mips32_common *mips32 = target_to_mips32(target); struct mips32_algorithm *mips32_algorithm_info = arch_info; enum mips32_isa_mode isa_mode = mips32->isa_mode; - uint32_t context[MIPS32NUMCOREREGS]; - int i; + uint32_t context[MIPS32_NUM_REGS]; int retval = ERROR_OK; LOG_DEBUG("Running algorithm"); @@ -365,20 +454,25 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* refresh core register cache */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction == PARAM_IN) + continue; retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); if (retval != ERROR_OK) return retval; } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction == PARAM_IN) + continue; + struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -402,7 +496,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, if (retval != ERROR_OK) return retval; - for (i = 0; i < num_mem_params; i++) { + for (int i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) { retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); @@ -411,7 +505,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } } - for (i = 0; i < num_reg_params; i++) { + for (int i = 0; i < num_reg_params; i++) { if (reg_params[i].direction != PARAM_OUT) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); if (!reg) { @@ -430,7 +524,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* restore everything we saved before */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) { + for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) { uint32_t regvalue; regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { @@ -438,8 +532,8 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, mips32->core_cache->reg_list[i].name, context[i]); buf_set_u32(mips32->core_cache->reg_list[i].value, 0, 32, context[i]); - mips32->core_cache->reg_list[i].valid = 1; - mips32->core_cache->reg_list[i].dirty = 1; + mips32->core_cache->reg_list[i].valid = true; + mips32->core_cache->reg_list[i].dirty = true; } } @@ -536,26 +630,36 @@ int mips32_configure_break_unit(struct target *target) if (retval != ERROR_OK) return retval; - /* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits, - * assume IB and DB registers are always present. */ - if (ejtag_info->ejtag_version == EJTAG_VERSION_20) - dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB; + /* EJTAG 2.0 defines IB and DB bits in IMP instead of DCR. */ + if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { + ejtag_info->debug_caps = dcr & EJTAG_DCR_ENM; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NOIB)) + ejtag_info->debug_caps |= EJTAG_DCR_IB; + if (!(ejtag_info->impcode & EJTAG_V20_IMP_NODB)) + ejtag_info->debug_caps |= EJTAG_DCR_DB; + } else + /* keep debug caps for later use */ + ejtag_info->debug_caps = dcr & (EJTAG_DCR_ENM + | EJTAG_DCR_IB | EJTAG_DCR_DB); + - if (dcr & EJTAG_DCR_IB) { + if (ejtag_info->debug_caps & EJTAG_DCR_IB) { retval = mips32_configure_ibs(target); if (retval != ERROR_OK) return retval; } - if (dcr & EJTAG_DCR_DB) { + if (ejtag_info->debug_caps & EJTAG_DCR_DB) { retval = mips32_configure_dbs(target); if (retval != ERROR_OK) return retval; } /* check if target endianness settings matches debug control register */ - if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || - (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) + if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) + && (target->endianness == TARGET_BIG_ENDIAN))) LOG_WARNING("DCR endianness settings does not match target settings"); LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, @@ -600,155 +704,212 @@ int mips32_enable_interrupts(struct target *target, int enable) return ERROR_OK; } -int mips32_checksum_memory(struct target *target, uint32_t address, +/* read config to config3 cp0 registers and log isa implementation */ +int mips32_read_config_regs(struct target *target) +{ + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + if (ejtag_info->config_regs == 0) + for (int i = 0; i != 4; i++) { + int retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i); + if (retval != ERROR_OK) { + LOG_ERROR("isa info not available, failed to read cp0 config register: %" PRId32, i); + ejtag_info->config_regs = 0; + return retval; + } + ejtag_info->config_regs = i + 1; + if ((ejtag_info->config[i] & (1 << 31)) == 0) + break; /* no more config registers implemented */ + } + else + return ERROR_OK; /* already succesfully read */ + + LOG_DEBUG("read %"PRId32" config registers", ejtag_info->config_regs); + + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { + mips32->isa_imp = MIPS32_MIPS16; + LOG_USER("MIPS32 with MIPS16 support implemented"); + + } else if (ejtag_info->config_regs >= 4) { /* config3 implemented */ + unsigned isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT; + if (isa_imp == 1) { + mips32->isa_imp = MMIPS32_ONLY; + LOG_USER("MICRO MIPS32 only implemented"); + + } else if (isa_imp != 0) { + mips32->isa_imp = MIPS32_MMIPS32; + LOG_USER("MIPS32 and MICRO MIPS32 implemented"); + } + } + + if (mips32->isa_imp == MIPS32_ONLY) /* initial default value */ + LOG_USER("MIPS32 only implemented"); + + return ERROR_OK; +} +int mips32_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct reg_param reg_params[2]; struct mips32_algorithm mips32_info; - int retval; - uint32_t i; - /* see contib/loaders/checksum/mips32.s for src */ + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + /* see contrib/loaders/checksum/mips32.s for src */ + uint32_t isa = ejtag_info->isa ? 1 : 0; - static const uint32_t mips_crc_code[] = { - 0x248C0000, /* addiu $t4, $a0, 0 */ - 0x24AA0000, /* addiu $t2, $a1, 0 */ - 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */ - 0x10000010, /* beq $zero, $zero, ncomp */ - 0x240B0000, /* addiu $t3, $zero, 0 */ + uint32_t mips_crc_code[] = { + MIPS32_ADDIU(isa, 12, 4, 0), /* addiu $t4, $a0, 0 */ + MIPS32_ADDIU(isa, 10, 5, 0), /* addiu $t2, $a1, 0 */ + MIPS32_ADDIU(isa, 4, 0, 0xFFFF), /* addiu $a0, $zero, 0xffff */ + MIPS32_BEQ(isa, 0, 0, 0x10 << isa), /* beq $zero, $zero, ncomp */ + MIPS32_ADDIU(isa, 11, 0, 0), /* addiu $t3, $zero, 0 */ /* nbyte: */ - 0x81850000, /* lb $a1, ($t4) */ - 0x218C0001, /* addi $t4, $t4, 1 */ - 0x00052E00, /* sll $a1, $a1, 24 */ - 0x3C0204C1, /* lui $v0, 0x04c1 */ - 0x00852026, /* xor $a0, $a0, $a1 */ - 0x34471DB7, /* ori $a3, $v0, 0x1db7 */ - 0x00003021, /* addu $a2, $zero, $zero */ - /* loop: */ - 0x00044040, /* sll $t0, $a0, 1 */ - 0x24C60001, /* addiu $a2, $a2, 1 */ - 0x28840000, /* slti $a0, $a0, 0 */ - 0x01074826, /* xor $t1, $t0, $a3 */ - 0x0124400B, /* movn $t0, $t1, $a0 */ - 0x28C30008, /* slti $v1, $a2, 8 */ - 0x1460FFF9, /* bne $v1, $zero, loop */ - 0x01002021, /* addu $a0, $t0, $zero */ - /* ncomp: */ - 0x154BFFF0, /* bne $t2, $t3, nbyte */ - 0x256B0001, /* addiu $t3, $t3, 1 */ - 0x7000003F, /* sdbbp */ + MIPS32_LB(isa, 5, 0, 12), /* lb $a1, ($t4) */ + MIPS32_ADDI(isa, 12, 12, 1), /* addi $t4, $t4, 1 */ + MIPS32_SLL(isa, 5, 5, 24), /* sll $a1, $a1, 24 */ + MIPS32_LUI(isa, 2, 0x04c1), /* lui $v0, 0x04c1 */ + MIPS32_XOR(isa, 4, 4, 5), /* xor $a0, $a0, $a1 */ + MIPS32_ORI(isa, 7, 2, 0x1db7), /* ori $a3, $v0, 0x1db7 */ + MIPS32_ADDU(isa, 6, 0, 0), /* addu $a2, $zero, $zero */ + /* loop */ + MIPS32_SLL(isa, 8, 4, 1), /* sll $t0, $a0, 1 */ + MIPS32_ADDIU(isa, 6, 6, 1), /* addiu $a2, $a2, 1 */ + MIPS32_SLTI(isa, 4, 4, 0), /* slti $a0, $a0, 0 */ + MIPS32_XOR(isa, 9, 8, 7), /* xor $t1, $t0, $a3 */ + MIPS32_MOVN(isa, 8, 9, 4), /* movn $t0, $t1, $a0 */ + MIPS32_SLTI(isa, 3, 6, 8), /* slti $v1, $a2, 8 */ + MIPS32_BNE(isa, 3, 0, NEG16(7 << isa)), /* bne $v1, $zero, loop */ + MIPS32_ADDU(isa, 4, 8, 0), /* addu $a0, $t0, $zero */ + /* ncomp */ + MIPS32_BNE(isa, 10, 11, NEG16(16 << isa)), /* bne $t2, $t3, nbyte */ + MIPS32_ADDIU(isa, 11, 11, 1), /* addiu $t3, $t3, 1 */ + MIPS32_SDBBP(isa), }; /* make sure we have a working area */ if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++) - target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]); + pracc_swap16_array(ejtag_info, mips_crc_code, ARRAY_SIZE(mips_crc_code)); + + /* convert mips crc code into a buffer in target endianness */ + uint8_t mips_crc_code_8[sizeof(mips_crc_code)]; + target_buffer_set_u32_array(target, mips_crc_code_8, + ARRAY_SIZE(mips_crc_code), mips_crc_code); + + int retval = target_write_buffer(target, crc_algorithm->address, sizeof(mips_crc_code), mips_crc_code_8); + if (retval != ERROR_OK) + return retval; mips32_info.common_magic = MIPS32_COMMON_MAGIC; - mips32_info.isa_mode = MIPS32_ISA_MIPS32; + mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32; /* run isa as in debug mode */ - init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT); + init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); - init_reg_param(®_params[1], "a1", 32, PARAM_OUT); + init_reg_param(®_params[1], "r5", 32, PARAM_OUT); buf_set_u32(reg_params[1].value, 0, 32, count); int timeout = 20000 * (1 + (count / (1024 * 1024))); - retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout, - &mips32_info); - if (retval != ERROR_OK) { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - target_free_working_area(target, crc_algorithm); - return retval; - } + retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, + crc_algorithm->address + (sizeof(mips_crc_code) - 4), timeout, &mips32_info); - *checksum = buf_get_u32(reg_params[0].value, 0, 32); + if (retval == ERROR_OK) + *checksum = buf_get_u32(reg_params[0].value, 0, 32); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); target_free_working_area(target, crc_algorithm); - return ERROR_OK; + return retval; } -/** Checks whether a memory region is zeroed. */ +/** Checks whether a memory region is erased. */ int mips32_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *blank) + struct target_memory_check_block *blocks, int num_blocks, + uint8_t erased_value) { struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; struct mips32_algorithm mips32_info; - int retval; - uint32_t i; - static const uint32_t erase_check_code[] = { + struct mips32_common *mips32 = target_to_mips32(target); + struct mips_ejtag *ejtag_info = &mips32->ejtag_info; + + if (erased_value != 0xff) { + LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for MIPS32", + erased_value); + return ERROR_FAIL; + } + uint32_t isa = ejtag_info->isa ? 1 : 0; + uint32_t erase_check_code[] = { /* nbyte: */ - 0x80880000, /* lb $t0, ($a0) */ - 0x00C83024, /* and $a2, $a2, $t0 */ - 0x24A5FFFF, /* addiu $a1, $a1, -1 */ - 0x14A0FFFC, /* bne $a1, $zero, nbyte */ - 0x24840001, /* addiu $a0, $a0, 1 */ - 0x7000003F /* sdbbp */ + MIPS32_LB(isa, 8, 0, 4), /* lb $t0, ($a0) */ + MIPS32_AND(isa, 6, 6, 8), /* and $a2, $a2, $t0 */ + MIPS32_ADDIU(isa, 5, 5, NEG16(1)), /* addiu $a1, $a1, -1 */ + MIPS32_BNE(isa, 5, 0, NEG16(4 << isa)), /* bne $a1, $zero, nbyte */ + MIPS32_ADDIU(isa, 4, 4, 1), /* addiu $a0, $a0, 1 */ + MIPS32_SDBBP(isa) /* sdbbp */ }; /* make sure we have a working area */ if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) { - target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), - erase_check_code[i]); - } + pracc_swap16_array(ejtag_info, erase_check_code, ARRAY_SIZE(erase_check_code)); + + /* convert erase check code into a buffer in target endianness */ + uint8_t erase_check_code_8[sizeof(erase_check_code)]; + target_buffer_set_u32_array(target, erase_check_code_8, + ARRAY_SIZE(erase_check_code), erase_check_code); + + int retval = target_write_buffer(target, erase_check_algorithm->address, + sizeof(erase_check_code), erase_check_code_8); + if (retval != ERROR_OK) + goto cleanup; mips32_info.common_magic = MIPS32_COMMON_MAGIC; - mips32_info.isa_mode = MIPS32_ISA_MIPS32; + mips32_info.isa_mode = isa ? MIPS32_ISA_MMIPS32 : MIPS32_ISA_MIPS32; - init_reg_param(®_params[0], "a0", 32, PARAM_OUT); - buf_set_u32(reg_params[0].value, 0, 32, address); + init_reg_param(®_params[0], "r4", 32, PARAM_OUT); + buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address); - init_reg_param(®_params[1], "a1", 32, PARAM_OUT); - buf_set_u32(reg_params[1].value, 0, 32, count); + init_reg_param(®_params[1], "r5", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size); - init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT); - buf_set_u32(reg_params[2].value, 0, 32, 0xff); - - retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - erase_check_algorithm->address, - erase_check_algorithm->address + (sizeof(erase_check_code)-4), - 10000, &mips32_info); - if (retval != ERROR_OK) { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - target_free_working_area(target, erase_check_algorithm); - return retval; - } + init_reg_param(®_params[2], "r6", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, erased_value); + + retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address, + erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &mips32_info); - *blank = buf_get_u32(reg_params[2].value, 0, 32); + if (retval == ERROR_OK) + blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); destroy_reg_param(®_params[2]); +cleanup: target_free_working_area(target, erase_check_algorithm); - return ERROR_OK; + if (retval != ERROR_OK) + return retval; + + return 1; /* only one block has been checked */ } -static int mips32_verify_pointer(struct command_context *cmd_ctx, +static int mips32_verify_pointer(struct command_invocation *cmd, struct mips32_common *mips32) { if (mips32->common_magic != MIPS32_COMMON_MAGIC) { - command_print(cmd_ctx, "target is not an MIPS32"); + command_print(cmd, "target is not an MIPS32"); return ERROR_TARGET_INVALID; } return ERROR_OK; @@ -766,12 +927,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command) struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - retval = mips32_verify_pointer(CMD_CTX, mips32); + retval = mips32_verify_pointer(CMD, mips32); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -788,12 +949,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command) retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); if (retval != ERROR_OK) { - command_print(CMD_CTX, + command_print(CMD, "couldn't access reg %" PRIi32, cp0_reg); return ERROR_OK; } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, + command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, cp0_reg, cp0_sel, value); } else if (CMD_ARGC == 3) { @@ -801,12 +962,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); if (retval != ERROR_OK) { - command_print(CMD_CTX, + command_print(CMD, "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32, cp0_reg, cp0_sel); return ERROR_OK; } - command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, + command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, cp0_reg, cp0_sel, value); } } @@ -825,13 +986,13 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command) else if (CMD_ARGC > 1) return ERROR_COMMAND_SYNTAX_ERROR; - command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay); - if (ejtag_info->scan_delay >= 2000000) { + command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay); + if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) { ejtag_info->mode = 0; - command_print(CMD_CTX, "running in legacy mode"); + command_print(CMD, "running in legacy mode"); } else { ejtag_info->mode = 1; - command_print(CMD_CTX, "running in fast queued mode"); + command_print(CMD, "running in fast queued mode"); } return ERROR_OK;