X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fhla_target.c;h=60ed7d64df1749014ff8d83b4466333d36181b6c;hp=73b7ca3d0e8a005a4be1a28607f0cea5f3c38c7d;hb=21687eb983a4d5e30cd9c4050b9ebce2f3b280c7;hpb=85ed6ea59fdc3cc15de33f95f04441b75b9439bf diff --git a/src/target/hla_target.c b/src/target/hla_target.c index 73b7ca3d0e..60ed7d64df 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -5,6 +5,8 @@ * Copyright (C) 2011 by Spencer Oliver * * spen@spen-soft.co.uk * * * + * revised: 4/25/13 by brent@mbari.org [DCC target request support] * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -16,9 +18,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -37,9 +37,12 @@ #include "armv7m.h" #include "cortex_m.h" #include "arm_semihosting.h" +#include "target_request.h" + +#define savedDCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */ -#define ARMV7M_SCS_DCRSR 0xe000edf4 -#define ARMV7M_SCS_DCRDR 0xe000edf8 +#define ARMV7M_SCS_DCRSR DCB_DCRSR +#define ARMV7M_SCS_DCRDR DCB_DCRDR static inline struct hl_interface_s *target_to_adapter(struct target *target) { @@ -61,7 +64,7 @@ static int adapter_load_core_reg_u32(struct target *target, switch (num) { case 0 ... 18: /* read a normal core register */ - retval = adapter->layout->api->read_reg(adapter->fd, num, value); + retval = adapter->layout->api->read_reg(adapter->handle, num, value); if (retval != ERROR_OK) { LOG_ERROR("JTAG failure %i", retval); @@ -70,11 +73,6 @@ static int adapter_load_core_reg_u32(struct target *target, LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); break; - case ARMV7M_FPSID: - case ARMV7M_FPEXC: - *value = 0; - break; - case ARMV7M_FPSCR: /* Floating-point Status and Registers */ retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33); @@ -83,7 +81,7 @@ static int adapter_load_core_reg_u32(struct target *target, retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value); if (retval != ERROR_OK) return retval; - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); + LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value); break; case ARMV7M_S0 ... ARMV7M_S31: @@ -94,11 +92,8 @@ static int adapter_load_core_reg_u32(struct target *target, retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value); if (retval != ERROR_OK) return retval; - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); - break; - - case ARMV7M_D0 ... ARMV7M_D15: - value = 0; + LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32, + (int)(num - ARMV7M_S0), *value); break; case ARMV7M_PRIMASK: @@ -109,7 +104,7 @@ static int adapter_load_core_reg_u32(struct target *target, * in one Debug Core register. So say r0 and r2 docs; * it was removed from r1 docs, but still works. */ - retval = adapter->layout->api->read_reg(adapter->fd, 20, value); + retval = adapter->layout->api->read_reg(adapter->handle, 20, value); if (retval != ERROR_OK) return retval; @@ -152,41 +147,25 @@ static int adapter_store_core_reg_u32(struct target *target, LOG_DEBUG("%s", __func__); -#ifdef ARMV7_GDB_HACKS - /* If the LR register is being modified, make sure it will put us - * in "thumb" mode, or an INVSTATE exception will occur. This is a - * hack to deal with the fact that gdb will sometimes "forge" - * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) - * Valid exception return codes have bit 0 set too. - */ - if (num == ARMV7M_R14) - value |= 0x01; -#endif - /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register * Selector values for R0..R15, xPSR, MSP, and PSP. */ switch (num) { case 0 ... 18: - retval = adapter->layout->api->write_reg(adapter->fd, num, value); + retval = adapter->layout->api->write_reg(adapter->handle, num, value); if (retval != ERROR_OK) { struct reg *r; LOG_ERROR("JTAG failure"); - r = armv7m->core_cache->reg_list + num; + r = armv7m->arm.core_cache->reg_list + num; r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); break; - case ARMV7M_FPSID: - case ARMV7M_FPEXC: - break; - case ARMV7M_FPSCR: /* Floating-point Status and Registers */ retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value); @@ -195,7 +174,7 @@ static int adapter_store_core_reg_u32(struct target *target, retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16)); if (retval != ERROR_OK) return retval; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); + LOG_DEBUG("write FPSCR value 0x%" PRIx32, value); break; case ARMV7M_S0 ... ARMV7M_S31: @@ -206,10 +185,8 @@ static int adapter_store_core_reg_u32(struct target *target, retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16)); if (retval != ERROR_OK) return retval; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - break; - - case ARMV7M_D0 ... ARMV7M_D15: + LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32, + (int)(num - ARMV7M_S0), value); break; case ARMV7M_PRIMASK: @@ -221,7 +198,7 @@ static int adapter_store_core_reg_u32(struct target *target, * it was removed from r1 docs, but still works. */ - adapter->layout->api->read_reg(adapter->fd, 20, ®); + adapter->layout->api->read_reg(adapter->handle, 20, ®); switch (num) { case ARMV7M_PRIMASK: @@ -241,7 +218,7 @@ static int adapter_store_core_reg_u32(struct target *target, break; } - adapter->layout->api->write_reg(adapter->fd, 20, reg); + adapter->layout->api->write_reg(adapter->handle, 20, reg); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); break; @@ -263,15 +240,104 @@ static int adapter_examine_debug_reason(struct target *target) return ERROR_OK; } +static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl) +{ + uint16_t dcrdr; + int retval = hl_if->layout->api->read_mem(hl_if->handle, + DCB_DCRDR, 1, sizeof(dcrdr), (uint8_t *)&dcrdr); + if (retval == ERROR_OK) { + *ctrl = (uint8_t)dcrdr; + *value = (uint8_t)(dcrdr >> 8); + + LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl); + + if (dcrdr & 1) { + /* write ack back to software dcc register + * to signify we have read data */ + /* atomically clear just the byte containing the busy bit */ + static const uint8_t zero; + retval = hl_if->layout->api->write_mem(hl_if->handle, DCB_DCRDR, 1, 1, &zero); + } + } + return retval; +} + +static int hl_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) +{ + struct hl_interface_s *hl_if = target_to_adapter(target); + uint8_t data; + uint8_t ctrl; + uint32_t i; + + for (i = 0; i < (size * 4); i++) { + int err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + + buffer[i] = data; + } + + return ERROR_OK; +} + +static int hl_handle_target_request(void *priv) +{ + struct target *target = priv; + int err; + + if (!target_was_examined(target)) + return ERROR_OK; + struct hl_interface_s *hl_if = target_to_adapter(target); + + if (!target->dbg_msg_enabled) + return ERROR_OK; + + if (target->state == TARGET_RUNNING) { + uint8_t data; + uint8_t ctrl; + + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + + /* check if we have data */ + if (ctrl & (1 << 0)) { + uint32_t request; + + /* we assume target is quick enough */ + request = data; + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + + request |= (data << 8); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + + request |= (data << 16); + err = hl_dcc_read(hl_if, &data, &ctrl); + if (err != ERROR_OK) + return err; + + request |= (data << 24); + target_request(target, request); + } + } + + return ERROR_OK; +} + static int adapter_init_arch_info(struct target *target, - struct cortex_m3_common *cortex_m3, + struct cortex_m_common *cortex_m, struct jtag_tap *tap) { struct armv7m_common *armv7m; LOG_DEBUG("%s", __func__); - armv7m = &cortex_m3->armv7m; + armv7m = &cortex_m->armv7m; armv7m_init_arch_info(target, armv7m); armv7m->load_core_reg_u32 = adapter_load_core_reg_u32; @@ -280,6 +346,9 @@ static int adapter_init_arch_info(struct target *target, armv7m->examine_debug_reason = adapter_examine_debug_reason; armv7m->stlink = true; + target_register_timer_callback(hl_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); + return ERROR_OK; } @@ -289,7 +358,7 @@ static int adapter_init_target(struct command_context *cmd_ctx, LOG_DEBUG("%s", __func__); armv7m_build_reg_cache(target); - + arm_semihosting_init(target); return ERROR_OK; } @@ -297,13 +366,19 @@ static int adapter_target_create(struct target *target, Jim_Interp *interp) { LOG_DEBUG("%s", __func__); - - struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common)); - - if (!cortex_m3) + struct adiv5_private_config *pc = target->private_config; + if (pc != NULL && pc->ap_num > 0) { + LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)"); return ERROR_COMMAND_SYNTAX_ERROR; + } - adapter_init_arch_info(target, cortex_m3, target->tap); + struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common)); + if (cortex_m == NULL) { + LOG_ERROR("No memory creating target"); + return ERROR_FAIL; + } + + adapter_init_arch_info(target, cortex_m, target->tap); return ERROR_OK; } @@ -311,11 +386,13 @@ static int adapter_target_create(struct target *target, static int adapter_load_context(struct target *target) { struct armv7m_common *armv7m = target_to_armv7m(target); - int num_regs = armv7m->core_cache->num_regs; + int num_regs = armv7m->arm.core_cache->num_regs; for (int i = 0; i < num_regs; i++) { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + + struct reg *r = &armv7m->arm.core_cache->reg_list[i]; + if (!r->valid) + armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY); } return ERROR_OK; @@ -330,6 +407,11 @@ static int adapter_debug_entry(struct target *target) uint32_t xPSR; int retval; + /* preserve the DCRDR across halts */ + retval = target_read_u32(target, DCB_DCRDR, &target->savedDCRDR); + if (retval != ERROR_OK) + return retval; + retval = armv7m->examine_debug_reason(target); if (retval != ERROR_OK) return retval; @@ -337,9 +419,9 @@ static int adapter_debug_entry(struct target *target) adapter_load_context(target); /* make sure we clear the vector catch bit */ - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA); + adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA); - r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + r = arm->cpsr; xPSR = buf_get_u32(r->value, 0, 32); /* Are we in an exception handler */ @@ -368,7 +450,7 @@ static int adapter_debug_entry(struct target *target) LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s", arm_mode_name(arm->core_mode), - *(uint32_t *)(arm->pc->value), + buf_get_u32(arm->pc->value, 0, 32), target_state_name(target)); return retval; @@ -379,29 +461,39 @@ static int adapter_poll(struct target *target) enum target_state state; struct hl_interface_s *adapter = target_to_adapter(target); struct armv7m_common *armv7m = target_to_armv7m(target); + enum target_state prev_target_state = target->state; - state = adapter->layout->api->state(adapter->fd); + state = adapter->layout->api->state(adapter->handle); if (state == TARGET_UNKNOWN) { LOG_ERROR("jtag status contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - if (target->state == state) + if (prev_target_state == state) + return ERROR_OK; + + if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING) return ERROR_OK; + target->state = state; + if (state == TARGET_HALTED) { - target->state = state; int retval = adapter_debug_entry(target); if (retval != ERROR_OK) return retval; - if (arm_semihosting(target, &retval) != 0) - return retval; + if (prev_target_state == TARGET_DEBUG_RUNNING) { + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + } else { + if (arm_semihosting(target, &retval) != 0) + return retval; + + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32)); + LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32)); } return ERROR_OK; @@ -420,24 +512,25 @@ static int adapter_assert_reset(struct target *target) bool srst_asserted = false; - if (jtag_reset_config & RESET_SRST_NO_GATING) { + if ((jtag_reset_config & RESET_HAS_SRST) && + (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); - res = adapter->layout->api->assert_srst(adapter->fd, 0); + res = adapter->layout->api->assert_srst(adapter->handle, 0); srst_asserted = true; } - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN); + adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN); /* only set vector catch if halt is requested */ if (target->reset_halt) - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET); + adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET); else - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA); + adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA); if (jtag_reset_config & RESET_HAS_SRST) { if (!srst_asserted) { jtag_add_reset(0, 1); - res = adapter->layout->api->assert_srst(adapter->fd, 0); + res = adapter->layout->api->assert_srst(adapter->handle, 0); } if (res == ERROR_COMMAND_NOTFOUND) LOG_ERROR("Hardware srst not supported, falling back to software reset"); @@ -449,16 +542,16 @@ static int adapter_assert_reset(struct target *target) if (use_srst_fallback) { /* stlink v1 api does not support hardware srst, so we use a software reset fallback */ - adapter->layout->api->write_debug_reg(adapter->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + adapter->layout->api->write_debug_reg(adapter->handle, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); } - res = adapter->layout->api->reset(adapter->fd); + res = adapter->layout->api->reset(adapter->handle); if (res != ERROR_OK) return res; /* registers are now invalid */ - register_cache_invalidate(armv7m->core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (target->reset_halt) { target->state = TARGET_RESET; @@ -472,7 +565,6 @@ static int adapter_assert_reset(struct target *target) static int adapter_deassert_reset(struct target *target) { - int res; struct hl_interface_s *adapter = target_to_adapter(target); enum reset_types jtag_reset_config = jtag_get_reset_config(); @@ -480,27 +572,16 @@ static int adapter_deassert_reset(struct target *target) LOG_DEBUG("%s", __func__); if (jtag_reset_config & RESET_HAS_SRST) - adapter->layout->api->assert_srst(adapter->fd, 1); + adapter->layout->api->assert_srst(adapter->handle, 1); /* virtual deassert reset, we need it for the internal * jtag state machine */ jtag_add_reset(0, 0); - if (!target->reset_halt) { - res = target_resume(target, 1, 0, 0, 0); - - if (res != ERROR_OK) - return res; - } + target->savedDCRDR = 0; /* clear both DCC busy bits on initial resume */ - return ERROR_OK; -} - -static int adapter_soft_reset_halt(struct target *target) -{ - LOG_DEBUG("%s", __func__); - return ERROR_OK; + return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0); } static int adapter_halt(struct target *target) @@ -518,7 +599,7 @@ static int adapter_halt(struct target *target) if (target->state == TARGET_UNKNOWN) LOG_WARNING("target was in unknown state when halt was requested"); - res = adapter->layout->api->halt(adapter->fd); + res = adapter->layout->api->halt(adapter->handle); if (res != ERROR_OK) return res; @@ -529,7 +610,7 @@ static int adapter_halt(struct target *target) } static int adapter_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, + target_addr_t address, int handle_breakpoints, int debug_execution) { int res; @@ -539,8 +620,8 @@ static int adapter_resume(struct target *target, int current, struct breakpoint *breakpoint = NULL; struct reg *pc; - LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address, - handle_breakpoints, debug_execution); + LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current, + address, handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -549,8 +630,8 @@ static int adapter_resume(struct target *target, int current, if (!debug_execution) { target_free_all_working_areas(target); - cortex_m3_enable_breakpoints(target); - cortex_m3_enable_watchpoints(target); + cortex_m_enable_breakpoints(target); + cortex_m_enable_watchpoints(target); } pc = armv7m->arm.pc; @@ -574,43 +655,53 @@ static int adapter_resume(struct target *target, int current, armv7m_restore_context(target); + /* restore savedDCRDR */ + res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR); + if (res != ERROR_OK) + return res; + /* registers are now invalid */ - register_cache_invalidate(armv7m->core_cache); + register_cache_invalidate(armv7m->arm.core_cache); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { /* Single step past breakpoint at current address */ breakpoint = breakpoint_find(target, resume_pc); if (breakpoint) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")", breakpoint->address, breakpoint->unique_id); - cortex_m3_unset_breakpoint(target, breakpoint); + cortex_m_unset_breakpoint(target, breakpoint); - res = adapter->layout->api->step(adapter->fd); + res = adapter->layout->api->step(adapter->handle); if (res != ERROR_OK) return res; - cortex_m3_set_breakpoint(target, breakpoint); + cortex_m_set_breakpoint(target, breakpoint); } } - res = adapter->layout->api->run(adapter->fd); + res = adapter->layout->api->run(adapter->handle); if (res != ERROR_OK) return res; - target->state = TARGET_RUNNING; target->debug_reason = DBG_REASON_NOTHALTED; - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if (!debug_execution) { + target->state = TARGET_RUNNING; + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + } else { + target->state = TARGET_DEBUG_RUNNING; + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); + } return ERROR_OK; } static int adapter_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + target_addr_t address, int handle_breakpoints) { int res; struct hl_interface_s *adapter = target_to_adapter(target); @@ -638,7 +729,7 @@ static int adapter_step(struct target *target, int current, if (handle_breakpoints) { breakpoint = breakpoint_find(target, pc_value); if (breakpoint) - cortex_m3_unset_breakpoint(target, breakpoint); + cortex_m_unset_breakpoint(target, breakpoint); } armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found); @@ -647,134 +738,69 @@ static int adapter_step(struct target *target, int current, armv7m_restore_context(target); + /* restore savedDCRDR */ + res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR); + if (res != ERROR_OK) + return res; + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - res = adapter->layout->api->step(adapter->fd); + res = adapter->layout->api->step(adapter->handle); if (res != ERROR_OK) return res; /* registers are now invalid */ - register_cache_invalidate(armv7m->core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (breakpoint) - cortex_m3_set_breakpoint(target, breakpoint); + cortex_m_set_breakpoint(target, breakpoint); adapter_debug_entry(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32)); + LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32)); return ERROR_OK; } -static int adapter_read_memory(struct target *target, uint32_t address, +static int adapter_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct hl_interface_s *adapter = target_to_adapter(target); - int res; - uint32_t buffer_threshold = (adapter->param.max_buffer / 4); - uint32_t addr_increment = 4; - uint32_t c; if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count); + LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32, + __func__, address, size, count); - /* prepare byte count, buffer threshold - * and address increment for none 32bit access - */ - if (size != 4) { - count *= size; - buffer_threshold = (adapter->param.max_buffer / 4) / 2; - addr_increment = 1; - } - - while (count) { - if (count > buffer_threshold) - c = buffer_threshold; - else - c = count; - - if (size != 4) - res = adapter->layout->api->read_mem8(adapter->fd, - address, c, buffer); - else - res = adapter->layout->api->read_mem32(adapter->fd, - address, c, buffer); - - if (res != ERROR_OK) - return res; - - address += (c * addr_increment); - buffer += (c * addr_increment); - count -= c; - } - - return ERROR_OK; + return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer); } -static int adapter_write_memory(struct target *target, uint32_t address, +static int adapter_write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct hl_interface_s *adapter = target_to_adapter(target); - int res; - uint32_t buffer_threshold = (adapter->param.max_buffer / 4); - uint32_t addr_increment = 4; - uint32_t c; if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; - LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count); - - /* prepare byte count, buffer threshold - * and address increment for none 32bit access - */ - if (size != 4) { - count *= size; - buffer_threshold = (adapter->param.max_buffer / 4) / 2; - addr_increment = 1; - } - - while (count) { - if (count > buffer_threshold) - c = buffer_threshold; - else - c = count; - - if (size != 4) - res = adapter->layout->api->write_mem8(adapter->fd, - address, c, buffer); - else - res = adapter->layout->api->write_mem32(adapter->fd, - address, c, buffer); - - if (res != ERROR_OK) - return res; - - address += (c * addr_increment); - buffer += (c * addr_increment); - count -= c; - } - - return ERROR_OK; -} + LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32, + __func__, address, size, count); -static int adapter_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, - const uint8_t *buffer) -{ - return adapter_write_memory(target, address, 4, count, buffer); + return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer); } static const struct command_registration adapter_command_handlers[] = { { .chain = arm_command_handlers, }, + { + .chain = armv7m_trace_command_handlers, + }, COMMAND_REGISTRATION_DONE }; @@ -783,26 +809,28 @@ struct target_type hla_target = { .deprecated_name = "stm32_stlink", .init_target = adapter_init_target, + .deinit_target = cortex_m_deinit_target, .target_create = adapter_target_create, - .examine = cortex_m3_examine, + .target_jim_configure = adiv5_jim_configure, + .examine = cortex_m_examine, .commands = adapter_command_handlers, .poll = adapter_poll, .arch_state = armv7m_arch_state, + .target_request_data = hl_target_request_data, .assert_reset = adapter_assert_reset, .deassert_reset = adapter_deassert_reset, - .soft_reset_halt = adapter_soft_reset_halt, .halt = adapter_halt, .resume = adapter_resume, .step = adapter_step, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = armv7m_get_gdb_reg_list, .read_memory = adapter_read_memory, .write_memory = adapter_write_memory, - .bulk_write_memory = adapter_bulk_write_memory, .checksum_memory = armv7m_checksum_memory, .blank_check_memory = armv7m_blank_check_memory, @@ -810,8 +838,9 @@ struct target_type hla_target = { .start_algorithm = armv7m_start_algorithm, .wait_algorithm = armv7m_wait_algorithm, - .add_breakpoint = cortex_m3_add_breakpoint, - .remove_breakpoint = cortex_m3_remove_breakpoint, - .add_watchpoint = cortex_m3_add_watchpoint, - .remove_watchpoint = cortex_m3_remove_watchpoint, + .add_breakpoint = cortex_m_add_breakpoint, + .remove_breakpoint = cortex_m_remove_breakpoint, + .add_watchpoint = cortex_m_add_watchpoint, + .remove_watchpoint = cortex_m_remove_watchpoint, + .profiling = cortex_m_profiling, };