X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fhla_target.c;h=11926c78dd138291b10c093ead5bb9168d0cb426;hp=3c3b84175704acc6ca84e9f3ff3f4da5b5e19ee1;hb=fc2abe63fd3cea7497da7be2955d333bd3f800b9;hpb=561984c8f672b5b35a78e80529107ec0599fc037 diff --git a/src/target/hla_target.c b/src/target/hla_target.c index 3c3b841757..11926c78dd 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -339,25 +339,23 @@ static int adapter_debug_entry(struct target *target) adapter_load_context(target); /* make sure we clear the vector catch bit */ - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0); + adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA); r = armv7m->core_cache->reg_list + ARMV7M_xPSR; xPSR = buf_get_u32(r->value, 0, 32); /* Are we in an exception handler */ if (xPSR & 0x1FF) { - armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { - unsigned control = buf_get_u32(armv7m->core_cache + unsigned control = buf_get_u32(arm->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 2); /* is this thread privileged? */ - armv7m->core_mode = control & 1; - arm->core_mode = armv7m->core_mode + arm->core_mode = control & 1 ? ARM_MODE_USER_THREAD : ARM_MODE_THREAD; @@ -371,7 +369,7 @@ static int adapter_debug_entry(struct target *target) } LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s", - armv7m_mode_strings[armv7m->core_mode], + arm_mode_name(arm->core_mode), *(uint32_t *)(arm->pc->value), target_state_name(target)); @@ -434,9 +432,9 @@ static int adapter_assert_reset(struct target *target) /* only set vector catch if halt is requested */ if (target->reset_halt) - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, VC_CORERESET); + adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET); else - adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, 0); + adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA); if (jtag_reset_config & RESET_HAS_SRST) { if (!srst_asserted) { @@ -571,6 +569,11 @@ static int adapter_resume(struct target *target, int current, resume_pc = buf_get_u32(pc->value, 0, 32); + /* write any user vector flags */ + res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr); + if (res != ERROR_OK) + return res; + armv7m_restore_context(target); /* registers are now invalid */ @@ -671,11 +674,11 @@ static int adapter_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { + struct hl_interface_s *adapter = target_to_adapter(target); int res; - uint32_t buffer_threshold = 128; + uint32_t buffer_threshold = (adapter->param.max_buffer / 4); uint32_t addr_increment = 4; uint32_t c; - struct hl_interface_s *adapter = target_to_adapter(target); if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; @@ -687,7 +690,7 @@ static int adapter_read_memory(struct target *target, uint32_t address, */ if (size != 4) { count *= size; - buffer_threshold = 64; + buffer_threshold = (adapter->param.max_buffer / 4) / 2; addr_increment = 1; } @@ -719,11 +722,11 @@ static int adapter_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { + struct hl_interface_s *adapter = target_to_adapter(target); int res; - uint32_t buffer_threshold = 128; + uint32_t buffer_threshold = (adapter->param.max_buffer / 4); uint32_t addr_increment = 4; uint32_t c; - struct hl_interface_s *adapter = target_to_adapter(target); if (!count || !buffer) return ERROR_COMMAND_SYNTAX_ERROR; @@ -735,7 +738,7 @@ static int adapter_write_memory(struct target *target, uint32_t address, */ if (size != 4) { count *= size; - buffer_threshold = 64; + buffer_threshold = (adapter->param.max_buffer / 4) / 2; addr_increment = 1; }