X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=cf034c428963a9011f3e077e9a41d5629a1d66a6;hp=5a45f2fd4b6ded9fd7b978ce3b23dbb390878f76;hb=af949b2531d2a8863d077025db40cbb170d13a63;hpb=6468859389d25b24ee3c569935c46eae5d1a580d

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 5a45f2fd4b..cf034c4289 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2008 by Marvell Semiconductors, Inc.                    *
+ *   Copyright (C) 2008-2009 by Marvell Semiconductors, Inc.                    *
  *   Written by Nicolas Pitre <nico@marvell.com>                           *
  *                                                                         *
  *   Copyright (C) 2008 by Hongtao Zheng                                   *
@@ -22,10 +22,10 @@
  ***************************************************************************/
 
 /*
- * Marvell Feroceon support, including Orion and Kirkwood SOCs.
+ * Marvell Feroceon/Dragonite support.
  *
- * The Feroceon core mimics the ARM926 ICE interface with the following
- * differences:
+ * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others,
+ * mimics the ARM926 ICE interface with the following differences:
  *
  * - the MOE (method of entry) reporting is not implemented
  *
@@ -43,6 +43,9 @@
  *
  * - the DCC channel is half duplex (only one FIFO for both directions) with
  *   seemingly no proper flow control.
+ *
+ * The Dragonite core is the non-mmu version based on the ARM966 model, and
+ * it shares the above issues as well.
  */
 
 #ifdef HAVE_CONFIG_H
@@ -50,19 +53,13 @@
 #endif
 
 #include "arm926ejs.h"
+#include "arm966e.h"
 #include "target_type.h"
 
-
-int feroceon_examine(struct target_s *target);
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp);
-int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
-int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int feroceon_quit(void);
-
 int feroceon_assert_reset(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 	int ud = arm7_9->use_dbgrq;
 
 	arm7_9->use_dbgrq = 0;
@@ -72,59 +69,19 @@ int feroceon_assert_reset(target_t *target)
 	return arm7_9_assert_reset(target);
 }
 
-target_type_t feroceon_target =
+int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 {
-	.name = "feroceon",
-
-	.poll = arm7_9_poll,
-	.arch_state = arm926ejs_arch_state,
-
-	.target_request_data = arm7_9_target_request_data,
-
-	.halt = arm7_9_halt,
-	.resume = arm7_9_resume,
-	.step = arm7_9_step,
-
-	.assert_reset = feroceon_assert_reset,
-	.deassert_reset = arm7_9_deassert_reset,
-	.soft_reset_halt = arm926ejs_soft_reset_halt,
-
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
-	.read_memory = arm7_9_read_memory,
-	.write_memory = arm926ejs_write_memory,
-	.bulk_write_memory = feroceon_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
-
-	.run_algorithm = armv4_5_run_algorithm,
-
-	.add_breakpoint = arm7_9_add_breakpoint,
-	.remove_breakpoint = arm7_9_remove_breakpoint,
-	.add_watchpoint = arm7_9_add_watchpoint,
-	.remove_watchpoint = arm7_9_remove_watchpoint,
-
-	.register_commands = arm926ejs_register_commands,
-	.target_create = feroceon_target_create,
-	.init_target = feroceon_init_target,
-	.examine = feroceon_examine,
-	.quit = feroceon_quit
-};
-
-
-int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
-{
-	scan_field_t fields[3];
-	u8 out_buf[4];
-	u8 instr_buf[4];
-	u8 sysspeed_buf = 0x0;
+	struct scan_field fields[3];
+	uint8_t out_buf[4];
+	uint8_t instr_buf[4];
+	uint8_t sysspeed_buf = 0x0;
 
 	/* prepare buffer */
 	buf_set_u32(out_buf, 0, 32, 0);
 
 	buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-	jtag_add_end_state(TAP_DRPAUSE);
+	jtag_set_end_state(TAP_DRPAUSE);
 	arm_jtag_scann(jtag_info, 0x1);
 
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@@ -132,45 +89,30 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
-	
 	fields[0].in_value = NULL;
-	
-	
-	
-	
 
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = &sysspeed_buf;
-	
 	fields[1].in_value = NULL;
-	
-	
-	
-	
 
 	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = instr_buf;
-	
 	fields[2].in_value = NULL;
-	
-	
-	
-	
 
-	jtag_add_dr_scan(3, fields, jtag_add_end_state(TAP_INVALID));
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-	/* no jtag_add_runtest(0, jtag_add_end_state(TAP_INVALID)) here */
+	/* no jtag_add_runtest(0, jtag_get_end_state()) here */
 
 	return ERROR_OK;
 }
 
-void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/*
 	 * save r0 before using it and put system in ARM state
@@ -212,12 +154,12 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 	*pc -= (12 + 4);
 }
 
-void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 {
 	int i;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -231,16 +173,16 @@ void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
 {
 	int i;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 	int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
-	u32 *buf_u32 = buffer;
-	u16 *buf_u16 = buffer;
-	u8 *buf_u8 = buffer;
+	uint32_t *buf_u32 = buffer;
+	uint16_t *buf_u16 = buffer;
+	uint8_t *buf_u8 = buffer;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -268,11 +210,11 @@ void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -291,13 +233,13 @@ void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
+void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -332,11 +274,11 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
+void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 
@@ -349,12 +291,12 @@ void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 {
 	int i;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -371,9 +313,9 @@ void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 
 void feroceon_branch_resume(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -388,12 +330,11 @@ void feroceon_branch_resume_thumb(target_t *target)
 {
 	LOG_DEBUG("-");
 
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-	u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-	u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
-	(void)(r0); // use R0...
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
+	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
+	uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -409,7 +350,7 @@ void feroceon_branch_resume_thumb(target_t *target)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
-	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0);
+	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 
@@ -420,11 +361,11 @@ void feroceon_branch_resume_thumb(target_t *target)
 	arm7_9->need_bypass_before_restart = 1;
 }
 
-int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
+int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 	int err;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
@@ -442,11 +383,11 @@ int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32
 	return jtag_execute_queue();
 }
 
-int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
+int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
+	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -463,18 +404,18 @@ int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 
 void feroceon_set_dbgrq(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 	buf_set_u32(dbg_ctrl->value, 0, 8, 2);
 	embeddedice_store_reg(dbg_ctrl);
 }
 
-void feroceon_enable_single_step(target_t *target, u32 next_pc)
+void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
 	/* set a breakpoint there */
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
@@ -486,8 +427,8 @@ void feroceon_enable_single_step(target_t *target, u32 next_pc)
 
 void feroceon_disable_single_step(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
@@ -507,20 +448,20 @@ int feroceon_examine_debug_reason(target_t *target)
 	return ERROR_OK;
 }
 
-int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
+int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	int retval;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 	enum armv4_5_state core_state = armv4_5->core_state;
-	u32 x, flip, shift, save[7];
-	u32 i;
+	uint32_t x, flip, shift, save[7];
+	uint32_t i;
 
 	/*
 	 * We can't use the dcc flow control bits, so let's transfer data
 	 * with 31 bits and flip the MSB each time a new data word is sent.
 	 */
-	static u32 dcc_code[] =
+	static uint32_t dcc_code[] =
 	{
 		0xee115e10,	/* 3:	mrc	p14, 0, r5, c1, c0, 0	*/
 		0xe3a0301e,	/* 1:	mov	r3, #30			*/
@@ -544,7 +485,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 		0xeafffff3,	/*	b	3b			*/
 	};
 
-	u32 dcc_size = sizeof(dcc_code);
+	uint32_t dcc_size = sizeof(dcc_code);
 
 	if (!arm7_9->dcc_downloads)
 		return target_write_memory(target, address, 4, count, buffer);
@@ -552,7 +493,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 	/* regrab previously allocated working_area, or allocate a new one */
 	if (!arm7_9->dcc_working_area)
 	{
-		u8 dcc_code_buf[dcc_size];
+		uint8_t dcc_code_buf[dcc_size];
 
 		/* make sure we have a working area */
 		if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
@@ -566,7 +507,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 			target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
 
 		/* write DCC code to working area */
-		if((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
+		if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -592,8 +533,8 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 	shift = 1;
 	for (i = 0; i < count; i++)
 	{
-		u32 y = target_buffer_get_u32(target, buffer);
-		u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
+		uint32_t y = target_buffer_get_u32(target, buffer);
+		uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
 		x = y << (32 - shift);
 		if (++shift >= 32 || i + 1 >= count)
@@ -606,9 +547,20 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 		buffer += 4;
 	}
 
-	target_halt(target);
-	while (target->state != TARGET_HALTED)
-		target_poll(target);
+	retval = target_halt(target);
+	if (retval == ERROR_OK)
+		retval = target_wait_state(target, TARGET_HALTED, 500);
+	if (retval == ERROR_OK) {
+                uint32_t endaddress =
+			buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
+		if (endaddress != address + count*4) {
+			LOG_ERROR("DCC write failed,"
+				" expected end address 0x%08" PRIx32
+				" got 0x%0" PRIx32 "",
+			       	address + count*4, endaddress);
+			retval = ERROR_FAIL;
+		}
+	}
 
 	/* restore target state */
 	for (i = 0; i <= 5; i++)
@@ -622,7 +574,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
 	armv4_5->core_cache->reg_list[15].dirty = 1;
 	armv4_5->core_state = core_state;
 
-	return ERROR_OK;
+	return retval;
 }
 
 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
@@ -631,21 +583,10 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
 	return ERROR_OK;
 }
 
-int feroceon_quit(void)
-{
-	return ERROR_OK;
-}
-
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+void feroceon_common_setup(struct target_s *target)
 {
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
-	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
-
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
-
-	armv4_5 = target->arch_info;
-	arm7_9 = armv4_5->arch_info;
+	struct arm *armv4_5 = target->arch_info;
+	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 
 	/* override some insn sequence functions */
 	arm7_9->change_to_arm = feroceon_change_to_arm;
@@ -665,10 +606,6 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 	/* MOE is not implemented */
 	arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
 
-	/* the standard ARM926 methods don't always work (don't ask...) */
-	arm926ejs->read_cp15 = feroceon_read_cp15;
-	arm926ejs->write_cp15 = feroceon_write_cp15;
-
 	/* Note: asserting DBGRQ might not win over the undef exception.
 	   If that happens then just use "arm7_9 dbgrq disable". */
 	arm7_9->use_dbgrq = 1;
@@ -677,18 +614,40 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
 	/* only one working comparator */
 	arm7_9->wp_available_max = 1;
 	arm7_9->wp1_used_default = -1;
+}
+
+int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+{
+	struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
+
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
+	feroceon_common_setup(target);
+
+	/* the standard ARM926 methods don't always work (don't ask...) */
+	arm926ejs->read_cp15 = feroceon_read_cp15;
+	arm926ejs->write_cp15 = feroceon_write_cp15;
+
+	return ERROR_OK;
+}
+
+int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
+{
+	struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
+
+	arm966e_init_arch_info(target, arm966e, target->tap);
+	feroceon_common_setup(target);
 
 	return ERROR_OK;
 }
 
 int feroceon_examine(struct target_s *target)
 {
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *armv4_5;
+	struct arm7_9_common *arm7_9;
 	int retval;
 
 	retval = arm9tdmi_examine(target);
-	if (retval!=ERROR_OK)
+	if (retval != ERROR_OK)
 		return retval;
 
 	armv4_5 = target->arch_info;
@@ -714,3 +673,80 @@ int feroceon_examine(struct target_s *target)
 
 	return ERROR_OK;
 }
+
+target_type_t feroceon_target =
+{
+	.name = "feroceon",
+
+	.poll = arm7_9_poll,
+	.arch_state = arm926ejs_arch_state,
+
+	.target_request_data = arm7_9_target_request_data,
+
+	.halt = arm7_9_halt,
+	.resume = arm7_9_resume,
+	.step = arm7_9_step,
+
+	.assert_reset = feroceon_assert_reset,
+	.deassert_reset = arm7_9_deassert_reset,
+	.soft_reset_halt = arm926ejs_soft_reset_halt,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = arm7_9_read_memory,
+	.write_memory = arm926ejs_write_memory,
+	.bulk_write_memory = feroceon_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = arm7_9_add_breakpoint,
+	.remove_breakpoint = arm7_9_remove_breakpoint,
+	.add_watchpoint = arm7_9_add_watchpoint,
+	.remove_watchpoint = arm7_9_remove_watchpoint,
+
+	.register_commands = arm926ejs_register_commands,
+	.target_create = feroceon_target_create,
+	.init_target = feroceon_init_target,
+	.examine = feroceon_examine,
+};
+
+target_type_t dragonite_target =
+{
+	.name = "dragonite",
+
+	.poll = arm7_9_poll,
+	.arch_state = armv4_5_arch_state,
+
+	.target_request_data = arm7_9_target_request_data,
+
+	.halt = arm7_9_halt,
+	.resume = arm7_9_resume,
+	.step = arm7_9_step,
+
+	.assert_reset = feroceon_assert_reset,
+	.deassert_reset = arm7_9_deassert_reset,
+	.soft_reset_halt = arm7_9_soft_reset_halt,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = arm7_9_read_memory,
+	.write_memory = arm7_9_write_memory,
+	.bulk_write_memory = feroceon_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = arm7_9_add_breakpoint,
+	.remove_breakpoint = arm7_9_remove_breakpoint,
+	.add_watchpoint = arm7_9_add_watchpoint,
+	.remove_watchpoint = arm7_9_remove_watchpoint,
+
+	.register_commands = arm966e_register_commands,
+	.target_create = dragonite_target_create,
+	.init_target = feroceon_init_target,
+	.examine = feroceon_examine,
+};
+