X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=407ac52b6c5a6e6f655cfc292039e1e0f0e832d6;hp=0cd632bd77fb3e65cf149d291931801793e1a2b8;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=c4a2fdbc39dd31170e61e7fe0be332826825acbd diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 0cd632bd77..407ac52b6c 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -2,6 +2,9 @@ * Copyright (C) 2008 by Marvell Semiconductors, Inc. * * Written by Nicolas Pitre * * * + * Copyright (C) 2008 by Hongtao Zheng * + * hontor@126.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -49,16 +52,28 @@ #include "arm926ejs.h" #include "jtag.h" #include "log.h" -#include "arm_simulator.h" #include #include - -int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int feroceon_examine(struct target_s *target); +int feroceon_target_create(struct target_s *target, Jim_Interp *interp); int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int feroceon_quit(); +int feroceon_quit(void); + +int feroceon_assert_reset(target_t *target) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + int ud = arm7_9->use_dbgrq; + + arm7_9->use_dbgrq = 0; + if (target->reset_halt) + arm7_9_halt(target); + arm7_9->use_dbgrq = ud; + return arm7_9_assert_reset(target); +} target_type_t feroceon_target = { @@ -73,7 +88,7 @@ target_type_t feroceon_target = .resume = arm7_9_resume, .step = arm7_9_step, - .assert_reset = arm7_9_assert_reset, + .assert_reset = feroceon_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, @@ -83,6 +98,7 @@ target_type_t feroceon_target = .write_memory = arm926ejs_write_memory, .bulk_write_memory = feroceon_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -92,13 +108,67 @@ target_type_t feroceon_target = .remove_watchpoint = arm7_9_remove_watchpoint, .register_commands = arm926ejs_register_commands, - .target_command = feroceon_target_command, + .target_create = feroceon_target_create, .init_target = feroceon_init_target, - .examine = arm9tdmi_examine, + .examine = feroceon_examine, .quit = feroceon_quit }; +int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) +{ + scan_field_t fields[3]; + u8 out_buf[4]; + u8 instr_buf[4]; + u8 sysspeed_buf = 0x0; + + /* prepare buffer */ + buf_set_u32(out_buf, 0, 32, 0); + + buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); + + jtag_add_end_state(TAP_PD); + arm_jtag_scann(jtag_info, 0x1); + + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + + fields[0].tap = jtag_info->tap; + fields[0].num_bits = 32; + fields[0].out_value = out_buf; + fields[0].out_mask = NULL; + fields[0].in_value = NULL; + fields[0].in_handler = NULL; + fields[0].in_handler_priv = NULL; + fields[0].in_check_value = NULL; + fields[0].in_check_mask = NULL; + + fields[1].tap = jtag_info->tap; + fields[1].num_bits = 3; + fields[1].out_value = &sysspeed_buf; + fields[1].out_mask = NULL; + fields[1].in_value = NULL; + fields[1].in_check_value = NULL; + fields[1].in_check_mask = NULL; + fields[1].in_handler = NULL; + fields[1].in_handler_priv = NULL; + + fields[2].tap = jtag_info->tap; + fields[2].num_bits = 32; + fields[2].out_value = instr_buf; + fields[2].out_mask = NULL; + fields[2].in_value = NULL; + fields[2].in_check_value = NULL; + fields[2].in_check_mask = NULL; + fields[2].in_handler = NULL; + fields[2].in_handler_priv = NULL; + + jtag_add_dr_scan(3, fields, -1); + + /* no jtag_add_runtest(0, -1) here */ + + return ERROR_OK; +} + void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -110,9 +180,10 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) * to allow common handling of ARM and THUMB debugging */ - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); + feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP); + feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP); + feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP); + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -138,10 +209,10 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) /* * fix program counter: - * MOV R0, PC was the 10th instruction (+18) + * MOV R0, PC was the 7th instruction (+12) * reading PC in Thumb state gives address of instruction + 4 */ - *pc -= 22; + *pc -= (12 + 4); } void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) @@ -313,9 +384,7 @@ void feroceon_branch_resume(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); - /* need BYPASS before RESTART */ - jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, 0xf, NULL); + arm7_9->need_bypass_before_restart = 1; } void feroceon_branch_resume_thumb(target_t *target) @@ -327,29 +396,23 @@ void feroceon_branch_resume_thumb(target_t *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - - arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc & ~3, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); + (void)(r0); // use R0... arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,r15,#1 */ + arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 1), 0, NULL, 0); + + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0); + + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -357,9 +420,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1); - /* need BYPASS before RESTART */ - jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, 0xf, NULL); + arm7_9->need_bypass_before_restart = 1; } int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) @@ -403,23 +464,20 @@ int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 return arm7_9_execute_sys_speed(target); } -void feroceon_enable_single_step(target_t *target) +void feroceon_set_dbgrq(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - u32 next_pc; + reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - /* calculate PC of next instruction */ - if (arm_simulate_step(target, &next_pc) != ERROR_OK) - { - u32 current_pc, current_opcode; - current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, " - "current opcode is 0x%8.8x", current_opcode); - next_pc = current_pc; - } - arm7_9_restore_context(target); + buf_set_u32(dbg_ctrl->value, 0, 8, 2); + embeddedice_store_reg(dbg_ctrl); +} + +void feroceon_enable_single_step(target_t *target, u32 next_pc) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; /* set a breakpoint there */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc); @@ -454,6 +512,7 @@ int feroceon_examine_debug_reason(target_t *target) int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; enum armv4_5_state core_state = armv4_5->core_state; @@ -510,7 +569,10 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); /* write DCC code to working area */ - target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf); + if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK) + { + return retval; + } } /* backup clobbered processor state */ @@ -568,63 +630,22 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_init_target(cmd_ctx, target); - - armv4_5 = target->arch_info; - arm7_9 = armv4_5->arch_info; - - /* the COMMS_CTRL bits are all contiguous */ - if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) - LOG_ERROR("unexpected Feroceon EICE version signature"); - - arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; - arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_monitor_mode = 1; - - /* vector catch reg is not initialized on reset */ - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0); - - /* clear monitor mode, enable comparators */ - embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - jtag_execute_queue(); - buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - return ERROR_OK; } -int feroceon_quit() +int feroceon_quit(void) { return ERROR_OK; } -int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int feroceon_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; - arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t)); - memset(arm926ejs, 0, sizeof(*arm926ejs)); - - if (argc < 4) - { - LOG_ERROR("'target arm926ejs' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; - - LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); - - arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant); + arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); + + arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant); armv4_5 = target->arch_info; arm7_9 = armv4_5->arch_info; @@ -651,12 +672,49 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char * arm926ejs->read_cp15 = feroceon_read_cp15; arm926ejs->write_cp15 = feroceon_write_cp15; - /* asserting DBGRQ won't win over the undef exception */ - arm7_9->use_dbgrq = 0; + /* Note: asserting DBGRQ might not win over the undef exception. + If that happens then just use "arm7_9 dbgrq disable". */ + arm7_9->use_dbgrq = 1; + arm7_9->set_special_dbgrq = feroceon_set_dbgrq; /* only one working comparator */ - arm7_9->wp_available = 1; - arm7_9->wp1_used = -1; + arm7_9->wp_available_max = 1; + arm7_9->wp1_used_default = -1; + + return ERROR_OK; +} + +int feroceon_examine(struct target_s *target) +{ + armv4_5_common_t *armv4_5; + arm7_9_common_t *arm7_9; + int retval; + + retval = arm9tdmi_examine(target); + if (retval!=ERROR_OK) + return retval; + + armv4_5 = target->arch_info; + arm7_9 = armv4_5->arch_info; + + /* the COMMS_CTRL bits are all contiguous */ + if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) + LOG_ERROR("unexpected Feroceon EICE version signature"); + + arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; + arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_monitor_mode = 1; + + /* vector catch reg is not initialized on reset */ + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0); + + /* clear monitor mode, enable comparators */ + embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); + jtag_execute_queue(); + buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0); + buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); + return ERROR_OK; }