X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Ffa526.c;h=bb9f7353af895e2ddf8944993df5fd26253fb3ae;hp=459293428a721e687dfa6b2b3f996265f904fa10;hb=9f021c2bc129f8f7c659c64ad19531bd8073264a;hpb=42ef503d37b18d907da16d26e99167566d5aabd1 diff --git a/src/target/fa526.c b/src/target/fa526.c index 459293428a..bb9f7353af 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ /* @@ -33,18 +31,19 @@ #include "arm920t.h" #include "target_type.h" +#include "arm_opcodes.h" -static void fa526_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) +static void fa526_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc) { LOG_ERROR("%s: there is no Thumb state on FA526", __func__); } -static void fa526_read_core_regs(target_t *target, - uint32_t mask, uint32_t* core_regs[16]) +static void fa526_read_core_regs(struct target *target, + uint32_t mask, uint32_t *core_regs[16]) { int i; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -58,20 +57,19 @@ static void fa526_read_core_regs(target_t *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ arm9tdmi_clock_data_in(jtag_info, core_regs[i]); } } -static void fa526_read_core_regs_target_buffer(target_t *target, - uint32_t mask, void* buffer, int size) +static void fa526_read_core_regs_target_buffer(struct target *target, + uint32_t mask, void *buffer, int size) { int i; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -89,12 +87,10 @@ static void fa526_read_core_regs_target_buffer(target_t *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -108,10 +104,10 @@ static void fa526_read_core_regs_target_buffer(target_t *target, } } -static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) +static void fa526_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) { - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); @@ -133,10 +129,10 @@ static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0); } -static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr) +static void fa526_write_xpsr(struct target *target, uint32_t xpsr, int spsr) { - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -169,11 +165,11 @@ static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -static void fa526_write_xpsr_im8(target_t *target, +static void fa526_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr) { - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -187,8 +183,7 @@ static void fa526_write_xpsr_im8(target_t *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* rot == 4 writes flags, which takes only one cycle */ - if (rot != 4) - { + if (rot != 4) { /* nothing fetched, MSR in EXECUTE (2) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, MSR in EXECUTE (3) */ @@ -196,12 +191,12 @@ static void fa526_write_xpsr_im8(target_t *target, } } -static void fa526_write_core_regs(target_t *target, +static void fa526_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16]) { int i; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -215,8 +210,7 @@ static void fa526_write_core_regs(target_t *target, /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); @@ -224,10 +218,10 @@ static void fa526_write_core_regs(target_t *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -static void fa526_write_pc(target_t *target, uint32_t pc) +static void fa526_write_pc(struct target *target, uint32_t pc) { - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -250,18 +244,14 @@ static void fa526_write_pc(target_t *target, uint32_t pc) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -static void fa526_branch_resume_thumb(target_t *target) +static void fa526_branch_resume_thumb(struct target *target) { LOG_ERROR("%s: there is no Thumb state on FA526", __func__); } -static int fa526_init_arch_info_2(target_t *target, - arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap) +static int fa526_init_arch_info_2(struct target *target, + struct arm7_9_common *arm7_9, struct jtag_tap *tap) { - arm7_9_common_t *arm7_9; - - arm7_9 = &arm9tdmi->arm7_9_common; - /* prepare JTAG information for the new target */ arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.scann_size = 5; @@ -292,10 +282,12 @@ static int fa526_init_arch_info_2(target_t *target, arm7_9->enable_single_step = arm9tdmi_enable_single_step; arm7_9->disable_single_step = arm9tdmi_disable_single_step; + arm7_9->write_memory = arm920t_write_memory; + arm7_9->bulk_write_memory = arm7_9_bulk_write_memory; + arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; - arm7_9->post_restore_context = NULL; /* initialize arch-specific breakpoint handling */ arm7_9->arm_bkpt = 0xdeeedeee; @@ -314,15 +306,13 @@ static int fa526_init_arch_info_2(target_t *target, return ERROR_OK; } -static int fa526_init_arch_info(target_t *target, - arm920t_common_t *arm920t, struct jtag_tap *tap) +static int fa526_init_arch_info(struct target *target, + struct arm920t_common *arm920t, struct jtag_tap *tap) { - arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - fa526_init_arch_info_2(target, arm9tdmi, tap); + /* initialize arm7/arm9 specific info (including armv4_5) */ + fa526_init_arch_info_2(target, arm7_9, tap); arm920t->common_magic = ARM920T_COMMON_MAGIC; @@ -350,16 +340,15 @@ static int fa526_init_arch_info(target_t *target, return ERROR_OK; } -static int fa526_target_create(struct target_s *target, Jim_Interp *interp) +static int fa526_target_create(struct target *target, Jim_Interp *interp) { - arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); + struct arm920t_common *arm920t = calloc(1, sizeof(struct arm920t_common)); return fa526_init_arch_info(target, arm920t, target->tap); } /** Holds methods for FA526 targets. */ -target_type_t fa526_target = -{ +struct target_type fa526_target = { .name = "fa526", .poll = arm7_9_poll, @@ -375,13 +364,14 @@ target_type_t fa526_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm920t_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm920t_read_memory, - .write_memory = arm920t_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + .write_memory = arm7_9_write_memory_opt, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -390,8 +380,9 @@ target_type_t fa526_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm920t_register_commands, + .commands = arm920t_command_handlers, .target_create = fa526_target_create, .init_target = arm9tdmi_init_target, - .examine = arm9tdmi_examine, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, };