X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fetm.c;h=53d31a1538421beb59d7381ad13fd53129d84e6e;hp=c60cc0d7b84adece8c0baecb26b17e2907519a23;hb=e740536568f5943748f2159f0ef8baa4ab37dcb9;hpb=03fdabaaacaf745455902e46f6978f4e2f988ba1

diff --git a/src/target/etm.c b/src/target/etm.c
index c60cc0d7b8..53d31a1538 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -21,236 +21,357 @@
 #include "config.h"
 #endif
 
-#include <string.h>
-
 #include "etm.h"
 #include "etb.h"
-
-#include "armv4_5.h"
+#include "image.h"
 #include "arm7_9_common.h"
 #include "arm_disassembler.h"
-#include "arm_simulator.h"
 
-#include "log.h"
-#include "arm_jtag.h"
-#include "types.h"
-#include "binarybuffer.h"
-#include "target.h"
-#include "register.h"
-#include "jtag.h"
-#include "fileio.h"
 
-#include <stdlib.h>
-
-/* ETM register access functionality
+/*
+ * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
+ *
+ * ETM modules collect instruction and/or data trace information, compress
+ * it, and transfer it to a debugging host through either a (buffered) trace
+ * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  *
+ * There are several generations of these modules.  Original versions have
+ * JTAG access through a dedicated scan chain.  Recent versions have added
+ * access via coprocessor instructions, memory addressing, and the ARM Debug
+ * Interface v5 (ADIv5); and phased out direct JTAG access.
+ *
+ * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
+ * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
+ * implying non-JTAG connectivity options.
+ *
+ * Relevant documentation includes:
+ *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
+ *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
+ *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  */
 
-#if 0
-static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
-{
-	{"R", 1},
-	{"W", 1},
-	{"reserved", 26},
-	{"version", 4}
+#define ARRAY_SIZE(x)	((int)(sizeof(x)/sizeof((x)[0])))
+
+enum {
+	RO,				/* read/only */
+	WO,				/* write/only */
+	RW,				/* read/write */
 };
-#endif
 
-static int etm_reg_arch_info[] =
-{
-	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
-	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
-	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
-	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
-	0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
-	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
-	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-	0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
-	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
-	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+struct etm_reg_info {
+	uint8_t		addr;
+	uint8_t		size;		/* low-N of 32 bits */
+	uint8_t		mode;		/* RO, WO, RW */
+	uint8_t		bcd_vers;	/* 1.0, 2.0, etc */
+	char		*name;
 };
 
-static int etm_reg_arch_size_info[] =
-{
-	32, 32, 17, 8, 3, 9, 32, 16,
-	17, 26, 25, 8, 17, 32, 32, 17,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	7, 7, 7, 7, 7, 7, 7, 7,
-	7, 7, 7, 7, 7, 7, 7, 7,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	16, 16, 16, 16, 18, 18, 18, 18,
-	17, 17, 17, 17, 16, 16, 16, 16,
-	17, 17, 17, 17, 17, 17, 2,
-	17, 17, 17, 17, 32, 32, 32, 32
+/*
+ * Registers 0..0x7f are JTAG-addressable using scanchain 6.
+ * (Or on some processors, through coprocessor operations.)
+ * Newer versions of ETM make some W/O registers R/W, and
+ * provide definitions for some previously-unused bits.
+ */
+
+/* basic registers that are always there given the right ETM version */
+static const struct etm_reg_info etm_core[] = {
+	/* NOTE: we "know" ETM_CONFIG is listed first */
+	{ ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
+
+	/* ETM Trace Registers */
+	{ ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
+	{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
+	{ ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
+	{ ETM_STATUS,  3, RO, 0x11, "ETM_status", },
+	{ ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
+
+	/* TraceEnable configuration */
+	{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
+	{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
+	{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
+	{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
+
+	/* ViewData configuration (data trace) */
+	{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
+	{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
+	{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
+	{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
+
+	/* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
+
+	{ 0x78, 12, WO, 0x20, "ETM_sync_freq", },
+	{ 0x79, 32, RO, 0x20, "ETM_id", },
 };
 
-static char* etm_reg_list[] =
-{
-	"ETM_CTRL",
-	"ETM_CONFIG",
-	"ETM_TRIG_EVENT",
-	"ETM_MMD_CTRL",
-	"ETM_STATUS",
-	"ETM_SYS_CONFIG",
-	"ETM_TRACE_RESOURCE_CTRL",
-	"ETM_TRACE_EN_CTRL2",
-	"ETM_TRACE_EN_EVENT",
-	"ETM_TRACE_EN_CTRL1",
-	"ETM_FIFOFULL_REGION",
-	"ETM_FIFOFULL_LEVEL",
-	"ETM_VIEWDATA_EVENT",
-	"ETM_VIEWDATA_CTRL1",
-	"ETM_VIEWDATA_CTRL2",
-	"ETM_VIEWDATA_CTRL3",
-	"ETM_ADDR_COMPARATOR_VALUE1",
-	"ETM_ADDR_COMPARATOR_VALUE2",
-	"ETM_ADDR_COMPARATOR_VALUE3",
-	"ETM_ADDR_COMPARATOR_VALUE4",
-	"ETM_ADDR_COMPARATOR_VALUE5",
-	"ETM_ADDR_COMPARATOR_VALUE6",
-	"ETM_ADDR_COMPARATOR_VALUE7",
-	"ETM_ADDR_COMPARATOR_VALUE8",
-	"ETM_ADDR_COMPARATOR_VALUE9",
-	"ETM_ADDR_COMPARATOR_VALUE10",
-	"ETM_ADDR_COMPARATOR_VALUE11",
-	"ETM_ADDR_COMPARATOR_VALUE12",
-	"ETM_ADDR_COMPARATOR_VALUE13",
-	"ETM_ADDR_COMPARATOR_VALUE14",
-	"ETM_ADDR_COMPARATOR_VALUE15",
-	"ETM_ADDR_COMPARATOR_VALUE16",
-	"ETM_ADDR_ACCESS_TYPE1",
-	"ETM_ADDR_ACCESS_TYPE2",
-	"ETM_ADDR_ACCESS_TYPE3",
-	"ETM_ADDR_ACCESS_TYPE4",
-	"ETM_ADDR_ACCESS_TYPE5",
-	"ETM_ADDR_ACCESS_TYPE6",
-	"ETM_ADDR_ACCESS_TYPE7",
-	"ETM_ADDR_ACCESS_TYPE8",
-	"ETM_ADDR_ACCESS_TYPE9",
-	"ETM_ADDR_ACCESS_TYPE10",
-	"ETM_ADDR_ACCESS_TYPE11",
-	"ETM_ADDR_ACCESS_TYPE12",
-	"ETM_ADDR_ACCESS_TYPE13",
-	"ETM_ADDR_ACCESS_TYPE14",
-	"ETM_ADDR_ACCESS_TYPE15",
-	"ETM_ADDR_ACCESS_TYPE16",
-	"ETM_DATA_COMPARATOR_VALUE1",
-	"ETM_DATA_COMPARATOR_VALUE2",
-	"ETM_DATA_COMPARATOR_VALUE3",
-	"ETM_DATA_COMPARATOR_VALUE4",
-	"ETM_DATA_COMPARATOR_VALUE5",
-	"ETM_DATA_COMPARATOR_VALUE6",
-	"ETM_DATA_COMPARATOR_VALUE7",
-	"ETM_DATA_COMPARATOR_VALUE8",
-	"ETM_DATA_COMPARATOR_VALUE9",
-	"ETM_DATA_COMPARATOR_VALUE10",
-	"ETM_DATA_COMPARATOR_VALUE11",
-	"ETM_DATA_COMPARATOR_VALUE12",
-	"ETM_DATA_COMPARATOR_VALUE13",
-	"ETM_DATA_COMPARATOR_VALUE14",
-	"ETM_DATA_COMPARATOR_VALUE15",
-	"ETM_DATA_COMPARATOR_VALUE16",
-	"ETM_DATA_COMPARATOR_MASK1",
-	"ETM_DATA_COMPARATOR_MASK2",
-	"ETM_DATA_COMPARATOR_MASK3",
-	"ETM_DATA_COMPARATOR_MASK4",
-	"ETM_DATA_COMPARATOR_MASK5",
-	"ETM_DATA_COMPARATOR_MASK6",
-	"ETM_DATA_COMPARATOR_MASK7",
-	"ETM_DATA_COMPARATOR_MASK8",
-	"ETM_DATA_COMPARATOR_MASK9",
-	"ETM_DATA_COMPARATOR_MASK10",
-	"ETM_DATA_COMPARATOR_MASK11",
-	"ETM_DATA_COMPARATOR_MASK12",
-	"ETM_DATA_COMPARATOR_MASK13",
-	"ETM_DATA_COMPARATOR_MASK14",
-	"ETM_DATA_COMPARATOR_MASK15",
-	"ETM_DATA_COMPARATOR_MASK16",
-	"ETM_COUNTER_INITAL_VALUE1",
-	"ETM_COUNTER_INITAL_VALUE2",
-	"ETM_COUNTER_INITAL_VALUE3",
-	"ETM_COUNTER_INITAL_VALUE4",
-	"ETM_COUNTER_ENABLE1",
-	"ETM_COUNTER_ENABLE2",
-	"ETM_COUNTER_ENABLE3",
-	"ETM_COUNTER_ENABLE4",
-	"ETM_COUNTER_RELOAD_VALUE1",
-	"ETM_COUNTER_RELOAD_VALUE2",
-	"ETM_COUNTER_RELOAD_VALUE3",
-	"ETM_COUNTER_RELOAD_VALUE4",
-	"ETM_COUNTER_VALUE1",
-	"ETM_COUNTER_VALUE2",
-	"ETM_COUNTER_VALUE3",
-	"ETM_COUNTER_VALUE4",
-	"ETM_SEQUENCER_CTRL1",
-	"ETM_SEQUENCER_CTRL2",
-	"ETM_SEQUENCER_CTRL3",
-	"ETM_SEQUENCER_CTRL4",
-	"ETM_SEQUENCER_CTRL5",
-	"ETM_SEQUENCER_CTRL6",
-	"ETM_SEQUENCER_STATE",
-	"ETM_EXTERNAL_OUTPUT1",
-	"ETM_EXTERNAL_OUTPUT2",
-	"ETM_EXTERNAL_OUTPUT3",
-	"ETM_EXTERNAL_OUTPUT4",
-	"ETM_CONTEXTID_COMPARATOR_VALUE1",
-	"ETM_CONTEXTID_COMPARATOR_VALUE2",
-	"ETM_CONTEXTID_COMPARATOR_VALUE3",
-	"ETM_CONTEXTID_COMPARATOR_MASK"
+static const struct etm_reg_info etm_fifofull[] = {
+	/* FIFOFULL configuration */
+	{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
+	{ ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
+};
+
+static const struct etm_reg_info etm_addr_comp[] = {
+	/* Address comparator register pairs */
+#define ADDR_COMPARATOR(i) \
+		{ ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
+				"ETM_addr_" #i "_comparator_value", }, \
+		{ ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
+				"ETM_addr_" #i "_access_type", }
+	ADDR_COMPARATOR(1),
+	ADDR_COMPARATOR(2),
+	ADDR_COMPARATOR(3),
+	ADDR_COMPARATOR(4),
+	ADDR_COMPARATOR(5),
+	ADDR_COMPARATOR(6),
+	ADDR_COMPARATOR(7),
+	ADDR_COMPARATOR(8),
+
+	ADDR_COMPARATOR(9),
+	ADDR_COMPARATOR(10),
+	ADDR_COMPARATOR(11),
+	ADDR_COMPARATOR(12),
+	ADDR_COMPARATOR(13),
+	ADDR_COMPARATOR(14),
+	ADDR_COMPARATOR(15),
+	ADDR_COMPARATOR(16),
+#undef ADDR_COMPARATOR
+};
+
+static const struct etm_reg_info etm_data_comp[] = {
+	/* Data Value Comparators (NOTE: odd addresses are reserved) */
+#define DATA_COMPARATOR(i) \
+		{ ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
+				"ETM_data_" #i "_comparator_value", }, \
+		{ ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
+				"ETM_data_" #i "_comparator_mask", }
+	DATA_COMPARATOR(1),
+	DATA_COMPARATOR(2),
+	DATA_COMPARATOR(3),
+	DATA_COMPARATOR(4),
+	DATA_COMPARATOR(5),
+	DATA_COMPARATOR(6),
+	DATA_COMPARATOR(7),
+	DATA_COMPARATOR(8),
+#undef DATA_COMPARATOR
+};
+
+static const struct etm_reg_info etm_counters[] = {
+#define ETM_COUNTER(i) \
+		{ ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
+				"ETM_counter_" #i "_reload_value", }, \
+		{ ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
+				"ETM_counter_" #i "_enable", }, \
+		{ ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
+				"ETM_counter_" #i "_reload_event", }, \
+		{ ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
+				"ETM_counter_" #i "_value", }
+	ETM_COUNTER(1),
+	ETM_COUNTER(2),
+	ETM_COUNTER(3),
+	ETM_COUNTER(4),
+#undef ETM_COUNTER
+};
+
+static const struct etm_reg_info etm_sequencer[] = {
+#define ETM_SEQ(i) \
+		{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
+				"ETM_sequencer_event" #i, }
+	ETM_SEQ(0),				/* 1->2 */
+	ETM_SEQ(1),				/* 2->1 */
+	ETM_SEQ(2),				/* 2->3 */
+	ETM_SEQ(3),				/* 3->1 */
+	ETM_SEQ(4),				/* 3->2 */
+	ETM_SEQ(5),				/* 1->3 */
+#undef ETM_SEQ
+	/* 0x66 reserved */
+	{ ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
+};
+
+static const struct etm_reg_info etm_outputs[] = {
+#define ETM_OUTPUT(i) \
+		{ ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
+				"ETM_external_output" #i, }
+
+	ETM_OUTPUT(1),
+	ETM_OUTPUT(2),
+	ETM_OUTPUT(3),
+	ETM_OUTPUT(4),
+#undef ETM_OUTPUT
 };
 
+#if 0
+	/* registers from 0x6c..0x7f were added after ETMv1.3 */
+
+	/* Context ID Comparators */
+	{ 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
+	{ 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
+	{ 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
+	{ 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
+#endif
+
 static int etm_reg_arch_type = -1;
 
 static int etm_get_reg(reg_t *reg);
+static int etm_read_reg_w_check(reg_t *reg,
+		uint8_t* check_value, uint8_t* check_mask);
+static int etm_register_user_commands(struct command_context_s *cmd_ctx);
+static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
+static int etm_write_reg(reg_t *reg, uint32_t value);
+
+static command_t *etm_cmd;
+
 
-static command_t *etm_cmd = NULL;
+/* Look up register by ID ... most ETM instances only
+ * support a subset of the possible registers.
+ */
+static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
+{
+	reg_cache_t *cache = etm_ctx->reg_cache;
+	int i;
+
+	for (i = 0; i < cache->num_regs; i++) {
+		struct etm_reg_s *reg = cache->reg_list[i].arch_info;
+
+		if (reg->reg_info->addr == id)
+			return &cache->reg_list[i];
+	}
+
+	/* caller asking for nonexistent register is a bug! */
+	/* REVISIT say which of the N targets was involved */
+	LOG_ERROR("ETM: register 0x%02x not available", id);
+	return NULL;
+}
+
+static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
+		reg_cache_t *cache, etm_reg_t *ereg,
+		const struct etm_reg_info *r, unsigned nreg)
+{
+	reg_t *reg = cache->reg_list;
+
+	reg += cache->num_regs;
+	ereg += cache->num_regs;
+
+	/* add up to "nreg" registers from "r", if supported by this
+	 * version of the ETM, to the specified cache.
+	 */
+	for (; nreg--; r++) {
+
+		/* this ETM may be too old to have some registers */
+		if (r->bcd_vers > bcd_vers)
+			continue;
+
+		reg->name = r->name;
+		reg->size = r->size;
+		reg->value = &ereg->value;
+		reg->arch_info = ereg;
+		reg->arch_type = etm_reg_arch_type;
+		reg++;
+		cache->num_regs++;
+
+		ereg->reg_info = r;
+		ereg->jtag_info = jtag_info;
+		ereg++;
+	}
+}
 
-reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
+reg_cache_t *etm_build_reg_cache(target_t *target,
+		arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 {
 	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = NULL;
 	etm_reg_t *arch_info = NULL;
-	int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
-	int i;
+	unsigned bcd_vers, config;
 
 	/* register a register arch-type for etm registers only once */
 	if (etm_reg_arch_type == -1)
-		etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
+		etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
+				etm_set_reg_w_exec);
 
 	/* the actual registers are kept in two arrays */
-	reg_list = calloc(num_regs, sizeof(reg_t));
-	arch_info = calloc(num_regs, sizeof(etm_reg_t));
+	reg_list = calloc(128, sizeof(reg_t));
+	arch_info = calloc(128, sizeof(etm_reg_t));
 
 	/* fill in values for the reg cache */
 	reg_cache->name = "etm registers";
 	reg_cache->next = NULL;
 	reg_cache->reg_list = reg_list;
-	reg_cache->num_regs = num_regs;
-
-	/* set up registers */
-	for (i = 0; i < num_regs; i++)
-	{
-		reg_list[i].name = etm_reg_list[i];
-		reg_list[i].size = 32;
-		reg_list[i].dirty = 0;
-		reg_list[i].valid = 0;
-		reg_list[i].bitfield_desc = NULL;
-		reg_list[i].num_bitfields = 0;
-		reg_list[i].value = calloc(1, 4);
-		reg_list[i].arch_info = &arch_info[i];
-		reg_list[i].arch_type = etm_reg_arch_type;
-		reg_list[i].size = etm_reg_arch_size_info[i];
-		arch_info[i].addr = etm_reg_arch_info[i];
-		arch_info[i].jtag_info = jtag_info;
+	reg_cache->num_regs = 0;
+
+	/* add ETM_CONFIG, then parse its values to see
+	 * which other registers exist in this ETM
+	 */
+	etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
+			etm_core, 1);
+
+	etm_get_reg(reg_list);
+	etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
+	config = etm_ctx->config;
+
+	/* figure ETM version then add base registers */
+	if (config & (1 << 31)) {
+		bcd_vers = 0x20;
+		LOG_WARNING("ETMv2+ support is incomplete");
+
+		/* REVISIT read ID register, distinguish ETMv3.3 etc;
+		 * don't presume trace start/stop support is present;
+		 * and include any context ID comparator registers.
+		 */
+	} else {
+		switch (config >> 28) {
+		case 7:
+		case 5:
+		case 3:
+			bcd_vers = 0x13;
+			break;
+		case 4:
+		case 2:
+			bcd_vers = 0x12;
+			break;
+		case 1:
+			bcd_vers = 0x11;
+			break;
+		case 0:
+			bcd_vers = 0x10;
+			break;
+		default:
+			LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
+			free(reg_cache);
+			free(reg_list);
+			free(arch_info);
+			return ERROR_OK;
+		}
 	}
+	etm_ctx->bcd_vers = bcd_vers;
+	LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
+
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_core + 1, ARRAY_SIZE(etm_core) - 1);
+
+	/* address and data comparators; counters; outputs */
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_addr_comp, 4 * (0x0f & (config >> 0)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_data_comp, 2 * (0x0f & (config >> 4)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_counters, 4 * (0x07 & (config >> 13)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_outputs, (0x07 & (config >> 20)));
+
+	/* FIFOFULL presence is optional
+	 * REVISIT for ETMv1.2 and later, don't bother adding this
+	 * unless ETM_SYS_CONFIG says it's also *supported* ...
+	 */
+	if (config & (1 << 23))
+		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+				etm_fifofull, ARRAY_SIZE(etm_fifofull));
+
+	/* sequencer is optional (for state-dependant triggering) */
+	if (config & (1 << 16))
+		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+				etm_sequencer, ARRAY_SIZE(etm_sequencer));
+
+	/* REVISIT could realloc and likely save half the memory
+	 * in the two chunks we allocated...
+	 */
 
 	/* the ETM might have an ETB connected */
 	if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
@@ -260,6 +381,9 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
 		if (!etb)
 		{
 			LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
+			free(reg_cache);
+			free(reg_list);
+			free(arch_info);
 			return ERROR_OK;
 		}
 
@@ -272,14 +396,28 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
 	return reg_cache;
 }
 
+static int etm_read_reg(reg_t *reg)
+{
+	return etm_read_reg_w_check(reg, NULL, NULL);
+}
+
+static int etm_store_reg(reg_t *reg)
+{
+	return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+}
+
 int etm_setup(target_t *target)
 {
 	int retval;
-	u32 etm_ctrl_value;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	etm_context_t *etm_ctx = arm7_9->etm_ctx;
-	reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+	uint32_t etm_ctrl_value;
+	struct arm *arm = target_to_arm(target);
+	etm_context_t *etm_ctx = arm->etm;
+	reg_t *etm_ctrl_reg;
+
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_OK;
+
 	/* initialize some ETM control register settings */
 	etm_get_reg(etm_ctrl_reg);
 	etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
@@ -295,10 +433,10 @@ int etm_setup(target_t *target)
 	buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 	etm_store_reg(etm_ctrl_reg);
 
-	if ((retval=jtag_execute_queue())!=ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
-	if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
+	if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 	{
 		LOG_ERROR("ETM capture driver initialization failed");
 		return retval;
@@ -306,9 +444,10 @@ int etm_setup(target_t *target)
 	return ERROR_OK;
 }
 
-int etm_get_reg(reg_t *reg)
+static int etm_get_reg(reg_t *reg)
 {
 	int retval;
+
 	if ((retval = etm_read_reg(reg)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register read");
@@ -324,56 +463,55 @@ int etm_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+static int etm_read_reg_w_check(reg_t *reg,
+		uint8_t* check_value, uint8_t* check_mask)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
-	u8 reg_addr = etm_reg->addr & 0x7f;
+	const struct etm_reg_info *r = etm_reg->reg_info;
+	uint8_t reg_addr = r->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i", etm_reg->addr);
+	if (etm_reg->reg_info->mode == WO) {
+		LOG_ERROR("BUG: can't read write-only register %s", r->name);
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	LOG_DEBUG("%s (%u)", r->name, reg_addr);
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 
 	fields[0].tap = etm_reg->jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
-	fields[0].out_mask = NULL;
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
+	fields[0].check_value = NULL;
+	fields[0].check_mask = NULL;
 
 	fields[1].tap = etm_reg->jtag_info->tap;
 	fields[1].num_bits = 7;
 	fields[1].out_value = malloc(1);
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-	fields[1].out_mask = NULL;
 	fields[1].in_value = NULL;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
+	fields[1].check_value = NULL;
+	fields[1].check_mask = NULL;
 
 	fields[2].tap = etm_reg->jtag_info->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = malloc(1);
 	buf_set_u32(fields[2].out_value, 0, 1, 0);
-	fields[2].out_mask = NULL;
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
+	fields[2].check_value = NULL;
+	fields[2].check_mask = NULL;
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	fields[0].in_value = reg->value;
-	jtag_set_check_value(fields+0, check_value, check_mask, NULL);
+	fields[0].check_value = check_value;
+	fields[0].check_mask = check_mask;
 
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
+	jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 
 	free(fields[1].out_value);
 	free(fields[2].out_value);
@@ -381,14 +519,10 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	return ERROR_OK;
 }
 
-int etm_read_reg(reg_t *reg)
-{
-	return etm_read_reg_w_check(reg, NULL, NULL);
-}
-
-int etm_set_reg(reg_t *reg, u32 value)
+static int etm_set_reg(reg_t *reg, uint32_t value)
 {
 	int retval;
+
 	if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 	{
 		LOG_ERROR("BUG: error scheduling etm register write");
@@ -402,9 +536,10 @@ int etm_set_reg(reg_t *reg, u32 value)
 	return ERROR_OK;
 }
 
-int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
+static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 {
 	int retval;
+
 	etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -415,64 +550,50 @@ int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 	return ERROR_OK;
 }
 
-int etm_write_reg(reg_t *reg, u32 value)
+static int etm_write_reg(reg_t *reg, uint32_t value)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
-	u8 reg_addr = etm_reg->addr & 0x7f;
+	const struct etm_reg_info *r = etm_reg->reg_info;
+	uint8_t reg_addr = r->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
+	if (etm_reg->reg_info->mode == RO) {
+		LOG_ERROR("BUG: can't write read--only register %s", r->name);
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 
-	jtag_add_end_state(TAP_IDLE);
+	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 
 	fields[0].tap = etm_reg->jtag_info->tap;
 	fields[0].num_bits = 32;
-	fields[0].out_value = malloc(4);
+	uint8_t tmp1[4];
+	fields[0].out_value = tmp1;
 	buf_set_u32(fields[0].out_value, 0, 32, value);
-	fields[0].out_mask = NULL;
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
 
 	fields[1].tap = etm_reg->jtag_info->tap;
 	fields[1].num_bits = 7;
-	fields[1].out_value = malloc(1);
+	uint8_t tmp2;
+	fields[1].out_value = &tmp2;
 	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
-	fields[1].out_mask = NULL;
 	fields[1].in_value = NULL;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
 
 	fields[2].tap = etm_reg->jtag_info->tap;
 	fields[2].num_bits = 1;
-	fields[2].out_value = malloc(1);
+	uint8_t tmp3;
+	fields[2].out_value = &tmp3;
 	buf_set_u32(fields[2].out_value, 0, 1, 1);
-	fields[2].out_mask = NULL;
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
-
-	jtag_add_dr_scan(3, fields, TAP_INVALID);
 
-	free(fields[0].out_value);
-	free(fields[1].out_value);
-	free(fields[2].out_value);
+	jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
 	return ERROR_OK;
 }
 
-int etm_store_reg(reg_t *reg)
-{
-	return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
 
 /* ETM trace analysis functionality
  *
@@ -492,24 +613,12 @@ static etm_capture_driver_t *etm_capture_drivers[] =
 	NULL
 };
 
-char *etmv1v1_branch_reason_strings[] =
-{
-	"normal PC change",
-	"tracing enabled",
-	"trace restarted after overflow",
-	"exit from debug",
-	"periodic synchronization",
-	"reserved",
-	"reserved",
-	"reserved",
-};
-
 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 {
 	int i;
 	int section = -1;
-	u32 size_read;
-	u32 opcode;
+	uint32_t size_read;
+	uint32_t opcode;
 	int retval;
 
 	if (!ctx->image)
@@ -534,7 +643,7 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi
 
 	if (ctx->core_state == ARMV4_5_STATE_ARM)
 	{
-		u8 buf[4];
+		uint8_t buf[4];
 		if ((retval = image_read_section(ctx->image, section,
 			ctx->current_pc - ctx->image->sections[section].base_address,
 			4, buf, &size_read)) != ERROR_OK)
@@ -547,7 +656,7 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi
 	}
 	else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 	{
-		u8 buf[2];
+		uint8_t buf[2];
 		if ((retval = image_read_section(ctx->image, section,
 			ctx->current_pc - ctx->image->sections[section].base_address,
 			2, buf, &size_read)) != ERROR_OK)
@@ -561,18 +670,18 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi
 	else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 	{
 		LOG_ERROR("BUG: tracing of jazelle code not supported");
-		exit(-1);
+		return ERROR_FAIL;
 	}
 	else
 	{
 		LOG_ERROR("BUG: unknown core state encountered");
-		exit(-1);
+		return ERROR_FAIL;
 	}
 
 	return ERROR_OK;
 }
 
-static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
+static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
 {
 	while (ctx->data_index < ctx->trace_depth)
 	{
@@ -640,10 +749,10 @@ static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 static int etmv1_branch_address(etm_context_t *ctx)
 {
 	int retval;
-	u8 packet;
+	uint8_t packet;
 	int shift = 0;
 	int apo;
-	u32 i;
+	uint32_t i;
 
 	/* quit analysis if less than two cycles are left in the trace
 	 * because we can't extract the APO */
@@ -723,10 +832,10 @@ static int etmv1_branch_address(etm_context_t *ctx)
 	return 0;
 }
 
-static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
+static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
 {
 	int j;
-	u8 buf[4];
+	uint8_t buf[4];
 	int retval;
 
 	for (j = 0; j < size; j++)
@@ -772,13 +881,13 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 
 	while (ctx->pipe_index < ctx->trace_depth)
 	{
-		u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
-		u32 next_pc = ctx->current_pc;
-		u32 old_data_index = ctx->data_index;
-		u32 old_data_half = ctx->data_half;
-		u32 old_index = ctx->pipe_index;
-		u32 last_instruction = ctx->last_instruction;
-		u32 cycles = 0;
+		uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
+		uint32_t next_pc = ctx->current_pc;
+		uint32_t old_data_index = ctx->data_index;
+		uint32_t old_data_half = ctx->data_half;
+		uint32_t old_index = ctx->pipe_index;
+		uint32_t last_instruction = ctx->last_instruction;
+		uint32_t cycles = 0;
 		int current_pc_ok = ctx->pc_ok;
 
 		if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
@@ -835,19 +944,19 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 					next_pc = ctx->last_branch;
 					break;
 				case 0x1:	/* tracing enabled */
-					command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
 					break;
 				case 0x2:	/* trace restarted after FIFO overflow */
-					command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
 					break;
 				case 0x3:	/* exit from debug state */
-					command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
@@ -859,16 +968,15 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 					 */
 					if (!current_pc_ok)
 					{
-						command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
+						command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 						ctx->current_pc = next_pc;
 						ctx->pipe_index++;
 						continue;
 					}
 					break;
 				default:	/* reserved */
-					LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
-					exit(-1);
-					break;
+					LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
+					return ERROR_FAIL;
 			}
 
 			/* if we got here the branch was a normal PC change
@@ -888,7 +996,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 				}
 				else
 				{
-					command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
+					command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
@@ -922,8 +1030,8 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 
 		if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 		{
-			u32 new_data_index = ctx->data_index;
-			u32 new_data_half = ctx->data_half;
+			uint32_t new_data_index = ctx->data_index;
+			uint32_t new_data_half = ctx->data_half;
 
 			/* in case of a branch with data, the branch target address was consumed before
 			 * we temporarily go back to the saved data index */
@@ -935,7 +1043,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 
 			if (ctx->tracemode & ETMV1_TRACE_ADDR)
 			{
-				u8 packet;
+				uint8_t packet;
 				int shift = 0;
 
 				do {
@@ -951,7 +1059,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 
 				if (ctx->ptr_ok)
 				{
-					command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
+					command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
 				}
 			}
 
@@ -964,19 +1072,19 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 					{
 						if (instruction.info.load_store_multiple.register_list & (1 << i))
 						{
-							u32 data;
+							uint32_t data;
 							if (etmv1_data(ctx, 4, &data) != 0)
 								return ERROR_ETM_ANALYSIS_FAILED;
-							command_print(cmd_ctx, "data: 0x%8.8x", data);
+							command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
 						}
 					}
 				}
 				else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 				{
-					u32 data;
+					uint32_t data;
 					if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 						return ERROR_ETM_ANALYSIS_FAILED;
-					command_print(cmd_ctx, "data: 0x%8.8x", data);
+					command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
 				}
 			}
 
@@ -993,7 +1101,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 		{
 			if (((instruction.type == ARM_B) ||
 			     (instruction.type == ARM_BL) ||
-			     (instruction.type == ARM_BLX)) &&	 
+			     (instruction.type == ARM_BLX)) &&
 			    (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
 			{
 				next_pc = instruction.info.b_bl_bx_blx.target_address;
@@ -1018,7 +1126,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 			if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
 			{
 				snprintf(cycles_text, 32, " (%i %s)",
-					cycles,
+					 (int)cycles,
 					(cycles == 1) ? "cycle" : "cycles");
 			}
 
@@ -1045,106 +1153,117 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd
 	return ERROR_OK;
 }
 
-static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_tracemode_command_update(
+		struct command_context_s *cmd_ctx,
+		char **args, etmv1_tracemode_t *mode)
 {
-	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
 	etmv1_tracemode_t tracemode;
 
-	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	/* what parts of data access are traced? */
+	if (strcmp(args[0], "none") == 0)
+		tracemode = ETMV1_TRACE_NONE;
+	else if (strcmp(args[0], "data") == 0)
+		tracemode = ETMV1_TRACE_DATA;
+	else if (strcmp(args[0], "address") == 0)
+		tracemode = ETMV1_TRACE_ADDR;
+	else if (strcmp(args[0], "all") == 0)
+		tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
+	else
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "invalid option '%s'", args[0]);
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	uint8_t context_id;
+	COMMAND_PARSE_NUMBER(u8, args[1], context_id);
+	switch (context_id)
+	{
+	case 0:
+		tracemode |= ETMV1_CONTEXTID_NONE;
+		break;
+	case 8:
+		tracemode |= ETMV1_CONTEXTID_8;
+		break;
+	case 16:
+		tracemode |= ETMV1_CONTEXTID_16;
+		break;
+	case 32:
+		tracemode |= ETMV1_CONTEXTID_32;
+		break;
+	default:
+		command_print(cmd_ctx, "invalid option '%s'", args[1]);
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	if (strcmp(args[2], "enable") == 0)
+		tracemode |= ETMV1_CYCLE_ACCURATE;
+	else if (strcmp(args[2], "disable") == 0)
+		tracemode |= 0;
+	else
+	{
+		command_print(cmd_ctx, "invalid option '%s'", args[2]);
+		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	if (!arm7_9->etm_ctx)
+	if (strcmp(args[3], "enable") == 0)
+		tracemode |= ETMV1_BRANCH_OUTPUT;
+	else if (strcmp(args[3], "disable") == 0)
+		tracemode |= 0;
+	else
 	{
-		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		command_print(cmd_ctx, "invalid option '%s'", args[3]);
+		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	tracemode = arm7_9->etm_ctx->tracemode;
+	/* IGNORED:
+	 *  - CPRT tracing (coprocessor register transfers)
+	 *  - debug request (causes debug entry on trigger)
+	 *  - stall on FIFOFULL (preventing tracedata lossage)
+	 */
+	*mode = tracemode;
 
-	if (argc == 4)
-	{
-		if (strcmp(args[0], "none") == 0)
-		{
-			tracemode = ETMV1_TRACE_NONE;
-		}
-		else if (strcmp(args[0], "data") == 0)
-		{
-			tracemode = ETMV1_TRACE_DATA;
-		}
-		else if (strcmp(args[0], "address") == 0)
-		{
-			tracemode = ETMV1_TRACE_ADDR;
-		}
-		else if (strcmp(args[0], "all") == 0)
-		{
-			tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
-		}
-		else
-		{
-			command_print(cmd_ctx, "invalid option '%s'", args[0]);
-			return ERROR_OK;
-		}
+	return ERROR_OK;
+}
 
-		switch (strtol(args[1], NULL, 0))
-		{
-			case 0:
-				tracemode |= ETMV1_CONTEXTID_NONE;
-				break;
-			case 8:
-				tracemode |= ETMV1_CONTEXTID_8;
-				break;
-			case 16:
-				tracemode |= ETMV1_CONTEXTID_16;
-				break;
-			case 32:
-				tracemode |= ETMV1_CONTEXTID_32;
-				break;
-			default:
-				command_print(cmd_ctx, "invalid option '%s'", args[1]);
-				return ERROR_OK;
-		}
+static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	struct arm *arm = target_to_arm(target);
+	struct etm *etm;
 
-		if (strcmp(args[2], "enable") == 0)
-		{
-			tracemode |= ETMV1_CYCLE_ACCURATE;
-		}
-		else if (strcmp(args[2], "disable") == 0)
-		{
-			tracemode |= 0;
-		}
-		else
-		{
-			command_print(cmd_ctx, "invalid option '%s'", args[2]);
-			return ERROR_OK;
-		}
+	if (!is_arm(arm)) {
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
+	}
 
-		if (strcmp(args[3], "enable") == 0)
-		{
-			tracemode |= ETMV1_BRANCH_OUTPUT;
-		}
-		else if (strcmp(args[3], "disable") == 0)
-		{
-			tracemode |= 0;
-		}
-		else
-		{
-			command_print(cmd_ctx, "invalid option '%s'", args[2]);
-			return ERROR_OK;
-		}
+	etm = arm->etm;
+	if (!etm) {
+		command_print(cmd_ctx, "current target doesn't have an ETM configured");
+		return ERROR_FAIL;
 	}
-	else if (argc != 0)
+
+	etmv1_tracemode_t tracemode = etm->tracemode;
+
+	switch (argc)
 	{
-		command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
-		return ERROR_OK;
+	case 0:
+		break;
+	case 4:
+		handle_etm_tracemode_command_update(cmd_ctx, args, &tracemode);
+		break;
+	default:
+		command_print(cmd_ctx, "usage: configure trace mode "
+				"<none | data | address | all> "
+				"<context id bits> <cycle accurate> <branch output>");
+		return ERROR_FAIL;
 	}
 
+	/**
+	 * todo: fail if parameters were invalid for this hardware,
+	 * or couldn't be written; display actual hardware state...
+	 */
+
 	command_print(cmd_ctx, "current tracemode configuration:");
 
 	switch (tracemode & ETMV1_TRACE_MASK)
@@ -1198,9 +1317,13 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
 	}
 
 	/* only update ETM_CTRL register if tracemode changed */
-	if (arm7_9->etm_ctx->tracemode != tracemode)
+	if (etm->tracemode != tracemode)
 	{
-		reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+		reg_t *etm_ctrl_reg;
+
+		etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
+		if (!etm_ctrl_reg)
+			return ERROR_FAIL;
 
 		etm_get_reg(etm_ctrl_reg);
 
@@ -1210,50 +1333,50 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
 		buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
 		etm_store_reg(etm_ctrl_reg);
 
-		arm7_9->etm_ctx->tracemode = tracemode;
+		etm->tracemode = tracemode;
 
 		/* invalidate old trace data */
-		arm7_9->etm_ctx->capture_status = TRACE_IDLE;
-		if (arm7_9->etm_ctx->trace_depth > 0)
+		etm->capture_status = TRACE_IDLE;
+		if (etm->trace_depth > 0)
 		{
-			free(arm7_9->etm_ctx->trace_data);
-			arm7_9->etm_ctx->trace_data = NULL;
+			free(etm->trace_data);
+			etm->trace_data = NULL;
 		}
-		arm7_9->etm_ctx->trace_depth = 0;
+		etm->trace_depth = 0;
 	}
 
 	return ERROR_OK;
 }
 
-static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_config_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_portmode_t portmode = 0x0;
-	etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
+	struct etm *etm_ctx;
 	int i;
 
 	if (argc != 5)
-	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	target = get_target_by_num(strtoul(args[0], NULL, 0));
 
+	target = get_target(args[0]);
 	if (!target)
 	{
-		LOG_ERROR("target number '%s' not defined", args[0]);
+		LOG_ERROR("target '%s' not defined", args[0]);
 		return ERROR_FAIL;
 	}
 
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
-	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
+	arm = target_to_arm(target);
+	if (!is_arm(arm)) {
+		command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
+				target->cmd_name, target_get_name(target));
 		return ERROR_FAIL;
 	}
 
-	switch (strtoul(args[1], NULL, 0))
+	uint8_t port_width;
+	COMMAND_PARSE_NUMBER(u8, args[1], port_width);
+	switch (port_width)
 	{
 		case 4:
 			portmode |= ETM_PORT_4BIT;
@@ -1301,12 +1424,18 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm
 		return ERROR_FAIL;
 	}
 
-	for (i=0; etm_capture_drivers[i]; i++)
+	etm_ctx = calloc(1, sizeof(etm_context_t));
+	if (!etm_ctx) {
+		LOG_DEBUG("out of memory");
+		return ERROR_FAIL;
+	}
+
+	for (i = 0; etm_capture_drivers[i]; i++)
 	{
 		if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
 		{
 			int retval;
-			if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
+			if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
 			{
 				free(etm_ctx);
 				return retval;
@@ -1329,66 +1458,70 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm
 	etm_ctx->target = target;
 	etm_ctx->trigger_percent = 50;
 	etm_ctx->trace_data = NULL;
-	etm_ctx->trace_depth = 0;
 	etm_ctx->portmode = portmode;
-	etm_ctx->tracemode = 0x0;
 	etm_ctx->core_state = ARMV4_5_STATE_ARM;
-	etm_ctx->image = NULL;
-	etm_ctx->pipe_index = 0;
-	etm_ctx->data_index = 0;
-	etm_ctx->current_pc = 0x0;
-	etm_ctx->pc_ok = 0;
-	etm_ctx->last_branch = 0x0;
-	etm_ctx->last_branch_reason = 0x0;
-	etm_ctx->last_ptr = 0x0;
-	etm_ctx->ptr_ok = 0x0;
-	etm_ctx->context_id = 0x0;
-	etm_ctx->last_instruction = 0;
-
-	arm7_9->etm_ctx = etm_ctx;
+
+	arm->etm = etm_ctx;
 
 	return etm_register_user_commands(cmd_ctx);
 }
 
-int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_info_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
-	reg_t *etm_config_reg;
+	struct arm *arm;
+	etm_context_t *etm;
 	reg_t *etm_sys_config_reg;
-
 	int max_port_size;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!arm7_9->etm_ctx)
+	etm = arm->etm;
+	if (!etm)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
-	etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
-	etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
-
-	etm_get_reg(etm_config_reg);
-	command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
-	command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
-	command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
-	command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
+	command_print(cmd_ctx, "ETM v%d.%d",
+			etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
+	command_print(cmd_ctx, "pairs of address comparators: %i",
+			(int) (etm->config >> 0) & 0x0f);
+	command_print(cmd_ctx, "data comparators: %i",
+			(int) (etm->config >> 4) & 0x0f);
+	command_print(cmd_ctx, "memory map decoders: %i",
+			(int) (etm->config >> 8) & 0x1f);
+	command_print(cmd_ctx, "number of counters: %i",
+			(int) (etm->config >> 13) & 0x07);
 	command_print(cmd_ctx, "sequencer %spresent",
-			(buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
-	command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
+			(int) (etm->config & (1 << 16)) ? "" : "not ");
+	command_print(cmd_ctx, "number of ext. inputs: %i",
+			(int) (etm->config >> 17) & 0x07);
+	command_print(cmd_ctx, "number of ext. outputs: %i",
+			(int) (etm->config >> 20) & 0x07);
 	command_print(cmd_ctx, "FIFO full %spresent",
-			(buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
+			(int) (etm->config & (1 << 23)) ? "" : "not ");
+	if (etm->bcd_vers < 0x20)
+		command_print(cmd_ctx, "protocol version: %i",
+				(int) (etm->config >> 28) & 0x07);
+	else {
+		command_print(cmd_ctx, "trace start/stop %spresent",
+				(etm->config & (1 << 26)) ? "" : "not ");
+		command_print(cmd_ctx, "number of context comparators: %i",
+				(int) (etm->config >> 24) & 0x03);
+	}
+
+	/* SYS_CONFIG isn't present before ETMv1.2 */
+	etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
+	if (!etm_sys_config_reg)
+		return ERROR_OK;
 
 	etm_get_reg(etm_sys_config_reg);
 
@@ -1405,7 +1538,7 @@ int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char *
 			break;
 		default:
 			LOG_ERROR("Illegal max_port_size");
-			exit(-1);
+			return ERROR_FAIL;
 	}
 	command_print(cmd_ctx, "max. port size: %i", max_port_size);
 
@@ -1425,79 +1558,109 @@ int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char *
 	return ERROR_OK;
 }
 
-static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_status_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
+	etm_context_t *etm;
 	trace_status_t trace_status;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!arm7_9->etm_ctx)
+	etm = arm->etm;
+	if (!etm)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
-	trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
+	/* ETM status */
+	if (etm->bcd_vers >= 0x11) {
+		reg_t *reg;
 
+		reg = etm_reg_lookup(etm, ETM_STATUS);
+		if (!reg)
+			return ERROR_FAIL;
+		if (etm_get_reg(reg) == ERROR_OK) {
+			unsigned s = buf_get_u32(reg->value, 0, reg->size);
+
+			command_print(cmd_ctx, "etm: %s%s%s%s",
+				/* bit(1) == progbit */
+				(etm->bcd_vers >= 0x12)
+					? ((s & (1 << 1))
+						? "disabled" : "enabled")
+					: "?",
+				((s & (1 << 3)) && etm->bcd_vers >= 0x31)
+					? " triggered" : "",
+				((s & (1 << 2)) && etm->bcd_vers >= 0x12)
+					? " start/stop" : "",
+				((s & (1 << 0)) && etm->bcd_vers >= 0x11)
+					? " untraced-overflow" : "");
+		} /* else ignore and try showing trace port status */
+	}
+
+	/* Trace Port Driver status */
+	trace_status = etm->capture_driver->status(etm);
 	if (trace_status == TRACE_IDLE)
 	{
-		command_print(cmd_ctx, "tracing is idle");
+		command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
 	}
 	else
 	{
 		static char *completed = " completed";
 		static char *running = " is running";
-		static char *overflowed = ", trace overflowed";
-		static char *triggered = ", trace triggered";
+		static char *overflowed = ", overflowed";
+		static char *triggered = ", triggered";
 
-		command_print(cmd_ctx, "trace collection%s%s%s",
+		command_print(cmd_ctx, "%s: trace collection%s%s%s",
+			etm->capture_driver->name,
 			(trace_status & TRACE_RUNNING) ? running : completed,
 			(trace_status & TRACE_OVERFLOWED) ? overflowed : "",
 			(trace_status & TRACE_TRIGGERED) ? triggered : "");
 
-		if (arm7_9->etm_ctx->trace_depth > 0)
+		if (etm->trace_depth > 0)
 		{
-			command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
+			command_print(cmd_ctx, "%i frames of trace data read",
+					(int)(etm->trace_depth));
 		}
 	}
 
 	return ERROR_OK;
 }
 
-static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_image_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
 
 	if (argc < 1)
 	{
 		command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->image)
@@ -1515,7 +1678,7 @@ static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd
 	if (argc >= 2)
 	{
 		etm_ctx->image->base_address_set = 1;
-		etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
+		COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
 	}
 	else
 	{
@@ -1526,39 +1689,40 @@ static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd
 	{
 		free(etm_ctx->image);
 		etm_ctx->image = NULL;
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	return ERROR_OK;
 }
 
-static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_dump_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	fileio_t file;
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
-	u32 i;
+	uint32_t i;
 
 	if (argc != 1)
 	{
 		command_print(cmd_ctx, "usage: etm dump <file>");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->capture_driver->status == TRACE_IDLE)
@@ -1571,7 +1735,7 @@ static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd,
 	{
 		/* TODO: if on-the-fly capture is to be supported, this needs to be changed */
 		command_print(cmd_ctx, "trace capture not completed");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	/* read the trace data if it wasn't read already */
@@ -1580,7 +1744,7 @@ static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd,
 
 	if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
 	{
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	fileio_write_u32(&file, etm_ctx->capture_status);
@@ -1600,51 +1764,52 @@ static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd,
 	return ERROR_OK;
 }
 
-static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_load_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	fileio_t file;
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
-	u32 i;
+	uint32_t i;
 
 	if (argc != 1)
 	{
 		command_print(cmd_ctx, "usage: etm load <file>");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
 	{
 		command_print(cmd_ctx, "trace capture running, stop first");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
 	{
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (file.size % 4)
 	{
 		command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
 		fileio_close(&file);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->trace_depth > 0)
@@ -1653,22 +1818,24 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd,
 		etm_ctx->trace_data = NULL;
 	}
 
-	fileio_read_u32(&file, &etm_ctx->capture_status);
-	fileio_read_u32(&file, &etm_ctx->portmode);
-	fileio_read_u32(&file, &etm_ctx->tracemode);
-	fileio_read_u32(&file, &etm_ctx->trace_depth);
-
+	{
+	  uint32_t tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
+	  fileio_read_u32(&file, &etm_ctx->trace_depth);
+	}
 	etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
-	if(etm_ctx->trace_data == NULL)
+	if (etm_ctx->trace_data == NULL)
 	{
 		command_print(cmd_ctx, "not enough memory to perform operation");
 		fileio_close(&file);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	for (i = 0; i < etm_ctx->trace_depth; i++)
 	{
-		u32 pipestat, packet, flags;
+		uint32_t pipestat, packet, flags;
 		fileio_read_u32(&file, &pipestat);
 		fileio_read_u32(&file, &packet);
 		fileio_read_u32(&file, &flags);
@@ -1682,34 +1849,36 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd,
 	return ERROR_OK;
 }
 
-static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if (argc > 0)
 	{
-		u32 new_value = strtoul(args[0], NULL, 0);
+		uint32_t new_value;
+		COMMAND_PARSE_NUMBER(u32, args[0], new_value);
 
 		if ((new_value < 2) || (new_value > 100))
 		{
-			command_print(cmd_ctx, "valid settings are 2% to 100%");
+			command_print(cmd_ctx, "valid settings are 2%% to 100%%");
 		}
 		else
 		{
@@ -1717,43 +1886,47 @@ static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx,
 		}
 	}
 
-	command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
+	command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
 
 	return ERROR_OK;
 }
 
-static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_start_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
 	reg_t *etm_ctrl_reg;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	/* invalidate old tracing data */
-	arm7_9->etm_ctx->capture_status = TRACE_IDLE;
-	if (arm7_9->etm_ctx->trace_depth > 0)
+	etm_ctx->capture_status = TRACE_IDLE;
+	if (etm_ctx->trace_depth > 0)
 	{
-		free(arm7_9->etm_ctx->trace_data);
-		arm7_9->etm_ctx->trace_data = NULL;
+		free(etm_ctx->trace_data);
+		etm_ctx->trace_data = NULL;
 	}
-	arm7_9->etm_ctx->trace_depth = 0;
+	etm_ctx->trace_depth = 0;
+
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_FAIL;
 
-	etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
 	etm_get_reg(etm_ctrl_reg);
 
 	/* Clear programming bit (10), set port selection bit (11) */
@@ -1767,29 +1940,33 @@ static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd
 	return ERROR_OK;
 }
 
-static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_stop_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
 	reg_t *etm_ctrl_reg;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
-	etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_FAIL;
+
 	etm_get_reg(etm_ctrl_reg);
 
 	/* Set programming bit (10), clear port selection bit (11) */
@@ -1803,31 +1980,32 @@ static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd,
 	return ERROR_OK;
 }
 
-static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_analyze_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
+	struct arm *arm;
 	etm_context_t *etm_ctx;
 	int retval;
 
 	target = get_current_target(cmd_ctx);
-
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
-		return ERROR_OK;
+		command_print(cmd_ctx, "ETM: current target isn't an ARM");
+		return ERROR_FAIL;
 	}
 
-	if (!(etm_ctx = arm7_9->etm_ctx))
+	etm_ctx = arm->etm;
+	if (!etm_ctx)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
 	{
-		switch(retval)
+		switch (retval)
 		{
 			case ERROR_ETM_ANALYSIS_FAILED:
 				command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
@@ -1843,27 +2021,30 @@ static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *c
 		}
 	}
 
-	return ERROR_OK;
+	return retval;
 }
 
 int etm_register_commands(struct command_context_s *cmd_ctx)
 {
 	etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
 
-	register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
+	register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
+		COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
 
 	return ERROR_OK;
 }
 
-int etm_register_user_commands(struct command_context_s *cmd_ctx)
+static int etm_register_user_commands(struct command_context_s *cmd_ctx)
 {
 	register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
-		COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
+		COMMAND_EXEC, "configure/display trace mode: "
+			"<none | data | address | all> "
+			"<context_id_bits> <cycle_accurate> <branch_output>");
 
 	register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
 		COMMAND_EXEC, "display info about the current target's ETM");
 
-	register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
+	register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
 		COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
 	register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
 		COMMAND_EXEC, "display current target's ETM status");