X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fetb.c;h=a789777baa64e8f6bce650f3e124b78746c7c160;hp=5791e578720b795f24ae10283abb4bafc6b5bfe8;hb=9abad965ab358c1d598f1354842967cad637b284;hpb=689e9664b00a81b637d82e990096338a10c4b720

diff --git a/src/target/etb.c b/src/target/etb.c
index 5791e57872..a789777baa 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -21,8 +21,10 @@
 #include "config.h"
 #endif
 
-#include "arm7_9_common.h"
+#include "arm.h"
+#include "etm.h"
 #include "etb.h"
+#include "register.h"
 
 
 static char* etb_reg_list[] =
@@ -38,27 +40,23 @@ static char* etb_reg_list[] =
 	"ETB_control",
 };
 
-static int etb_reg_arch_type = -1;
+static int etb_get_reg(struct reg *reg);
 
-static int etb_get_reg(reg_t *reg);
-
-static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
-static int etb_set_instr(etb_t *etb, u32 new_instr)
+static int etb_set_instr(struct etb *etb, uint32_t new_instr)
 {
-	jtag_tap_t *tap;
+	struct jtag_tap *tap;
 
 	tap = etb->tap;
-	if (tap==NULL)
+	if (tap == NULL)
 		return ERROR_FAIL;
 
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 	{
-		scan_field_t field;
+		struct scan_field field;
 
 		field.tap = tap;
 		field.num_bits = tap->ir_length;
-		field.out_value = calloc(CEIL(field.num_bits, 8), 1);
+		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 
 		field.in_value = NULL;
@@ -71,15 +69,15 @@ static int etb_set_instr(etb_t *etb, u32 new_instr)
 	return ERROR_OK;
 }
 
-static int etb_scann(etb_t *etb, u32 new_scan_chain)
+static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
 {
 	if (etb->cur_scan_chain != new_scan_chain)
 	{
-		scan_field_t field;
+		struct scan_field field;
 
 		field.tap = etb->tap;
 		field.num_bits = 5;
-		field.out_value = calloc(CEIL(field.num_bits, 8), 1);
+		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
 		buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
 
 		field.in_value = NULL;
@@ -96,21 +94,49 @@ static int etb_scann(etb_t *etb, u32 new_scan_chain)
 	return ERROR_OK;
 }
 
-reg_cache_t* etb_build_reg_cache(etb_t *etb)
+static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
+static int etb_set_reg_w_exec(struct reg *, uint8_t *);
+
+static int etb_read_reg(struct reg *reg)
 {
-	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
-	reg_t *reg_list = NULL;
-	etb_reg_t *arch_info = NULL;
+	return etb_read_reg_w_check(reg, NULL, NULL);
+}
+
+static int etb_get_reg(struct reg *reg)
+{
+	int retval;
+
+	if ((retval = etb_read_reg(reg)) != ERROR_OK)
+	{
+		LOG_ERROR("BUG: error scheduling ETB register read");
+		return retval;
+	}
+
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		LOG_ERROR("ETB register read failed");
+		return retval;
+	}
+
+	return ERROR_OK;
+}
+
+static const struct reg_arch_type etb_reg_type = {
+	.get = etb_get_reg,
+	.set = etb_set_reg_w_exec,
+};
+
+struct reg_cache* etb_build_reg_cache(struct etb *etb)
+{
+	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
+	struct reg *reg_list = NULL;
+	struct etb_reg *arch_info = NULL;
 	int num_regs = 9;
 	int i;
 
-	/* register a register arch-type for etm registers only once */
-	if (etb_reg_arch_type == -1)
-		etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
-
 	/* the actual registers are kept in two arrays */
-	reg_list = calloc(num_regs, sizeof(reg_t));
-	arch_info = calloc(num_regs, sizeof(etb_reg_t));
+	reg_list = calloc(num_regs, sizeof(struct reg));
+	arch_info = calloc(num_regs, sizeof(struct etb_reg));
 
 	/* fill in values for the reg cache */
 	reg_cache->name = "etb registers";
@@ -125,11 +151,9 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
 		reg_list[i].size = 32;
 		reg_list[i].dirty = 0;
 		reg_list[i].valid = 0;
-		reg_list[i].bitfield_desc = NULL;
-		reg_list[i].num_bitfields = 0;
 		reg_list[i].value = calloc(1, 4);
 		reg_list[i].arch_info = &arch_info[i];
-		reg_list[i].arch_type = etb_reg_arch_type;
+		reg_list[i].type = &etb_reg_type;
 		reg_list[i].size = 32;
 		arch_info[i].addr = i;
 		arch_info[i].etb = etb;
@@ -138,35 +162,17 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
 	return reg_cache;
 }
 
-static int etb_get_reg(reg_t *reg)
+static void etb_getbuf(jtag_callback_data_t arg)
 {
-	int retval;
-
-	if ((retval = etb_read_reg(reg)) != ERROR_OK)
-	{
-		LOG_ERROR("BUG: error scheduling etm register read");
-		return retval;
-	}
-
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("register read failed");
-		return retval;
-	}
-
-	return ERROR_OK;
-}
-
+	uint8_t *in = (uint8_t *)arg;
 
-static void etb_getbuf(u8 *in)
-{
-	*((u32 *)in)=buf_get_u32(in, 0, 32);
+	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
 }
 
 
-static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
+static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 {
-	scan_field_t fields[3];
+	struct scan_field fields[3];
 	int i;
 
 	jtag_set_end_state(TAP_IDLE);
@@ -203,10 +209,10 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 		else
 			buf_set_u32(fields[1].out_value, 0, 7, 0);
 
-		fields[0].in_value = (u8 *)(data+i);
+		fields[0].in_value = (uint8_t *)(data + i);
 		jtag_add_dr_scan(3, fields, jtag_get_end_state());
 
-		jtag_add_callback(etb_getbuf, (u8 *)(data+i));
+		jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 	}
 
 	jtag_execute_queue();
@@ -217,13 +223,14 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 	return ERROR_OK;
 }
 
-int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
+static int etb_read_reg_w_check(struct reg *reg,
+		uint8_t* check_value, uint8_t* check_mask)
 {
-	etb_reg_t *etb_reg = reg->arch_info;
-	u8 reg_addr = etb_reg->addr & 0x7f;
-	scan_field_t fields[3];
+	struct etb_reg *etb_reg = reg->arch_info;
+	uint8_t reg_addr = etb_reg->addr & 0x7f;
+	struct scan_field fields[3];
 
-	LOG_DEBUG("%i", etb_reg->addr);
+	LOG_DEBUG("%i", (int)(etb_reg->addr));
 
 	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
@@ -270,18 +277,15 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 	return ERROR_OK;
 }
 
-int etb_read_reg(reg_t *reg)
-{
-	return etb_read_reg_w_check(reg, NULL, NULL);
-}
+static int etb_write_reg(struct reg *, uint32_t);
 
-int etb_set_reg(reg_t *reg, u32 value)
+static int etb_set_reg(struct reg *reg, uint32_t value)
 {
 	int retval;
 
 	if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 	{
-		LOG_ERROR("BUG: error scheduling etm register write");
+		LOG_ERROR("BUG: error scheduling ETB register write");
 		return retval;
 	}
 
@@ -292,7 +296,7 @@ int etb_set_reg(reg_t *reg, u32 value)
 	return ERROR_OK;
 }
 
-int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
+static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
 	int retval;
 
@@ -300,19 +304,19 @@ int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
-		LOG_ERROR("register write failed");
+		LOG_ERROR("ETB: register write failed");
 		return retval;
 	}
 	return ERROR_OK;
 }
 
-int etb_write_reg(reg_t *reg, u32 value)
+static int etb_write_reg(struct reg *reg, uint32_t value)
 {
-	etb_reg_t *etb_reg = reg->arch_info;
-	u8 reg_addr = etb_reg->addr & 0x7f;
-	scan_field_t fields[3];
+	struct etb_reg *etb_reg = reg->arch_info;
+	uint8_t reg_addr = etb_reg->addr & 0x7f;
+	struct scan_field fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 
 	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
@@ -344,60 +348,44 @@ int etb_write_reg(reg_t *reg, u32 value)
 	return ERROR_OK;
 }
 
-int etb_store_reg(reg_t *reg)
-{
-	return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
-
-static int etb_register_commands(struct command_context_s *cmd_ctx)
+COMMAND_HANDLER(handle_etb_config_command)
 {
-	command_t *etb_cmd;
+	struct target *target;
+	struct jtag_tap *tap;
+	struct arm *arm;
 
-	etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
-
-	register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
-
-	return ERROR_OK;
-}
-
-static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
-{
-	target_t *target;
-	jtag_tap_t *tap;
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
-
-	if (argc != 2)
+	if (CMD_ARGC != 2)
 	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	target = get_target(args[0]);
+	target = get_target(CMD_ARGV[0]);
 
 	if (!target)
 	{
-		LOG_ERROR("target '%s' not defined", args[0]);
+		LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
-	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
+		command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
-	tap = jtag_tap_by_string( args[1] );
+	tap = jtag_tap_by_string(CMD_ARGV[1]);
 	if (tap == NULL)
 	{
-		command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
+		command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
 		return ERROR_FAIL;
 	}
 
-	if (arm7_9->etm_ctx)
+	if (arm->etm)
 	{
-		etb_t *etb = malloc(sizeof(etb_t));
+		struct etb *etb = malloc(sizeof(struct etb));
 
-		arm7_9->etm_ctx->capture_driver_priv = etb;
+		arm->etm->capture_driver_priv = etb;
 
 		etb->tap  = tap;
 		etb->cur_scan_chain = 0xffffffff;
@@ -407,16 +395,86 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
 	}
 	else
 	{
-		LOG_ERROR("target has no ETM defined, ETB left unconfigured");
+		LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(handle_etb_trigger_percent_command)
+{
+	struct target *target;
+	struct arm *arm;
+	struct etm_context *etm;
+	struct etb *etb;
+
+	target = get_current_target(CMD_CTX);
+	arm = target_to_arm(target);
+	if (!is_arm(arm))
+	{
+		command_print(CMD_CTX, "ETB: current target isn't an ARM");
+		return ERROR_FAIL;
+	}
+
+	etm = arm->etm;
+	if (!etm) {
+		command_print(CMD_CTX, "ETB: target has no ETM configured");
 		return ERROR_FAIL;
 	}
+	if (etm->capture_driver != &etb_capture_driver) {
+		command_print(CMD_CTX, "ETB: target not using ETB");
+		return ERROR_FAIL;
+	}
+	etb = arm->etm->capture_driver_priv;
+
+	if (CMD_ARGC > 0) {
+		uint32_t new_value;
+
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
+		if ((new_value < 2) || (new_value > 100))
+			command_print(CMD_CTX,
+				"valid percentages are 2%% to 100%%");
+		else
+			etb->trigger_percent = (unsigned) new_value;
+	}
+
+	command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
+			etb->trigger_percent);
 
 	return ERROR_OK;
 }
 
-static int etb_init(etm_context_t *etm_ctx)
+static const struct command_registration etb_config_command_handlers[] = {
+	{
+		.name = "config",
+		.handler = &handle_etb_config_command,
+		.mode = COMMAND_CONFIG,
+		.usage = "target tap",
+	},
+	{
+		.name = "trigger_percent",
+		.handler = &handle_etb_trigger_percent_command,
+		.mode = COMMAND_EXEC,
+		.help = "percent of trace buffer to be filled "
+			"after the trigger occurs",
+		.usage = "[percent]",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration etb_command_handlers[] = {
+	{
+		.name = "etb",
+		.mode = COMMAND_ANY,
+		.help = "Emebdded Trace Buffer command group",
+		.chain = etb_config_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static int etb_init(struct etm_context *etm_ctx)
 {
-	etb_t *etb = etm_ctx->capture_driver_priv;
+	struct etb *etb = etm_ctx->capture_driver_priv;
 
 	etb->etm_ctx = etm_ctx;
 
@@ -428,70 +486,69 @@ static int etb_init(etm_context_t *etm_ctx)
 	etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 	etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 
+	etb->trigger_percent = 50;
+
 	return ERROR_OK;
 }
 
-static trace_status_t etb_status(etm_context_t *etm_ctx)
+static trace_status_t etb_status(struct etm_context *etm_ctx)
 {
-	etb_t *etb = etm_ctx->capture_driver_priv;
+	struct etb *etb = etm_ctx->capture_driver_priv;
+	struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
+	struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
+	trace_status_t retval = 0;
+	int etb_timeout = 100;
 
 	etb->etm_ctx = etm_ctx;
 
-	/* if tracing is currently idle, return this information */
-	if (etm_ctx->capture_status == TRACE_IDLE)
-	{
-		return etm_ctx->capture_status;
-	}
-	else if (etm_ctx->capture_status & TRACE_RUNNING)
-	{
-		reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
-		int etb_timeout = 100;
+	/* read control and status registers */
+	etb_read_reg(control);
+	etb_read_reg(status);
+	jtag_execute_queue();
 
-		/* trace is running, check the ETB status flags */
-		etb_get_reg(etb_status_reg);
+	/* See if it's (still) active */
+	retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 
-		/* check Full bit to identify an overflow */
-		if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
-			etm_ctx->capture_status |= TRACE_OVERFLOWED;
+	/* check Full bit to identify wraparound/overflow */
+	if (buf_get_u32(status->value, 0, 1) == 1)
+		retval |= TRACE_OVERFLOWED;
 
-		/* check Triggered bit to identify trigger condition */
-		if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
-			etm_ctx->capture_status |= TRACE_TRIGGERED;
+	/* check Triggered bit to identify trigger condition */
+	if (buf_get_u32(status->value, 1, 1) == 1)
+		retval |= TRACE_TRIGGERED;
 
-		/* check AcqComp to identify trace completion */
-		if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
-		{
-			while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
-			{
-				/* wait for data formatter idle */
-				etb_get_reg(etb_status_reg);
-			}
+	/* check AcqComp to see if trigger counter dropped to zero */
+	if (buf_get_u32(status->value, 2, 1) == 1) {
+		/* wait for DFEmpty */
+		while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
+			etb_get_reg(status);
 
-			if (etb_timeout == 0)
-			{
-				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
-					buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
-			}
+		if (etb_timeout == 0)
+			LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
+				(unsigned) buf_get_u32(status->value, 0, 4));
 
-			if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
-			{
-				LOG_ERROR("trace completed, but no trigger condition detected");
-			}
+		if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
+			LOG_WARNING("ETB: trace complete without triggering?");
 
-			etm_ctx->capture_status &= ~TRACE_RUNNING;
-			etm_ctx->capture_status |= TRACE_COMPLETED;
-		}
+		retval |= TRACE_COMPLETED;
 	}
 
-	return etm_ctx->capture_status;
+	/* NOTE: using a trigger is optional; and at least ETB11 has a mode
+	 * where it can ignore the trigger counter.
+	 */
+
+	/* update recorded state */
+	etm_ctx->capture_status = retval;
+
+	return retval;
 }
 
-static int etb_read_trace(etm_context_t *etm_ctx)
+static int etb_read_trace(struct etm_context *etm_ctx)
 {
-	etb_t *etb = etm_ctx->capture_driver_priv;
+	struct etb *etb = etm_ctx->capture_driver_priv;
 	int first_frame = 0;
 	int num_frames = etb->ram_depth;
-	u32 *trace_data = NULL;
+	uint32_t *trace_data = NULL;
 	int i, j;
 
 	etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
@@ -514,7 +571,7 @@ static int etb_read_trace(etm_context_t *etm_ctx)
 	etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 
 	/* read data into temporary array for unpacking */
-	trace_data = malloc(sizeof(u32) * num_frames);
+	trace_data = malloc(sizeof(uint32_t) * num_frames);
 	etb_read_ram(etb, trace_data, num_frames);
 
 	if (etm_ctx->trace_depth > 0)
@@ -529,7 +586,7 @@ static int etb_read_trace(etm_context_t *etm_ctx)
 	else
 		etm_ctx->trace_depth = num_frames;
 
-	etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
+	etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 
 	for (i = 0, j = 0; i < num_frames; i++)
 	{
@@ -549,32 +606,32 @@ static int etb_read_trace(etm_context_t *etm_ctx)
 				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+1 */
-			etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
-			etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
-			etm_ctx->trace_data[j+1].flags = 0;
+			/* trace word j + 1 */
+			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
+			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
+			etm_ctx->trace_data[j + 1].flags = 0;
 			if ((trace_data[i] & 0x8000) >> 15)
 			{
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+2 */
-			etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
-			etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
-			etm_ctx->trace_data[j+2].flags = 0;
+			/* trace word j + 2 */
+			etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
+			etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
+			etm_ctx->trace_data[j + 2].flags = 0;
 			if ((trace_data[i] & 0x800000) >> 23)
 			{
-				etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
-				etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
+				etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
 			j += 3;
@@ -595,18 +652,18 @@ static int etb_read_trace(etm_context_t *etm_ctx)
 				etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
-			/* trace word j+1 */
-			etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
-			etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
-			etm_ctx->trace_data[j+1].flags = 0;
+			/* trace word j + 1 */
+			etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
+			etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
+			etm_ctx->trace_data[j + 1].flags = 0;
 			if ((trace_data[i] & 0x800000) >> 23)
 			{
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 			}
-			if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
+			if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 			{
-				etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
-				etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
+				etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+				etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 			}
 
 			j += 2;
@@ -636,11 +693,11 @@ static int etb_read_trace(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-static int etb_start_capture(etm_context_t *etm_ctx)
+static int etb_start_capture(struct etm_context *etm_ctx)
 {
-	etb_t *etb = etm_ctx->capture_driver_priv;
-	u32 etb_ctrl_value = 0x1;
-	u32 trigger_count;
+	struct etb *etb = etm_ctx->capture_driver_priv;
+	uint32_t etb_ctrl_value = 0x1;
+	uint32_t trigger_count;
 
 	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 	{
@@ -652,10 +709,12 @@ static int etb_start_capture(etm_context_t *etm_ctx)
 		etb_ctrl_value |= 0x2;
 	}
 
-	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
+	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+		LOG_ERROR("ETB: can't run in multiplexed mode");
 		return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
+	}
 
-	trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
+	trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
 
 	etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 	etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
@@ -668,10 +727,10 @@ static int etb_start_capture(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-static int etb_stop_capture(etm_context_t *etm_ctx)
+static int etb_stop_capture(struct etm_context *etm_ctx)
 {
-	etb_t *etb = etm_ctx->capture_driver_priv;
-	reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
+	struct etb *etb = etm_ctx->capture_driver_priv;
+	struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 
 	etb_write_reg(etb_ctrl_reg, 0x0);
 	jtag_execute_queue();
@@ -682,10 +741,10 @@ static int etb_stop_capture(etm_context_t *etm_ctx)
 	return ERROR_OK;
 }
 
-etm_capture_driver_t etb_capture_driver =
+struct etm_capture_driver etb_capture_driver =
 {
 	.name = "etb",
-	.register_commands = etb_register_commands,
+	.commands = etb_command_handlers,
 	.init = etb_init,
 	.status = etb_status,
 	.start_capture = etb_start_capture,