X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fetb.c;h=974ab2b5c9f7585eb1259c688e9faf0ce28d04f5;hp=bc0e1bf2c714d7bfd7b720df41005125dde90ac7;hb=1163435e19f316a4a97fd33f1467f5c1684db654;hpb=f74e2e033a2ad082e5bef67d0ddedd1db3f58300 diff --git a/src/target/etb.c b/src/target/etb.c index bc0e1bf2c7..974ab2b5c9 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -21,7 +21,7 @@ #include "config.h" #endif -#include "armv4_5.h" +#include "arm.h" #include "etm.h" #include "etb.h" #include "register.h" @@ -54,16 +54,16 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr) { struct scan_field field; - field.tap = tap; field.num_bits = tap->ir_length; - field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); - buf_set_u32(field.out_value, 0, field.num_bits, new_instr); + void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_instr); field.in_value = NULL; - jtag_add_ir_scan(1, &field, jtag_get_end_state()); + jtag_add_ir_scan(tap, &field, TAP_IDLE); - free(field.out_value); + free(t); } return ERROR_OK; @@ -75,20 +75,20 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain) { struct scan_field field; - field.tap = etb->tap; field.num_bits = 5; - field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); - buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain); + void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + field.out_value = t; + buf_set_u32(t, 0, field.num_bits, new_scan_chain); field.in_value = NULL; /* select INTEST instruction */ etb_set_instr(etb, 0x2); - jtag_add_dr_scan(1, &field, jtag_get_end_state()); + jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE); etb->cur_scan_chain = new_scan_chain; - free(field.out_value); + free(t); } return ERROR_OK; @@ -166,7 +166,7 @@ static void etb_getbuf(jtag_callback_data_t arg) { uint8_t *in = (uint8_t *)arg; - *((uint32_t *)in) = buf_get_u32(in, 0, 32); + *((uint32_t *)arg) = buf_get_u32(in, 0, 32); } @@ -175,51 +175,46 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames) struct scan_field fields[3]; int i; - jtag_set_end_state(TAP_IDLE); etb_scann(etb, 0x0); etb_set_instr(etb, 0xc); - fields[0].tap = etb->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = NULL; - fields[1].tap = etb->tap; fields[1].num_bits = 7; - fields[1].out_value = malloc(1); - buf_set_u32(fields[1].out_value, 0, 7, 4); + uint8_t temp1; + fields[1].out_value = &temp1; + buf_set_u32(&temp1, 0, 7, 4); fields[1].in_value = NULL; - fields[2].tap = etb->tap; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); - buf_set_u32(fields[2].out_value, 0, 1, 0); + uint8_t temp2; + fields[2].out_value = &temp2; + buf_set_u32(&temp2, 0, 1, 0); fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE); for (i = 0; i < num_frames; i++) { /* ensure nR/W reamins set to read */ - buf_set_u32(fields[2].out_value, 0, 1, 0); + buf_set_u32(&temp2, 0, 1, 0); /* address remains set to 0x4 (RAM data) until we read the last frame */ if (i < num_frames - 1) - buf_set_u32(fields[1].out_value, 0, 7, 4); + buf_set_u32(&temp1, 0, 7, 4); else - buf_set_u32(fields[1].out_value, 0, 7, 0); + buf_set_u32(&temp1, 0, 7, 0); fields[0].in_value = (uint8_t *)(data + i); - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE); jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i)); } jtag_execute_queue(); - free(fields[1].out_value); - free(fields[2].out_value); - return ERROR_OK; } @@ -232,47 +227,42 @@ static int etb_read_reg_w_check(struct reg *reg, LOG_DEBUG("%i", (int)(etb_reg->addr)); - jtag_set_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); - fields[0].tap = etb_reg->etb->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; fields[0].in_value = NULL; fields[0].check_value = NULL; fields[0].check_mask = NULL; - fields[1].tap = etb_reg->etb->tap; fields[1].num_bits = 7; - fields[1].out_value = malloc(1); - buf_set_u32(fields[1].out_value, 0, 7, reg_addr); + uint8_t temp1; + fields[1].out_value = &temp1; + buf_set_u32(&temp1, 0, 7, reg_addr); fields[1].in_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; - fields[2].tap = etb_reg->etb->tap; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); - buf_set_u32(fields[2].out_value, 0, 1, 0); + uint8_t temp2; + fields[2].out_value = &temp2; + buf_set_u32(&temp2, 0, 1, 0); fields[2].in_value = NULL; fields[2].check_value = NULL; fields[2].check_mask = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE); /* read the identification register in the second run, to make sure we * don't read the ETB data register twice, skipping every second entry */ - buf_set_u32(fields[1].out_value, 0, 7, 0x0); + buf_set_u32(&temp1, 0, 7, 0x0); fields[0].in_value = reg->value; fields[0].check_value = check_value; fields[0].check_mask = check_mask; - jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); - - free(fields[1].out_value); - free(fields[2].out_value); + jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE); return ERROR_OK; } @@ -318,32 +308,28 @@ static int etb_write_reg(struct reg *reg, uint32_t value) LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value); - jtag_set_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); - fields[0].tap = etb_reg->etb->tap; fields[0].num_bits = 32; - fields[0].out_value = malloc(4); - buf_set_u32(fields[0].out_value, 0, 32, value); + uint8_t temp0[4]; + fields[0].out_value = temp0; + buf_set_u32(&temp0, 0, 32, value); fields[0].in_value = NULL; - fields[1].tap = etb_reg->etb->tap; fields[1].num_bits = 7; - fields[1].out_value = malloc(1); - buf_set_u32(fields[1].out_value, 0, 7, reg_addr); + uint8_t temp1; + fields[1].out_value = &temp1; + buf_set_u32(&temp1, 0, 7, reg_addr); fields[1].in_value = NULL; - fields[2].tap = etb_reg->etb->tap; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); - buf_set_u32(fields[2].out_value, 0, 1, 1); - + uint8_t temp2; + fields[2].out_value = &temp2; + buf_set_u32(&temp2, 0, 1, 1); fields[2].in_value = NULL; - free(fields[0].out_value); - free(fields[1].out_value); - free(fields[2].out_value); + jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE); return ERROR_OK; } @@ -402,12 +388,67 @@ COMMAND_HANDLER(handle_etb_config_command) return ERROR_OK; } +COMMAND_HANDLER(handle_etb_trigger_percent_command) +{ + struct target *target; + struct arm *arm; + struct etm_context *etm; + struct etb *etb; + + target = get_current_target(CMD_CTX); + arm = target_to_arm(target); + if (!is_arm(arm)) + { + command_print(CMD_CTX, "ETB: current target isn't an ARM"); + return ERROR_FAIL; + } + + etm = arm->etm; + if (!etm) { + command_print(CMD_CTX, "ETB: target has no ETM configured"); + return ERROR_FAIL; + } + if (etm->capture_driver != &etb_capture_driver) { + command_print(CMD_CTX, "ETB: target not using ETB"); + return ERROR_FAIL; + } + etb = arm->etm->capture_driver_priv; + + if (CMD_ARGC > 0) { + uint32_t new_value; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value); + if ((new_value < 2) || (new_value > 100)) + command_print(CMD_CTX, + "valid percentages are 2%% to 100%%"); + else + etb->trigger_percent = (unsigned) new_value; + } + + command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger", + etb->trigger_percent); + + return ERROR_OK; +} + static const struct command_registration etb_config_command_handlers[] = { { + /* NOTE: with ADIv5, ETBs are accessed using DAP operations, + * possibly over SWD, not through separate TAPs... + */ .name = "config", - .handler = &handle_etb_config_command, + .handler = handle_etb_config_command, .mode = COMMAND_CONFIG, - .usage = " ", + .help = "Associate ETB with target and JTAG TAP.", + .usage = "target tap", + }, + { + .name = "trigger_percent", + .handler = handle_etb_trigger_percent_command, + .mode = COMMAND_EXEC, + .help = "Set percent of trace buffer to be filled " + "after the trigger occurs (2..100).", + .usage = "[percent]", }, COMMAND_REGISTRATION_DONE }; @@ -435,6 +476,8 @@ static int etb_init(struct etm_context *etm_ctx) etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32); etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32); + etb->trigger_percent = 50; + return ERROR_OK; } @@ -526,9 +569,9 @@ static int etb_read_trace(struct etm_context *etm_ctx) free(etm_ctx->trace_data); } - if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) + if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) etm_ctx->trace_depth = num_frames * 3; - else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) + else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) etm_ctx->trace_depth = num_frames * 2; else etm_ctx->trace_depth = num_frames; @@ -537,7 +580,7 @@ static int etb_read_trace(struct etm_context *etm_ctx) for (i = 0, j = 0; i < num_frames; i++) { - if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) + if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) { /* trace word j */ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7; @@ -583,7 +626,7 @@ static int etb_read_trace(struct etm_context *etm_ctx) j += 3; } - else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) + else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) { /* trace word j */ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7; @@ -646,9 +689,9 @@ static int etb_start_capture(struct etm_context *etm_ctx) uint32_t etb_ctrl_value = 0x1; uint32_t trigger_count; - if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) + if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) { - if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) + if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) { LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port"); return ERROR_ETM_PORTMODE_NOT_SUPPORTED; @@ -656,12 +699,12 @@ static int etb_start_capture(struct etm_context *etm_ctx) etb_ctrl_value |= 0x2; } - if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) { + if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) { LOG_ERROR("ETB: can't run in multiplexed mode"); return ERROR_ETM_PORTMODE_NOT_SUPPORTED; } - trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100; + trigger_count = (etb->ram_depth * etb->trigger_percent) / 100; etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count); etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);