X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.h;h=39902fb3ec920add7511768ceed9f22a7b618e22;hp=dde37f65f372d2bd1e293516b34e75e5a807bde4;hb=HEAD;hpb=9b25f5eba2a8326e28146bbe315efe21e0cea91e diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index dde37f65f3..32acd705a5 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -1,32 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005, 2006 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * ***************************************************************************/ -#ifndef EMBEDDED_ICE_H -#define EMBEDDED_ICE_H -#include "target.h" -#include "register.h" -#include "arm_jtag.h" +#ifndef OPENOCD_TARGET_EMBEDDEDICE_H +#define OPENOCD_TARGET_EMBEDDEDICE_H + #include "arm7_9_common.h" -enum -{ +enum { EICE_DBG_CTRL = 0, EICE_DBG_STAT = 1, EICE_COMMS_CTRL = 2, @@ -46,17 +36,15 @@ enum EICE_VEC_CATCH = 16 }; -enum -{ +enum { EICE_DBG_CONTROL_ICEDIS = 5, - EICE_DBG_CONTROL_MONEN = 4, + EICE_DBG_CONTROL_MONEN = 4, EICE_DBG_CONTROL_INTDIS = 2, EICE_DBG_CONTROL_DBGRQ = 1, EICE_DBG_CONTROL_DBGACK = 0, }; -enum -{ +enum { EICE_DBG_STATUS_IJBIT = 5, EICE_DBG_STATUS_ITBIT = 4, EICE_DBG_STATUS_SYSCOMP = 3, @@ -65,108 +53,66 @@ enum EICE_DBG_STATUS_DBGACK = 0 }; -enum -{ +enum { EICE_W_CTRL_ENABLE = 0x100, EICE_W_CTRL_RANGE = 0x80, EICE_W_CTRL_CHAIN = 0x40, EICE_W_CTRL_EXTERN = 0x20, - EICE_W_CTRL_nTRANS = 0x10, - EICE_W_CTRL_nOPC = 0x8, + EICE_W_CTRL_NTRANS = 0x10, + EICE_W_CTRL_NOPC = 0x8, EICE_W_CTRL_MAS = 0x6, EICE_W_CTRL_ITBIT = 0x2, - EICE_W_CTRL_nRW = 0x1 + EICE_W_CTRL_NRW = 0x1 }; -enum -{ +enum { EICE_COMM_CTRL_WBIT = 1, EICE_COMM_CTRL_RBIT = 0 }; -typedef struct embeddedice_reg_s -{ +struct embeddedice_reg { int addr; - arm_jtag_t *jtag_info; -} embeddedice_reg_t; - -extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9); -extern int embeddedice_read_reg(reg_t *reg); -extern int embeddedice_write_reg(reg_t *reg, u32 value); -extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask); -extern int embeddedice_store_reg(reg_t *reg); -extern int embeddedice_set_reg(reg_t *reg, u32 value); -extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf); -extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size); -extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size); -extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout); - -/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of - * embeddedice_write_reg + struct arm_jtag *jtag_info; +}; + +struct reg_cache *embeddedice_build_reg_cache(struct target *target, + struct arm7_9_common *arm7_9); +void embeddedice_free_reg_cache(struct reg_cache *reg_cache); + +int embeddedice_setup(struct target *target); + +int embeddedice_read_reg(struct reg *reg); +int embeddedice_read_reg_w_check(struct reg *reg, + uint8_t *check_value, uint8_t *check_mask); + +void embeddedice_write_reg(struct reg *reg, uint32_t value); +void embeddedice_store_reg(struct reg *reg); + +void embeddedice_set_reg(struct reg *reg, uint32_t value); + +int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); +int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); + +int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout); + +/* If many embeddedice_write_reg() follow each other, then the >1 invocations can be + * this faster version of embeddedice_write_reg */ -static __inline__ void embeddedice_write_reg_inner(reg_t *reg, u32 value) +static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value) { - embeddedice_reg_t *ice_reg = reg->arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; -#if 1 - u32 values[3]; - int num_bits[3]; - - values[0]=value; - num_bits[0]=32; - values[1]=reg_addr; - num_bits[1]=5; - values[2]=1; - num_bits[2]=1; - - jtag_add_dr_out(ice_reg->jtag_info->chain_pos, - 3, - num_bits, - values, - -1); -#else - scan_field_t fields[3]; - u8 field0_out[4]; - u8 field1_out[1]; - u8 field2_out[1]; - - fields[0].device = ice_reg->jtag_info->chain_pos; - fields[0].num_bits = 32; - fields[0].out_value = field0_out; - buf_set_u32(fields[0].out_value, 0, 32, value); - fields[0].out_mask = NULL; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - - fields[1].device = ice_reg->jtag_info->chain_pos; - fields[1].num_bits = 5; - fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - - fields[2].device = ice_reg->jtag_info->chain_pos; - fields[2].num_bits = 1; - fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 1); - fields[2].out_mask = NULL; - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - - jtag_add_dr_scan(3, fields, -1); - -#endif + uint8_t out_reg_addr = (1 << 5) | reg_addr; + uint8_t out_value[4]; + buf_set_u32(out_value, 0, 32, value); + + struct scan_field fields[2] = { + { .num_bits = 32, .out_value = out_value }, + { .num_bits = 6, .out_value = &out_reg_addr }, + }; + + jtag_add_dr_scan(tap, 2, fields, TAP_IDLE); } +void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, + int little, int count); -#endif /* EMBEDDED_ICE_H */ +#endif /* OPENOCD_TARGET_EMBEDDEDICE_H */