X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.h;h=20cf2b4e7238d0915dd693d339ca59fc26328aad;hp=e038f92d06cd13bd88ce9a7814875b5258f4f29c;hb=96261e827782235709fcdfb2c1bbb93fedc977be;hpb=fbf5bec7f3ea9f4a9584099a12e71681cb55ce35

diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index e038f92d06..20cf2b4e72 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
+ *   Copyright (C) 2005, 2006 by Dominic Rath                              *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -23,6 +23,7 @@
 #include "target.h"
 #include "register.h"
 #include "arm_jtag.h"
+#include "arm7_9_common.h"
 
 enum
 {
@@ -41,7 +42,8 @@ enum
 	EICE_W1_DATA_VALUE = 12,
 	EICE_W1_DATA_MASK = 13,
 	EICE_W1_CONTROL_VALUE = 14,
-	EICE_W1_CONTROL_MASK = 15
+	EICE_W1_CONTROL_MASK = 15,
+	EICE_VEC_CATCH = 16
 };
 
 enum
@@ -55,6 +57,7 @@ enum
 
 enum
 {
+	EICE_DBG_STATUS_IJBIT = 5,
 	EICE_DBG_STATUS_ITBIT = 4,
 	EICE_DBG_STATUS_SYSCOMP = 3,
 	EICE_DBG_STATUS_IFEN = 2,
@@ -87,12 +90,81 @@ typedef struct embeddedice_reg_s
 	arm_jtag_t *jtag_info;
 } embeddedice_reg_t;
 
-extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);
+extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
 extern int embeddedice_read_reg(reg_t *reg);
 extern int embeddedice_write_reg(reg_t *reg, u32 value);
 extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
 extern int embeddedice_store_reg(reg_t *reg);
 extern int embeddedice_set_reg(reg_t *reg, u32 value);
-extern int embeddedice_set_reg_w_exec(reg_t *reg, u32 value);
+extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
+extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
+extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
+extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
+
+/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of 
+ * embeddedice_write_reg
+ */
+static __inline__ void embeddedice_write_reg_inner(int chain_pos, int reg_addr, u32 value)
+{
+#if 1
+	u32 values[3];
+	int num_bits[3];
+	
+	values[0]=value;
+	num_bits[0]=32;
+	values[1]=reg_addr;
+	num_bits[1]=5;
+	values[2]=1;
+	num_bits[2]=1;
+	
+	jtag_add_dr_out(chain_pos, 
+			3,
+			num_bits,
+			values,
+			-1);
+#else
+	scan_field_t fields[3];
+	u8 field0_out[4];
+	u8 field1_out[1];
+	u8 field2_out[1];
+
+	fields[0].device = ice_reg->jtag_info->chain_pos;
+	fields[0].num_bits = 32;
+	fields[0].out_value = field0_out;
+	buf_set_u32(fields[0].out_value, 0, 32, value);
+	fields[0].out_mask = NULL;
+	fields[0].in_value = NULL;
+	fields[0].in_check_value = NULL;
+	fields[0].in_check_mask = NULL;
+	fields[0].in_handler = NULL;
+	fields[0].in_handler_priv = NULL;
+	
+	fields[1].device = ice_reg->jtag_info->chain_pos;
+	fields[1].num_bits = 5;
+	fields[1].out_value = field1_out;
+	buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
+	fields[1].out_mask = NULL;
+	fields[1].in_value = NULL;
+	fields[1].in_check_value = NULL;
+	fields[1].in_check_mask = NULL;
+	fields[1].in_handler = NULL;
+	fields[1].in_handler_priv = NULL;
+
+	fields[2].device = ice_reg->jtag_info->chain_pos;
+	fields[2].num_bits = 1;
+	fields[2].out_value = field2_out;
+	buf_set_u32(fields[2].out_value, 0, 1, 1);
+	fields[2].out_mask = NULL;
+	fields[2].in_value = NULL;
+	fields[2].in_check_value = NULL;
+	fields[2].in_check_mask = NULL;
+	fields[2].in_handler = NULL;
+	fields[2].in_handler_priv = NULL;
+	
+	jtag_add_dr_scan(3, fields, -1);
+	
+#endif
+}
+
 
 #endif /* EMBEDDED_ICE_H */