X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=8a1b398715904da5f3659ed9f0eb444cbf36d89d;hp=270e52bfde5ae21f5ee3f3dd3e040bb1808fb140;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=e199d7bd2cd8a9c9dead86ad293ebf3dfd8be33a diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 270e52bfde..8a1b398715 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -2,6 +2,12 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -36,7 +42,7 @@ #include -bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = +bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] = { {"R", 1}, {"W", 1}, @@ -56,38 +62,39 @@ char* embeddedice_reg_list[] = { "debug_ctrl", "debug_status", - + "comms_ctrl", "comms_data", - + "watch 0 addr value", "watch 0 addr mask", "watch 0 data value", "watch 0 data mask", "watch 0 control value", "watch 0 control mask", - + "watch 1 addr value", "watch 1 addr mask", "watch 1 data value", "watch 1 data mask", "watch 1 control value", "watch 1 control mask", - + "vector catch" }; int embeddedice_reg_arch_type = -1; int embeddedice_get_reg(reg_t *reg); -int embeddedice_set_reg(reg_t *reg, u32 value); +void embeddedice_set_reg(reg_t *reg, u32 value); int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf); -int embeddedice_write_reg(reg_t *reg, u32 value); +void embeddedice_write_reg(reg_t *reg, u32 value); int embeddedice_read_reg(reg_t *reg); reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) { + int retval; reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = NULL; embeddedice_reg_t *arch_info = NULL; @@ -95,26 +102,26 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 int num_regs; int i; int eice_version = 0; - + /* register a register arch-type for EmbeddedICE registers only once */ if (embeddedice_reg_arch_type == -1) embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec); - + if (arm7_9->has_vector_catch) num_regs = 17; else num_regs = 16; - + /* the actual registers are kept in two arrays */ reg_list = calloc(num_regs, sizeof(reg_t)); arch_info = calloc(num_regs, sizeof(embeddedice_reg_t)); - + /* fill in values for the reg cache */ reg_cache->name = "EmbeddedICE registers"; reg_cache->next = NULL; reg_cache->reg_list = reg_list; reg_cache->num_regs = num_regs; - + /* set up registers */ for (i = 0; i < num_regs; i++) { @@ -130,13 +137,22 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arch_info[i].addr = embeddedice_reg_arch_info[i]; arch_info[i].jtag_info = jtag_info; } - + /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - jtag_execute_queue(); - + if ((retval=jtag_execute_queue())!=ERROR_OK) + { + for (i = 0; i < num_regs; i++) + { + free(reg_list[i].value); + } + free(reg_list); + free(arch_info); + return NULL; + } + eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); - + switch (eice_version) { case 1: @@ -149,7 +165,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arm7_9->has_single_step = 1; break; case 3: - ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); + LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_single_step = 1; @@ -172,40 +188,53 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arm7_9->has_monitor_mode = 1; break; case 7: - WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken"); + LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken"); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; break; default: - ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); + LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } - + + return reg_cache; +} + +int embeddedice_setup(target_t *target) +{ + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + /* explicitly disable monitor mode */ if (arm7_9->has_monitor_mode) { - embeddedice_read_reg(®_list[EICE_DBG_CTRL]); - jtag_execute_queue(); - buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value); + reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + + embeddedice_read_reg(dbg_ctrl); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + buf_set_u32(dbg_ctrl->value, 4, 1, 0); + embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); } - - return reg_cache; + return jtag_execute_queue(); } int embeddedice_get_reg(reg_t *reg) { - if (embeddedice_read_reg(reg) != ERROR_OK) + int retval; + if ((retval = embeddedice_read_reg(reg)) != ERROR_OK) { - ERROR("BUG: error scheduling EmbeddedICE register read"); - exit(-1); + LOG_ERROR("BUG: error scheduling EmbeddedICE register read"); + return retval; } - - if (jtag_execute_queue() != ERROR_OK) + + if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("register read failed"); + LOG_ERROR("register read failed"); + return retval; } - + return ERROR_OK; } @@ -219,10 +248,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); - + arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); - - fields[0].device = ice_reg->jtag_info->chain_pos; + + fields[0].tap = ice_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; fields[0].out_mask = NULL; @@ -231,8 +260,8 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - - fields[1].device = ice_reg->jtag_info->chain_pos; + + fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, reg_addr); @@ -243,7 +272,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = ice_reg->jtag_info->chain_pos; + fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); @@ -253,18 +282,18 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); - + fields[0].in_value = reg->value; jtag_set_check_value(fields+0, check_value, check_mask, NULL); - + /* when reading the DCC data register, leaving the address field set to * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - + jtag_add_dr_scan(3, fields, -1); return ERROR_OK; @@ -283,8 +312,8 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) jtag_add_end_state(TAP_RTI); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - - fields[0].device = jtag_info->chain_pos; + + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -293,8 +322,8 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - - fields[1].device = jtag_info->chain_pos; + + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); @@ -305,7 +334,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); @@ -315,9 +344,9 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); - + while (size > 0) { /* when reading the last item, set the register address to the DCC control reg, @@ -325,70 +354,65 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) */ if (size == 1) buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - + fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = data; jtag_add_dr_scan(3, fields, -1); - + data++; size--; } - + return jtag_execute_queue(); } int embeddedice_read_reg(reg_t *reg) { - return embeddedice_read_reg_w_check(reg, NULL, NULL); + return embeddedice_read_reg_w_check(reg, NULL, NULL); } -int embeddedice_set_reg(reg_t *reg, u32 value) +void embeddedice_set_reg(reg_t *reg, u32 value) { - if (embeddedice_write_reg(reg, value) != ERROR_OK) - { - ERROR("BUG: error scheduling EmbeddedICE register write"); - exit(-1); - } - + embeddedice_write_reg(reg, value); + buf_set_u32(reg->value, 0, reg->size, value); reg->valid = 1; reg->dirty = 0; - - return ERROR_OK; + } int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) { + int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - - if (jtag_execute_queue() != ERROR_OK) + + if ((retval = jtag_execute_queue()) != ERROR_OK) { - ERROR("register write failed"); - exit(-1); + LOG_ERROR("register write failed"); + return retval; } return ERROR_OK; } -int embeddedice_write_reg(reg_t *reg, u32 value) +void embeddedice_write_reg(reg_t *reg, u32 value) { embeddedice_reg_t *ice_reg = reg->arch_info; - DEBUG("%i: 0x%8.8x", ice_reg->addr, value); - + LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); + jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); - + arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); u8 reg_addr = ice_reg->addr & 0x1f; - embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value); - - return ERROR_OK; + embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); + } -int embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(reg_t *reg) { - return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); + embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } /* send words of 32 bit to the DCC @@ -406,7 +430,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = field0_out; fields[0].out_mask = NULL; @@ -416,7 +440,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); @@ -427,7 +451,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 1); @@ -475,7 +499,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -485,7 +509,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); @@ -496,7 +520,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); @@ -524,3 +548,14 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) return ERROR_TARGET_TIMEOUT; } + +/* this is the inner loop of the open loop DCC write of data to target */ +void MINIDRIVER(embeddedice_write_dcc)(jtag_tap_t *tap, int reg_addr, u8 *buffer, int little, int count) +{ + int i; + for (i = 0; i < count; i++) + { + embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little)); + buffer += 4; + } +}