X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=7ef4ac421b5aee57f69a245baaa6ca45ed63c6c7;hp=59cd5624f0be07461eaba058718c231cebd5c521;hb=263b4b9057b4e34eec8b39c4f165d370cb51a9e3;hpb=7f6bab0c4c36d7a64f933904e5add9bc6b36d78c

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 59cd5624f0..7ef4ac421b 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -47,6 +47,8 @@
  * core entered debug mode.
  */
 
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+
 /*
  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  */
@@ -357,7 +359,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bits 36:32 -- register */
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = reg_addr;
+	field1_out[0] = reg_addr;
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
@@ -365,7 +367,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bit 37 -- 0/read */
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
@@ -382,7 +384,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	 * EICE_COMMS_DATA would read the register twice
 	 * reading the control register is safe
 	 */
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 	/* traverse Update-DR, reading but with no other side effects */
 	jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
@@ -413,12 +415,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -429,7 +431,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 		 * to avoid reading additional data from the DCC data reg
 		 */
 		if (size == 1)
-			fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+			field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 		fields[0].in_value = (uint8_t *)data;
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -469,7 +471,7 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
 	int retval;
 
@@ -529,18 +531,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 1;
+	field2_out[0] = 1;
 
 	fields[2].in_value = NULL;
 
 	while (size > 0)
 	{
-		buf_set_u32(fields[0].out_value, 0, 32, *data);
+		buf_set_u32(field0_out, 0, 32, *data);
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 		data++;
@@ -581,12 +583,12 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);