X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=4693fcc2274390e900b1103ea45882ebd43f345e;hp=169ad2c302e733f1fafc6c2f9f63d55eb6aeaeee;hb=e018c7c1d29e8dabb9b4a90bb9eb3574eb1668bb;hpb=2f7fc2921d5769799f1bd527b49a7a877b4c8fa0 diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 169ad2c302..4693fcc227 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -28,15 +28,15 @@ #endif #include "embeddedice.h" - -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) +#include "register.h" /** * @file * * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT) * module found on scan chain 2 in ARM7, ARM9, and some other families - * of ARM cores. + * of ARM cores. The module is called "EmbeddedICE-RT" if it has + * monitor mode support. * * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug * Communications Channel (DCC) used to read or write 32-bit words to @@ -144,9 +144,7 @@ static const struct { }; -static int embeddedice_reg_arch_type = -1; - -static int embeddedice_get_reg(reg_t *reg) +static int embeddedice_get_reg(struct reg *reg) { int retval; @@ -158,34 +156,34 @@ static int embeddedice_get_reg(reg_t *reg) return retval; } +static const struct reg_arch_type eice_reg_type = { + .get = embeddedice_get_reg, + .set = embeddedice_set_reg_w_exec, +}; + /** * Probe EmbeddedICE module and set up local records of its registers. * Different versions of the modules have different capabilities, such as * hardware support for vector_catch, single stepping, and monitor mode. */ -reg_cache_t * -embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) +struct reg_cache * +embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) { int retval; - reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = NULL; + struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = NULL; struct embeddedice_reg *arch_info = NULL; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; - /* register arch-type for EmbeddedICE registers only once */ - if (embeddedice_reg_arch_type == -1) - embeddedice_reg_arch_type = register_reg_arch_type( - embeddedice_get_reg, embeddedice_set_reg_w_exec); - /* vector_catch isn't always present */ if (!arm7_9->has_vector_catch) num_regs--; /* the actual registers are kept in two arrays */ - reg_list = calloc(num_regs, sizeof(reg_t)); + reg_list = calloc(num_regs, sizeof(struct reg)); arch_info = calloc(num_regs, sizeof(struct embeddedice_reg)); /* fill in values for the reg cache */ @@ -194,6 +192,11 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) reg_cache->reg_list = reg_list; reg_cache->num_regs = num_regs; + /* FIXME the second watchpoint unit on Feroceon and Dragonite + * seems not to work ... we should have a way to not set up + * its four registers here! + */ + /* set up registers */ for (i = 0; i < num_regs; i++) { @@ -201,11 +204,9 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) reg_list[i].size = eice_regs[i].width; reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; - reg_list[i].arch_type = embeddedice_reg_arch_type; + reg_list[i].type = &eice_reg_type; arch_info[i].addr = eice_regs[i].addr; arch_info[i].jtag_info = jtag_info; } @@ -286,21 +287,26 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) * in some unusual bits. Let feroceon.c validate it * and do the appropriate setup itself. */ - if (strcmp(target_get_name(target), "feroceon") == 0 || - strcmp(target_get_name(target), "dragonite") == 0) + if (strcmp(target_type_name(target), "feroceon") == 0 || + strcmp(target_type_name(target), "dragonite") == 0) break; LOG_ERROR("unknown EmbeddedICE version " "(comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } + /* On Feroceon and Dragonite the second unit is seemingly missing. */ + LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s", + target_name(target), arm7_9->wp_available_max, + (arm7_9->wp_available_max != 1) ? "s" : ""); + return reg_cache; } /** * Initialize EmbeddedICE module, if needed. */ -int embeddedice_setup(target_t *target) +int embeddedice_setup(struct target *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -312,7 +318,7 @@ int embeddedice_setup(target_t *target) */ if (arm7_9->has_monitor_mode) { - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -328,7 +334,7 @@ int embeddedice_setup(target_t *target) * optionally checking the value read. * Note that at this level, all registers are 32 bits wide. */ -int embeddedice_read_reg_w_check(reg_t *reg, +int embeddedice_read_reg_w_check(struct reg *reg, uint8_t *check_value, uint8_t *check_mask) { struct embeddedice_reg *ice_reg = reg->arch_info; @@ -343,7 +349,6 @@ int embeddedice_read_reg_w_check(reg_t *reg, arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); /* bits 31:0 -- data (ignored here) */ - fields[0].tap = ice_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; fields[0].in_value = NULL; @@ -351,25 +356,23 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[0].check_mask = NULL; /* bits 36:32 -- register */ - fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + fields[1].out_value[0] = reg_addr; fields[1].in_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; /* bit 37 -- 0/read */ - fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; fields[2].check_value = NULL; fields[2].check_mask = NULL; /* traverse Update-DR, setting address for the next read */ - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state()); /* bits 31:0 -- the data we're reading (and maybe checking) */ fields[0].in_value = reg->value; @@ -380,10 +383,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; /* traverse Update-DR, reading but with no other side effects */ - jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); + jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state()); return ERROR_OK; } @@ -406,24 +409,21 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state()); while (size > 0) { @@ -431,11 +431,10 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz * to avoid reading additional data from the DCC data reg */ if (size == 1) - buf_set_u32(fields[1].out_value, 0, 5, - eice_regs[EICE_COMMS_CTRL].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr; fields[0].in_value = (uint8_t *)data; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state()); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data); data++; @@ -449,7 +448,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz * Queue a read for an EmbeddedICE register into the register cache, * not checking the value read. */ -int embeddedice_read_reg(reg_t *reg) +int embeddedice_read_reg(struct reg *reg) { return embeddedice_read_reg_w_check(reg, NULL, NULL); } @@ -458,7 +457,7 @@ int embeddedice_read_reg(reg_t *reg) * Queue a write for an EmbeddedICE register, updating the register cache. * Uses embeddedice_write_reg(). */ -void embeddedice_set_reg(reg_t *reg, uint32_t value) +void embeddedice_set_reg(struct reg *reg, uint32_t value) { embeddedice_write_reg(reg, value); @@ -472,7 +471,7 @@ void embeddedice_set_reg(reg_t *reg, uint32_t value) * Write an EmbeddedICE register, updating the register cache. * Uses embeddedice_set_reg(); not queued. */ -int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) +int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; @@ -485,7 +484,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) /** * Queue a write for an EmbeddedICE register, bypassing the register cache. */ -void embeddedice_write_reg(reg_t *reg, uint32_t value) +void embeddedice_write_reg(struct reg *reg, uint32_t value) { struct embeddedice_reg *ice_reg = reg->arch_info; @@ -504,7 +503,7 @@ void embeddedice_write_reg(reg_t *reg, uint32_t value) * Queue a write for an EmbeddedICE register, using cached value. * Uses embeddedice_write_reg(). */ -void embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(struct reg *reg) { embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } @@ -528,28 +527,25 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = field0_out; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 1); + fields[2].out_value[0] = 1; fields[2].in_value = NULL; while (size > 0) { buf_set_u32(fields[0].out_value, 0, 32, *data); - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state()); data++; size--; @@ -584,27 +580,24 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = field0_in; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_value[0] = 0; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state()); gettimeofday(&lap, NULL); do { - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state()); if ((retval = jtag_execute_queue()) != ERROR_OK) return retval;