X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fdsp563xx.c;h=a0e120627659ffd7c8f37bd5d28cea80e254451a;hp=10365dfdd76eb254670d6396b8135e2820cf7362;hb=fc553327c0a40b3039388bf9139aad2f9dc8fdf1;hpb=aa9baf11a8080cab47f19905a0e7697a1128724e diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 10365dfdd7..a0e1206276 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -25,6 +25,7 @@ #include "target.h" #include "target_type.h" +#include "algorithm.h" #include "register.h" #include "dsp563xx.h" #include "dsp563xx_once.h" @@ -92,35 +93,120 @@ #define ASM_REG_W_AAR2 0xFFFFF7 #define ASM_REG_W_AAR3 0xFFFFF6 +enum once_reg_idx { + ONCE_REG_IDX_OSCR=0, + ONCE_REG_IDX_OMBC=1, + ONCE_REG_IDX_OBCR=2, + ONCE_REG_IDX_OMLR0=3, + ONCE_REG_IDX_OMLR1=4, + ONCE_REG_IDX_OGDBR=5, + ONCE_REG_IDX_OPDBR=6, + ONCE_REG_IDX_OPILR=7, + ONCE_REG_IDX_PDB=8, + ONCE_REG_IDX_OTC=9, + ONCE_REG_IDX_OPABFR=10, + ONCE_REG_IDX_OPABDR=11, + ONCE_REG_IDX_OPABEX=12, + ONCE_REG_IDX_OPABF0=13, + ONCE_REG_IDX_OPABF1=14, + ONCE_REG_IDX_OPABF2=15, + ONCE_REG_IDX_OPABF3=16, + ONCE_REG_IDX_OPABF4=17, + ONCE_REG_IDX_OPABF5=18, + ONCE_REG_IDX_OPABF6=19, + ONCE_REG_IDX_OPABF7=20, + ONCE_REG_IDX_OPABF8=21, + ONCE_REG_IDX_OPABF9=22, + ONCE_REG_IDX_OPABF10=23, + ONCE_REG_IDX_OPABF11=24, +}; + static struct once_reg once_regs[] = { - {0, 0x00, 24, "OSCR", 0}, - {1, 0x01, 24, "OMBC", 0}, - {2, 0x02, 24, "OBCR", 0}, - {3, 0x05, 24, "OMLR0", 0}, - {4, 0x06, 24, "OMLR1", 0}, - {5, 0x09, 24, "OGDBR", 0}, - {6, 0x0a, 24, "OPDBR", 0}, - {7, 0x0b, 24, "OPILR", 0}, - {8, 0x0c, 24, "PDB", 0}, - {9, 0x0d, 24, "OTC", 0}, - {10, 0x0f, 24, "OPABFR", 0}, - {11, 0x10, 24, "OPABDR", 0}, - {12, 0x11, 24, "OPABEX", 0}, - {13, 0x12, 25, "OPABF0", 0}, - {14, 0x12, 25, "OPABF1", 0}, - {15, 0x12, 25, "OPABF2", 0}, - {16, 0x12, 25, "OPABF3", 0}, - {17, 0x12, 25, "OPABF4", 0}, - {18, 0x12, 25, "OPABF5", 0}, - {19, 0x12, 25, "OPABF6", 0}, - {20, 0x12, 25, "OPABF7", 0}, - {21, 0x12, 25, "OPABF8", 0}, - {22, 0x12, 25, "OPABF9", 0}, - {23, 0x12, 25, "OPABF10", 0}, - {24, 0x12, 25, "OPABF11", 0}, + {ONCE_REG_IDX_OSCR, DSP563XX_ONCE_OSCR, 24, "OSCR", 0}, + {ONCE_REG_IDX_OMBC, DSP563XX_ONCE_OMBC, 24, "OMBC", 0}, + {ONCE_REG_IDX_OBCR, DSP563XX_ONCE_OBCR, 24, "OBCR", 0}, + {ONCE_REG_IDX_OMLR0, DSP563XX_ONCE_OMLR0, 24, "OMLR0", 0}, + {ONCE_REG_IDX_OMLR1, DSP563XX_ONCE_OMLR1, 24, "OMLR1", 0}, + {ONCE_REG_IDX_OGDBR, DSP563XX_ONCE_OGDBR, 24, "OGDBR", 0}, + {ONCE_REG_IDX_OPDBR, DSP563XX_ONCE_OPDBR, 24, "OPDBR", 0}, + {ONCE_REG_IDX_OPILR, DSP563XX_ONCE_OPILR, 24, "OPILR", 0}, + {ONCE_REG_IDX_PDB, DSP563XX_ONCE_PDBGOTO, 24, "PDB", 0}, + {ONCE_REG_IDX_OTC, DSP563XX_ONCE_OTC, 24, "OTC", 0}, + {ONCE_REG_IDX_OPABFR, DSP563XX_ONCE_OPABFR, 24, "OPABFR", 0}, + {ONCE_REG_IDX_OPABDR, DSP563XX_ONCE_OPABDR, 24, "OPABDR", 0}, + {ONCE_REG_IDX_OPABEX, DSP563XX_ONCE_OPABEX, 24, "OPABEX", 0}, + {ONCE_REG_IDX_OPABF0, DSP563XX_ONCE_OPABF11, 25, "OPABF0", 0}, + {ONCE_REG_IDX_OPABF1, DSP563XX_ONCE_OPABF11, 25, "OPABF1", 0}, + {ONCE_REG_IDX_OPABF2, DSP563XX_ONCE_OPABF11, 25, "OPABF2", 0}, + {ONCE_REG_IDX_OPABF3, DSP563XX_ONCE_OPABF11, 25, "OPABF3", 0}, + {ONCE_REG_IDX_OPABF4, DSP563XX_ONCE_OPABF11, 25, "OPABF4", 0}, + {ONCE_REG_IDX_OPABF5, DSP563XX_ONCE_OPABF11, 25, "OPABF5", 0}, + {ONCE_REG_IDX_OPABF6, DSP563XX_ONCE_OPABF11, 25, "OPABF6", 0}, + {ONCE_REG_IDX_OPABF7, DSP563XX_ONCE_OPABF11, 25, "OPABF7", 0}, + {ONCE_REG_IDX_OPABF8, DSP563XX_ONCE_OPABF11, 25, "OPABF8", 0}, + {ONCE_REG_IDX_OPABF9, DSP563XX_ONCE_OPABF11, 25, "OPABF9", 0}, + {ONCE_REG_IDX_OPABF10, DSP563XX_ONCE_OPABF11, 25, "OPABF10", 0}, + {ONCE_REG_IDX_OPABF11, DSP563XX_ONCE_OPABF11, 25, "OPABF11", 0}, // {25,0x1f,24,"NRSEL",0}, }; +enum dsp563xx_reg_idx { + DSP563XX_REG_IDX_R0=0, + DSP563XX_REG_IDX_R1=1, + DSP563XX_REG_IDX_R2=2, + DSP563XX_REG_IDX_R3=3, + DSP563XX_REG_IDX_R4=4, + DSP563XX_REG_IDX_R5=5, + DSP563XX_REG_IDX_R6=6, + DSP563XX_REG_IDX_R7=7, + DSP563XX_REG_IDX_N0=8, + DSP563XX_REG_IDX_N1=9, + DSP563XX_REG_IDX_N2=10, + DSP563XX_REG_IDX_N3=11, + DSP563XX_REG_IDX_N4=12, + DSP563XX_REG_IDX_N5=13, + DSP563XX_REG_IDX_N6=14, + DSP563XX_REG_IDX_N7=15, + DSP563XX_REG_IDX_M0=16, + DSP563XX_REG_IDX_M1=17, + DSP563XX_REG_IDX_M2=18, + DSP563XX_REG_IDX_M3=19, + DSP563XX_REG_IDX_M4=20, + DSP563XX_REG_IDX_M5=21, + DSP563XX_REG_IDX_M6=22, + DSP563XX_REG_IDX_M7=23, + DSP563XX_REG_IDX_X0=24, + DSP563XX_REG_IDX_X1=25, + DSP563XX_REG_IDX_Y0=26, + DSP563XX_REG_IDX_Y1=27, + DSP563XX_REG_IDX_A0=28, + DSP563XX_REG_IDX_A1=29, + DSP563XX_REG_IDX_A2=30, + DSP563XX_REG_IDX_B0=31, + DSP563XX_REG_IDX_B1=32, + DSP563XX_REG_IDX_B2=33, + DSP563XX_REG_IDX_SSH=34, + DSP563XX_REG_IDX_SSL=35, + DSP563XX_REG_IDX_SP=36, + DSP563XX_REG_IDX_EP=37, + DSP563XX_REG_IDX_SZ=38, + DSP563XX_REG_IDX_SC=39, + DSP563XX_REG_IDX_PC=40, + DSP563XX_REG_IDX_SR=41, + DSP563XX_REG_IDX_OMR=42, + DSP563XX_REG_IDX_LA=43, + DSP563XX_REG_IDX_LC=44, + DSP563XX_REG_IDX_VBA=45, + DSP563XX_REG_IDX_IPRC=46, + DSP563XX_REG_IDX_IPRP=47, + DSP563XX_REG_IDX_BCR=48, + DSP563XX_REG_IDX_DCR=49, + DSP563XX_REG_IDX_AAR0=50, + DSP563XX_REG_IDX_AAR1=51, + DSP563XX_REG_IDX_AAR2=52, + DSP563XX_REG_IDX_AAR3=53, +}; + static const struct { unsigned id; @@ -133,98 +219,77 @@ static const struct { /* *INDENT-OFF* */ /* address registers */ - { 0, "r0", 24, 0x10, ASM_REG_W_R0}, - { 1, "r1", 24, 0x11, ASM_REG_W_R1}, - { 2, "r2", 24, 0x12, ASM_REG_W_R2}, - { 3, "r3", 24, 0x13, ASM_REG_W_R3}, - { 4, "r4", 24, 0x14, ASM_REG_W_R4}, - { 5, "r5", 24, 0x15, ASM_REG_W_R5}, - { 6, "r6", 24, 0x16, ASM_REG_W_R6}, - { 7, "r7", 24, 0x17, ASM_REG_W_R7}, + {DSP563XX_REG_IDX_R0, "r0", 24, 0x10, ASM_REG_W_R0}, + {DSP563XX_REG_IDX_R1, "r1", 24, 0x11, ASM_REG_W_R1}, + {DSP563XX_REG_IDX_R2, "r2", 24, 0x12, ASM_REG_W_R2}, + {DSP563XX_REG_IDX_R3, "r3", 24, 0x13, ASM_REG_W_R3}, + {DSP563XX_REG_IDX_R4, "r4", 24, 0x14, ASM_REG_W_R4}, + {DSP563XX_REG_IDX_R5, "r5", 24, 0x15, ASM_REG_W_R5}, + {DSP563XX_REG_IDX_R6, "r6", 24, 0x16, ASM_REG_W_R6}, + {DSP563XX_REG_IDX_R7, "r7", 24, 0x17, ASM_REG_W_R7}, /* offset registers */ - { 8, "n0", 24, 0x18, ASM_REG_W_N0}, - { 9, "n1", 24, 0x19, ASM_REG_W_N1}, - {10, "n2", 24, 0x1a, ASM_REG_W_N2}, - {11, "n3", 24, 0x1b, ASM_REG_W_N3}, - {12, "n4", 24, 0x1c, ASM_REG_W_N4}, - {13, "n5", 24, 0x1d, ASM_REG_W_N5}, - {14, "n6", 24, 0x1e, ASM_REG_W_N6}, - {15, "n7", 24, 0x1f, ASM_REG_W_N7}, + {DSP563XX_REG_IDX_N0, "n0", 24, 0x18, ASM_REG_W_N0}, + {DSP563XX_REG_IDX_N1, "n1", 24, 0x19, ASM_REG_W_N1}, + {DSP563XX_REG_IDX_N2, "n2", 24, 0x1a, ASM_REG_W_N2}, + {DSP563XX_REG_IDX_N3, "n3", 24, 0x1b, ASM_REG_W_N3}, + {DSP563XX_REG_IDX_N4, "n4", 24, 0x1c, ASM_REG_W_N4}, + {DSP563XX_REG_IDX_N5, "n5", 24, 0x1d, ASM_REG_W_N5}, + {DSP563XX_REG_IDX_N6, "n6", 24, 0x1e, ASM_REG_W_N6}, + {DSP563XX_REG_IDX_N7, "n7", 24, 0x1f, ASM_REG_W_N7}, /* modifier registers */ - {16, "m0", 24, 0x20, ASM_REG_W_M0}, - {17, "m1", 24, 0x21, ASM_REG_W_M1}, - {18, "m2", 24, 0x22, ASM_REG_W_M2}, - {19, "m3", 24, 0x23, ASM_REG_W_M3}, - {20, "m4", 24, 0x24, ASM_REG_W_M4}, - {21, "m5", 24, 0x25, ASM_REG_W_M5}, - {22, "m6", 24, 0x26, ASM_REG_W_M6}, - {23, "m7", 24, 0x27, ASM_REG_W_M7}, + {DSP563XX_REG_IDX_M0, "m0", 24, 0x20, ASM_REG_W_M0}, + {DSP563XX_REG_IDX_M1, "m1", 24, 0x21, ASM_REG_W_M1}, + {DSP563XX_REG_IDX_M2, "m2", 24, 0x22, ASM_REG_W_M2}, + {DSP563XX_REG_IDX_M3, "m3", 24, 0x23, ASM_REG_W_M3}, + {DSP563XX_REG_IDX_M4, "m4", 24, 0x24, ASM_REG_W_M4}, + {DSP563XX_REG_IDX_M5, "m5", 24, 0x25, ASM_REG_W_M5}, + {DSP563XX_REG_IDX_M6, "m6", 24, 0x26, ASM_REG_W_M6}, + {DSP563XX_REG_IDX_M7, "m7", 24, 0x27, ASM_REG_W_M7}, /* data alu input register */ - {24, "x0", 24, 0x04, ASM_REG_W_X0}, - {25, "x1", 24, 0x05, ASM_REG_W_X1}, - {26, "y0", 24, 0x06, ASM_REG_W_Y0}, - {27, "y1", 24, 0x07, ASM_REG_W_Y1}, + {DSP563XX_REG_IDX_X0, "x0", 24, 0x04, ASM_REG_W_X0}, + {DSP563XX_REG_IDX_X1, "x1", 24, 0x05, ASM_REG_W_X1}, + {DSP563XX_REG_IDX_Y0, "y0", 24, 0x06, ASM_REG_W_Y0}, + {DSP563XX_REG_IDX_Y1, "y1", 24, 0x07, ASM_REG_W_Y1}, /* data alu accumulator register */ - {28, "a0", 24, 0x08, ASM_REG_W_A0}, - {29, "a1", 24, 0x0c, ASM_REG_W_A1}, - {30, "a2", 8, 0x0a, ASM_REG_W_A2}, - {31, "b0", 24, 0x09, ASM_REG_W_B0}, - {32, "b1", 24, 0x0d, ASM_REG_W_B1}, - {33, "b2", 8, 0x0b, ASM_REG_W_B2}, + {DSP563XX_REG_IDX_A0, "a0", 24, 0x08, ASM_REG_W_A0}, + {DSP563XX_REG_IDX_A1, "a1", 24, 0x0c, ASM_REG_W_A1}, + {DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2}, + {DSP563XX_REG_IDX_B0, "b0", 24, 0x09, ASM_REG_W_B0}, + {DSP563XX_REG_IDX_B1, "b1", 24, 0x0d, ASM_REG_W_B1}, + {DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2}, /* stack */ - {34, "ssh",24, 0x3c, ASM_REG_W_SSH}, - {35, "ssl",24, 0x3d, ASM_REG_W_SSL}, - {36, "sp", 24, 0x3b, ASM_REG_W_SP}, - {37, "ep", 24, 0x2a, ASM_REG_W_EP}, - {38, "sz", 24, 0x38, ASM_REG_W_SZ}, - {39, "sc", 24, 0x31, ASM_REG_W_SC}, + {DSP563XX_REG_IDX_SSH, "ssh",24, 0x3c, ASM_REG_W_SSH}, + {DSP563XX_REG_IDX_SSL, "ssl",24, 0x3d, ASM_REG_W_SSL}, + {DSP563XX_REG_IDX_SP, "sp", 24, 0x3b, ASM_REG_W_SP}, + {DSP563XX_REG_IDX_EP, "ep", 24, 0x2a, ASM_REG_W_EP}, + {DSP563XX_REG_IDX_SZ, "sz", 24, 0x38, ASM_REG_W_SZ}, + {DSP563XX_REG_IDX_SC, "sc", 24, 0x31, ASM_REG_W_SC}, /* system */ - {40, "pc", 24, 0x00, ASM_REG_W_PC}, - {41, "sr", 24, 0x39, ASM_REG_W_SR}, - {42, "omr",24, 0x3a, ASM_REG_W_OMR}, - {43, "la", 24, 0x3e, ASM_REG_W_LA}, - {44, "lc", 24, 0x3f, ASM_REG_W_LC}, + {DSP563XX_REG_IDX_PC, "pc", 24, 0x00, ASM_REG_W_PC}, + {DSP563XX_REG_IDX_SR, "sr", 24, 0x39, ASM_REG_W_SR}, + {DSP563XX_REG_IDX_OMR, "omr",24, 0x3a, ASM_REG_W_OMR}, + {DSP563XX_REG_IDX_LA, "la", 24, 0x3e, ASM_REG_W_LA}, + {DSP563XX_REG_IDX_LC, "lc", 24, 0x3f, ASM_REG_W_LC}, /* interrupt */ - {45, "vba", 24, 0x30, ASM_REG_W_VBA}, - {46, "iprc",24, 0x00, ASM_REG_W_IPRC}, - {47, "iprp",24, 0x00, ASM_REG_W_IPRP}, + {DSP563XX_REG_IDX_VBA, "vba", 24, 0x30, ASM_REG_W_VBA}, + {DSP563XX_REG_IDX_IPRC, "iprc",24, 0x00, ASM_REG_W_IPRC}, + {DSP563XX_REG_IDX_IPRP, "iprp",24, 0x00, ASM_REG_W_IPRP}, /* port a */ - {48, "bcr", 24, 0x00, ASM_REG_W_BCR}, - {49, "dcr", 24, 0x00, ASM_REG_W_DCR}, - {50, "aar0",24, 0x00, ASM_REG_W_AAR0}, - {51, "aar1",24, 0x00, ASM_REG_W_AAR1}, - {52, "aar2",24, 0x00, ASM_REG_W_AAR2}, - {53, "aar3",24, 0x00, ASM_REG_W_AAR3}, + {DSP563XX_REG_IDX_BCR, "bcr", 24, 0x00, ASM_REG_W_BCR}, + {DSP563XX_REG_IDX_DCR, "dcr", 24, 0x00, ASM_REG_W_DCR}, + {DSP563XX_REG_IDX_AAR0, "aar0",24, 0x00, ASM_REG_W_AAR0}, + {DSP563XX_REG_IDX_AAR1, "aar1",24, 0x00, ASM_REG_W_AAR1}, + {DSP563XX_REG_IDX_AAR2, "aar2",24, 0x00, ASM_REG_W_AAR2}, + {DSP563XX_REG_IDX_AAR3, "aar3",24, 0x00, ASM_REG_W_AAR3}, /* *INDENT-ON* */ }; -#define REG_NUM_R0 0 -#define REG_NUM_R1 1 -#define REG_NUM_N0 8 -#define REG_NUM_N1 9 -#define REG_NUM_M0 16 -#define REG_NUM_M1 17 -#define REG_NUM_SSH 34 -#define REG_NUM_SSL 35 -#define REG_NUM_SP 36 -#define REG_NUM_EP 37 -#define REG_NUM_SC 39 -#define REG_NUM_PC 40 -#define REG_NUM_SR 41 -#define REG_NUM_IPRC 46 -#define REG_NUM_IPRP 47 -#define REG_NUM_BCR 48 -#define REG_NUM_DCR 49 -#define REG_NUM_AAR0 50 -#define REG_NUM_AAR1 51 -#define REG_NUM_AAR2 52 -#define REG_NUM_AAR3 53 - enum memory_type { MEM_X = 0, MEM_Y = 1, MEM_P = 2, + MEM_L = 3, }; #define INSTR_JUMP 0x0AF080 @@ -239,6 +304,24 @@ enum memory_type */ #define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f)) +/* the gdb register list is send in this order */ +uint8_t gdb_reg_list_idx[] = { + DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0, + DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2, + DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR, + DSP563XX_REG_IDX_OMR,DSP563XX_REG_IDX_LA, DSP563XX_REG_IDX_LC, DSP563XX_REG_IDX_SSH, + DSP563XX_REG_IDX_SSL,DSP563XX_REG_IDX_SP, DSP563XX_REG_IDX_EP, DSP563XX_REG_IDX_SZ, + DSP563XX_REG_IDX_SC, DSP563XX_REG_IDX_VBA,DSP563XX_REG_IDX_IPRC, DSP563XX_REG_IDX_IPRP, + DSP563XX_REG_IDX_BCR,DSP563XX_REG_IDX_DCR,DSP563XX_REG_IDX_AAR0,DSP563XX_REG_IDX_AAR1, + DSP563XX_REG_IDX_AAR2,DSP563XX_REG_IDX_AAR3,DSP563XX_REG_IDX_R0,DSP563XX_REG_IDX_R1, + DSP563XX_REG_IDX_R2, DSP563XX_REG_IDX_R3, DSP563XX_REG_IDX_R4, DSP563XX_REG_IDX_R5, + DSP563XX_REG_IDX_R6, DSP563XX_REG_IDX_R7, DSP563XX_REG_IDX_N0, DSP563XX_REG_IDX_N1, + DSP563XX_REG_IDX_N2, DSP563XX_REG_IDX_N3, DSP563XX_REG_IDX_N4, DSP563XX_REG_IDX_N5, + DSP563XX_REG_IDX_N6, DSP563XX_REG_IDX_N7, DSP563XX_REG_IDX_M0, DSP563XX_REG_IDX_M1, + DSP563XX_REG_IDX_M2, DSP563XX_REG_IDX_M3, DSP563XX_REG_IDX_M4, DSP563XX_REG_IDX_M5, + DSP563XX_REG_IDX_M6, DSP563XX_REG_IDX_M7, +}; + static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { int i; @@ -257,7 +340,7 @@ static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_lis for (i = 0; i < DSP563XX_NUMCOREREGS; i++) { - (*reg_list)[i] = &dsp563xx->core_cache->reg_list[i]; + (*reg_list)[i] = &dsp563xx->core_cache->reg_list[gdb_reg_list_idx[i]]; } return ERROR_OK; @@ -267,13 +350,11 @@ static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_lis static int dsp563xx_read_core_reg(struct target *target, int num) { uint32_t reg_value; - struct dsp563xx_core_reg *dsp563xx_core_reg; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); if ((num < 0) || (num >= DSP563XX_NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; - dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info; reg_value = dsp563xx->core_regs[num]; buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value); dsp563xx->core_cache->reg_list[num].valid = 1; @@ -285,14 +366,12 @@ static int dsp563xx_read_core_reg(struct target *target, int num) static int dsp563xx_write_core_reg(struct target *target, int num) { uint32_t reg_value; - struct dsp563xx_core_reg *dsp563xx_core_reg; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); if ((num < 0) || (num >= DSP563XX_NUMCOREREGS)) return ERROR_INVALID_ARGUMENTS; reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32); - dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info; dsp563xx->core_regs[num] = reg_value; dsp563xx->core_cache->reg_list[num].valid = 1; dsp563xx->core_cache->reg_list[num].dirty = 0; @@ -300,21 +379,6 @@ static int dsp563xx_write_core_reg(struct target *target, int num) return ERROR_OK; } -static int dsp563xx_target_create(struct target *target, Jim_Interp * interp) -{ - struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common)); - - if (!dsp563xx) - return ERROR_INVALID_ARGUMENTS; - - dsp563xx->jtag_info.tap = target->tap; - target->arch_info = dsp563xx; - dsp563xx->read_core_reg = dsp563xx_read_core_reg; - dsp563xx->write_core_reg = dsp563xx_write_core_reg; - - return ERROR_OK; -} - static int dsp563xx_get_core_reg(struct reg *reg) { struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info; @@ -351,6 +415,48 @@ static int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf) return ERROR_OK; } +static const struct reg_arch_type dsp563xx_reg_type = { + .get = dsp563xx_get_core_reg, + .set = dsp563xx_set_core_reg, +}; + +static void dsp563xx_build_reg_cache(struct target *target) +{ + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS); + struct dsp563xx_core_reg *arch_info = malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS); + int i; + + /* Build the process context cache */ + cache->name = "dsp563xx registers"; + cache->next = NULL; + cache->reg_list = reg_list; + cache->num_regs = DSP563XX_NUMCOREREGS; + (*cache_p) = cache; + dsp563xx->core_cache = cache; + + for (i = 0; i < DSP563XX_NUMCOREREGS; i++) + { + arch_info[i].num = dsp563xx_regs[i].id; + arch_info[i].name = dsp563xx_regs[i].name; + arch_info[i].size = dsp563xx_regs[i].bits; + arch_info[i].eame = dsp563xx_regs[i].eame; + arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask; + arch_info[i].target = target; + arch_info[i].dsp563xx_common = dsp563xx; + reg_list[i].name = dsp563xx_regs[i].name; + reg_list[i].size = 32; //dsp563xx_regs[i].bits; + reg_list[i].value = calloc(1, 4); + reg_list[i].dirty = 0; + reg_list[i].valid = 0; + reg_list[i].type = &dsp563xx_reg_type; + reg_list[i].arch_info = &arch_info[i]; + } +} + static int dsp563xx_read_register(struct target *target, int num, int force); static int dsp563xx_write_register(struct target *target, int num, int force); @@ -361,22 +467,22 @@ static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); /* we use r0 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R0].valid) - dsp563xx->read_core_reg(target, REG_NUM_R0); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0); /* move source memory to r0 */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 0, EAME_R0, instr_mask); - if ((err = dsp563xx_once_execute_sw_ir_nq(target->tap, instr)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr)) != ERROR_OK) return err; /* move r0 to debug register */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, 0xfffffc); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, instr)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr)) != ERROR_OK) return err; /* read debug register */ - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, data)) != ERROR_OK) + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data)) != ERROR_OK) return err; /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; return ERROR_OK; } @@ -388,19 +494,19 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); /* we use r0 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R0].valid) - dsp563xx->read_core_reg(target, REG_NUM_R0); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0); /* move data to r0 */ - if ((err = dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, data)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x60F400, data)) != ERROR_OK) return err; /* move r0 to destination memory */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, instr_mask); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, instr)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr)) != ERROR_OK) return err; /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; return ERROR_OK; } @@ -411,87 +517,98 @@ static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t * da uint32_t instr; instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, eame, 0xfffffc); - if ((err = dsp563xx_once_execute_sw_ir_nq(target->tap, instr)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr)) != ERROR_OK) return err; /* nop */ - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0x000000)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000)) != ERROR_OK) return err; /* read debug register */ - return dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, data); + return dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data); } static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32_t data) { int err; - if ((err = dsp563xx_once_execute_dw_ir_nq(target->tap, instr_mask, data)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, instr_mask, data)) != ERROR_OK) return err; /* nop */ - return dsp563xx_once_execute_sw_ir(target->tap, 0x000000); + return dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000); } static int dsp563xx_reg_pc_read(struct target *target) { - int err; - uint32_t opabdr, opabex; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); /* pc was changed, nothing todo */ - if (dsp563xx->core_cache->reg_list[REG_NUM_PC].dirty) + if (dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) return ERROR_OK; - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR, &opabdr)) != ERROR_OK) - return err; - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &opabex)) != ERROR_OK) - return err; - /* conditional branch check */ - if (opabdr == opabex) + if ( once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg ) { - /* TODO: check the trace buffer and if a - * conditional branch is detected then decode - * the branch command and add the relative - * address to the current pc - */ - LOG_DEBUG("%s conditional branch not supported yet", __FUNCTION__); + if ( (once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0 ) + { + LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)", __FUNCTION__, + (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1), + once_regs[ONCE_REG_IDX_OPABDR].reg, + once_regs[ONCE_REG_IDX_OPABEX].reg); + + /* TODO: use disassembly to set correct pc offset + * read 2 words from OPABF11 and disasm the instruction + */ + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1) & 0x00FFFFFF; + } + else + { + if ( once_regs[ONCE_REG_IDX_OPABEX].reg == once_regs[ONCE_REG_IDX_OPABFR].reg ) + { + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg; + } + else + { + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg - 1; + } + } } else { - dsp563xx->core_regs[REG_NUM_PC] = opabex; - dsp563xx->read_core_reg(target, REG_NUM_PC); + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg; } + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_PC); + return ERROR_OK; } static int dsp563xx_reg_ssh_read(struct target *target) { int err; - uint32_t sp, sc, ep; + uint32_t sp; struct dsp563xx_core_reg *arch_info; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_SSH].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, REG_NUM_SP, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) return err; - sp = dsp563xx->core_regs[REG_NUM_SP]; - if ((err = dsp563xx_write_register(target, REG_NUM_SP, 0)) != ERROR_OK) + sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) return err; /* get a valid stack count */ - if ((err = dsp563xx_read_register(target, REG_NUM_SC, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SC, 0)) != ERROR_OK) return err; - sc = dsp563xx->core_regs[REG_NUM_SC]; - if ((err = dsp563xx_write_register(target, REG_NUM_SC, 0)) != ERROR_OK) + + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 0)) != ERROR_OK) return err; /* get a valid extended pointer */ - if ((err = dsp563xx_read_register(target, REG_NUM_EP, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_EP, 0)) != ERROR_OK) return err; - ep = dsp563xx->core_regs[REG_NUM_EP]; - if ((err = dsp563xx_write_register(target, REG_NUM_EP, 0)) != ERROR_OK) + + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 0)) != ERROR_OK) return err; if (!sp) @@ -503,16 +620,16 @@ static int dsp563xx_reg_ssh_read(struct target *target) if ((err = dsp563xx_reg_read(target, arch_info->eame, &sp)) != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, REG_NUM_SC, 1)) != ERROR_OK) + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 1)) != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, REG_NUM_SP, 1)) != ERROR_OK) + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, REG_NUM_EP, 1)) != ERROR_OK) + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 1)) != ERROR_OK) return err; } - dsp563xx->core_regs[REG_NUM_SSH] = sp; - dsp563xx->read_core_reg(target, REG_NUM_SSH); + dsp563xx->core_regs[DSP563XX_REG_IDX_SSH] = sp; + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSH); return ERROR_OK; } @@ -524,29 +641,29 @@ static int dsp563xx_reg_ssh_write(struct target *target) struct dsp563xx_core_reg *arch_info; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_SSH].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, REG_NUM_SP, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) return err; - sp = dsp563xx->core_regs[REG_NUM_SP]; + sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; if (sp) { sp--; /* write new stackpointer */ - dsp563xx->core_regs[REG_NUM_SP] = sp; - if ((err = dsp563xx->read_core_reg(target, REG_NUM_SP)) != ERROR_OK) + dsp563xx->core_regs[DSP563XX_REG_IDX_SP] = sp; + if ((err = dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SP)) != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, REG_NUM_SP, 1)) != ERROR_OK) + if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) return err; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, dsp563xx->core_regs[REG_NUM_SSH])) != ERROR_OK) + if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, dsp563xx->core_regs[DSP563XX_REG_IDX_SSH])) != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, REG_NUM_SP, 1)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, REG_NUM_SSH, 1)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SSH, 1)) != ERROR_OK) return err; } @@ -560,12 +677,12 @@ static int dsp563xx_reg_ssl_read(struct target *target) struct dsp563xx_core_reg *arch_info; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_SSL].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, REG_NUM_SP, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) return err; - sp = dsp563xx->core_regs[REG_NUM_SP]; + sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; if (!sp) { @@ -577,8 +694,8 @@ static int dsp563xx_reg_ssl_read(struct target *target) return err; } - dsp563xx->core_regs[REG_NUM_SSL] = sp; - dsp563xx->read_core_reg(target, REG_NUM_SSL); + dsp563xx->core_regs[DSP563XX_REG_IDX_SSL] = sp; + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSL); return ERROR_OK; } @@ -599,23 +716,23 @@ static int dsp563xx_read_register(struct target *target, int num, int force) switch (arch_info->num) { - case REG_NUM_SSH: + case DSP563XX_REG_IDX_SSH: err = dsp563xx_reg_ssh_read(target); break; - case REG_NUM_SSL: + case DSP563XX_REG_IDX_SSL: err = dsp563xx_reg_ssl_read(target); break; - case REG_NUM_PC: + case DSP563XX_REG_IDX_PC: err = dsp563xx_reg_pc_read(target); break; - case REG_NUM_IPRC: - case REG_NUM_IPRP: - case REG_NUM_BCR: - case REG_NUM_DCR: - case REG_NUM_AAR0: - case REG_NUM_AAR1: - case REG_NUM_AAR2: - case REG_NUM_AAR3: + case DSP563XX_REG_IDX_IPRC: + case DSP563XX_REG_IDX_IPRP: + case DSP563XX_REG_IDX_BCR: + case DSP563XX_REG_IDX_DCR: + case DSP563XX_REG_IDX_AAR0: + case DSP563XX_REG_IDX_AAR1: + case DSP563XX_REG_IDX_AAR2: + case DSP563XX_REG_IDX_AAR3: err = dsp563xx_reg_read_high_io(target, arch_info->instr_mask, &data); if (err == ERROR_OK) { @@ -655,29 +772,29 @@ static int dsp563xx_write_register(struct target *target, int num, int force) switch (arch_info->num) { - case REG_NUM_SSH: + case DSP563XX_REG_IDX_SSH: err = dsp563xx_reg_ssh_write(target); break; - case REG_NUM_PC: + case DSP563XX_REG_IDX_PC: /* pc is updated on resume, no need to write it here */ break; - case REG_NUM_IPRC: - case REG_NUM_IPRP: - case REG_NUM_BCR: - case REG_NUM_DCR: - case REG_NUM_AAR0: - case REG_NUM_AAR1: - case REG_NUM_AAR2: - case REG_NUM_AAR3: + case DSP563XX_REG_IDX_IPRC: + case DSP563XX_REG_IDX_IPRP: + case DSP563XX_REG_IDX_BCR: + case DSP563XX_REG_IDX_DCR: + case DSP563XX_REG_IDX_AAR0: + case DSP563XX_REG_IDX_AAR1: + case DSP563XX_REG_IDX_AAR2: + case DSP563XX_REG_IDX_AAR3: err = dsp563xx_reg_write_high_io(target, arch_info->instr_mask, dsp563xx->core_regs[num]); break; default: err = dsp563xx_reg_write(target, arch_info->instr_mask, dsp563xx->core_regs[num]); - if ((err == ERROR_OK) && (arch_info->num == REG_NUM_SP)) + if ((err == ERROR_OK) && (arch_info->num == DSP563XX_REG_IDX_SP)) { - dsp563xx->core_cache->reg_list[REG_NUM_SSH].valid = 0; - dsp563xx->core_cache->reg_list[REG_NUM_SSL].valid = 0; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0; } break; @@ -713,48 +830,76 @@ static int dsp563xx_restore_context(struct target *target) return err; } -static const struct reg_arch_type dsp563xx_reg_type = { - .get = dsp563xx_get_core_reg, - .set = dsp563xx_set_core_reg, -}; - -static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target) +static void dsp563xx_invalidate_x_context(struct target *target, uint32_t addr_start, uint32_t addr_end ) { - /* get pointers to arch-specific information */ + int i; + struct dsp563xx_core_reg *arch_info; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - struct reg_cache *cache = malloc(sizeof(struct reg_cache)); - struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS); - struct dsp563xx_core_reg *arch_info = malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS); - int i; + if ( addr_start > ASM_REG_W_IPRC ) + return; + if ( addr_start < ASM_REG_W_AAR3 ) + return; + + for (i = DSP563XX_REG_IDX_IPRC; i < DSP563XX_NUMCOREREGS; i++) + { + arch_info = dsp563xx->core_cache->reg_list[i].arch_info; + + if ( (arch_info->instr_mask >= addr_start) && + (arch_info->instr_mask <= addr_end)) + { + dsp563xx->core_cache->reg_list[i].valid = 0; + dsp563xx->core_cache->reg_list[i].dirty = 0; + } + } +} + +static int dsp563xx_target_create(struct target *target, Jim_Interp * interp) +{ + struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common)); + + if (!dsp563xx) + return ERROR_INVALID_ARGUMENTS; + + dsp563xx->jtag_info.tap = target->tap; + target->arch_info = dsp563xx; + dsp563xx->read_core_reg = dsp563xx_read_core_reg; + dsp563xx->write_core_reg = dsp563xx_write_core_reg; + + return ERROR_OK; +} +static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target) +{ LOG_DEBUG("%s", __FUNCTION__); - /* Build the process context cache */ - cache->name = "dsp563xx registers"; - cache->next = NULL; - cache->reg_list = reg_list; - cache->num_regs = DSP563XX_NUMCOREREGS; - (*cache_p) = cache; - dsp563xx->core_cache = cache; + dsp563xx_build_reg_cache(target); - for (i = 0; i < DSP563XX_NUMCOREREGS; i++) + return ERROR_OK; +} + +static int dsp563xx_examine(struct target *target) +{ + uint32_t chip; + + if (target->tap->hasidcode == false) { - arch_info[i].num = dsp563xx_regs[i].id; - arch_info[i].name = dsp563xx_regs[i].name; - arch_info[i].size = dsp563xx_regs[i].bits; - arch_info[i].eame = dsp563xx_regs[i].eame; - arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask; - arch_info[i].target = target; - arch_info[i].dsp563xx_common = dsp563xx; - reg_list[i].name = dsp563xx_regs[i].name; - reg_list[i].size = dsp563xx_regs[i].bits; - reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].type = &dsp563xx_reg_type; - reg_list[i].arch_info = &arch_info[i]; + LOG_ERROR("no IDCODE present on device"); + + return ERROR_INVALID_ARGUMENTS; + } + + if (!target_was_examined(target)) + { + target_set_examined(target); + + /* examine core and chip derivate number */ + chip = (target->tap->idcode>>12)&0x3ff; + /* core number 0 means DSP563XX */ + if ( ((chip>>5)&0x1f) == 0 ) + chip += 300; + + LOG_INFO("DSP56%03d device found",chip); } return ERROR_OK; @@ -771,7 +916,7 @@ static int dsp563xx_arch_state(struct target *target) static int dsp563xx_debug_once_init(struct target *target) { - return dsp563xx_once_read_register(target->tap, once_regs, DSP563XX_NUMONCEREGS); + return dsp563xx_once_read_register(target->tap, 1, once_regs, DSP563XX_NUMONCEREGS); } static int dsp563xx_debug_init(struct target *target) @@ -784,63 +929,63 @@ static int dsp563xx_debug_init(struct target *target) if ((err = dsp563xx_debug_once_init(target)) != ERROR_OK) return err; - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_SR].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info; /* check 24bit mode */ - if ((err = dsp563xx_read_register(target, REG_NUM_SR, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SR, 0)) != ERROR_OK) return err; - sr = dsp563xx->core_regs[REG_NUM_SR]; + sr = dsp563xx->core_regs[DSP563XX_REG_IDX_SR]; if (sr & (DSP563XX_SR_SA | DSP563XX_SR_SC)) { sr &= ~(DSP563XX_SR_SA | DSP563XX_SR_SC); - if ((err = dsp563xx_once_execute_dw_ir(target->tap, arch_info->instr_mask, sr)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr)) != ERROR_OK) return err; - dsp563xx->core_cache->reg_list[REG_NUM_SR].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1; } - if ((err = dsp563xx_read_register(target, REG_NUM_N0, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0)) != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, REG_NUM_N1, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N1, 0)) != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, REG_NUM_M0, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M0, 0)) != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, REG_NUM_M1, 0)) != ERROR_OK) + if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M1, 0)) != ERROR_OK) return err; - if (dsp563xx->core_regs[REG_NUM_N0] != 0x000000) + if (dsp563xx->core_regs[DSP563XX_REG_IDX_N0] != 0x000000) { - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_N0].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info; if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000)) != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[REG_NUM_N0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1; - if (dsp563xx->core_regs[REG_NUM_N1] != 0x000000) + if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) { - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_N1].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info; if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000)) != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[REG_NUM_N1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1; - if (dsp563xx->core_regs[REG_NUM_M0] != 0xffffff) + if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) { - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_M0].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info; if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff)) != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[REG_NUM_M0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1; - if (dsp563xx->core_regs[REG_NUM_M1] != 0xffffff) + if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) { - arch_info = dsp563xx->core_cache->reg_list[REG_NUM_M1].arch_info; + arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info; if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff)) != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[REG_NUM_M1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1; if ((err = dsp563xx_save_context(target)) != ERROR_OK) return err; @@ -856,7 +1001,8 @@ static int dsp563xx_jtag_debug_request(struct target *target) static int dsp563xx_poll(struct target *target) { int err; - uint32_t once_status; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + uint32_t once_status=0; int state; state = dsp563xx_once_target_status(target->tap); @@ -868,7 +1014,7 @@ static int dsp563xx_poll(struct target *target) return ERROR_TARGET_FAILURE; } - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) return err; if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) @@ -876,10 +1022,22 @@ static int dsp563xx_poll(struct target *target) if (target->state != TARGET_HALTED) { target->state = TARGET_HALTED; + if ((err = dsp563xx_debug_init(target)) != ERROR_OK) return err; - LOG_DEBUG("target->state: %s", target_state_name(target)); + if ( once_status & (DSP563XX_ONCE_OSCR_MBO|DSP563XX_ONCE_OSCR_SWO) ) + { + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + } + else + { + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } + + LOG_DEBUG("target->state: %s (%x)", target_state_name(target),once_status); + + LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC] ); } } @@ -889,7 +1047,8 @@ static int dsp563xx_poll(struct target *target) static int dsp563xx_halt(struct target *target) { int err; - struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + LOG_DEBUG("%s", __FUNCTION__); if (target->state == TARGET_HALTED) { @@ -905,13 +1064,7 @@ static int dsp563xx_halt(struct target *target) if ((err = dsp563xx_jtag_debug_request(target)) != ERROR_OK) return err; - /* store pipeline register */ - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR, &dsp563xx->pipeline_context.once_opilr)) != ERROR_OK) - return err; - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR, &dsp563xx->pipeline_context.once_opdbr)) != ERROR_OK) - return err; - - LOG_DEBUG("%s", __FUNCTION__); + target->debug_reason = DBG_REASON_DBGRQ; return ERROR_OK; } @@ -921,7 +1074,20 @@ static int dsp563xx_resume(struct target *target, int current, uint32_t address, int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - LOG_DEBUG("%s", __FUNCTION__); + /* check if pc was changed and resume want to execute the next address + * if pc was changed from gdb or other interface we will + * jump to this address and don't execute the next address + * this will not affect the resume command with an address argument + * because current is set to zero then + */ + if ( current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty ) + { + dsp563xx_write_core_reg(target,DSP563XX_REG_IDX_PC); + address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; + current = 0; + } + + LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address); if ((err = dsp563xx_restore_context(target)) != ERROR_OK) return err; @@ -930,24 +1096,26 @@ static int dsp563xx_resume(struct target *target, int current, uint32_t address, if (current) { /* restore pipeline registers and go */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR, dsp563xx->pipeline_context.once_opilr)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, once_regs[ONCE_REG_IDX_OPILR].reg)) != ERROR_OK) return err; if ((err = - dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, - dsp563xx->pipeline_context.once_opdbr)) != ERROR_OK) + dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, + once_regs[ONCE_REG_IDX_OPDBR].reg)) != ERROR_OK) return err; } else { /* set to go register and jump */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) return err; } target->state = TARGET_RUNNING; + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); + return ERROR_OK; } @@ -964,6 +1132,19 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address return ERROR_OK; } + /* check if pc was changed and step want to execute the next address + * if pc was changed from gdb or other interface we will + * jump to this address and don't execute the next address + * this will not affect the step command with an address argument + * because current is set to zero then + */ + if ( current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty ) + { + dsp563xx_write_core_reg(target,DSP563XX_REG_IDX_PC); + address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; + current = 0; + } + LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address); if ((err = dsp563xx_jtag_debug_request(target)) != ERROR_OK) @@ -972,10 +1153,10 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address return err; /* reset trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) return err; /* enable trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME)) != ERROR_OK) return err; cnt = steps; @@ -985,53 +1166,47 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address cnt++; /* load step counter with N-1 */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OTC, cnt)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, cnt)) != ERROR_OK) return err; if (current) { /* restore pipeline registers and go */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR, dsp563xx->pipeline_context.once_opilr)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, once_regs[ONCE_REG_IDX_OPILR].reg)) != ERROR_OK) return err; if ((err = - dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, - dsp563xx->pipeline_context.once_opdbr)) != ERROR_OK) + dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, + once_regs[ONCE_REG_IDX_OPDBR].reg)) != ERROR_OK) return err; } else { /* set to go register and jump */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) return err; } while (1) { - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) return err; if (once_status & DSP563XX_ONCE_OSCR_TO) { - /* store pipeline register */ - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR, &dsp563xx->pipeline_context.once_opilr)) != ERROR_OK) + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in)) != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR, &dsp563xx->pipeline_context.once_opdbr)) != ERROR_OK) + LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff); + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in)) != ERROR_OK) return err; - - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR, &dr_in)) != ERROR_OK) - return err; - LOG_DEBUG("fetch: %08X", (unsigned) dr_in); - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR, &dr_in)) != ERROR_OK) - return err; - LOG_DEBUG("decode: %08X", (unsigned) dr_in); - if ((err = dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &dr_in)) != ERROR_OK) + LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff); + if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in)) != ERROR_OK) return err; - LOG_DEBUG("execute: %08X", (unsigned) dr_in); + LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff); /* reset trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) + if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) return err; register_cache_invalidate(dsp563xx->core_cache); @@ -1047,7 +1222,26 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address static int dsp563xx_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - return dsp563xx_step_ex(target, current, address, handle_breakpoints, 0); + int err; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if ( (err=dsp563xx_step_ex(target, current, address, handle_breakpoints, 0)) != ERROR_OK ) + { + return err; + } + + target->debug_reason = DBG_REASON_SINGLESTEP; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + + LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC] ); + + return err; } static int dsp563xx_assert_reset(struct target *target) @@ -1107,8 +1301,10 @@ static int dsp563xx_deassert_reset(struct target *target) return err; } } - -// target->state = TARGET_RUNNING; + else + { + target->state = TARGET_RUNNING; + } LOG_DEBUG("%s", __FUNCTION__); return ERROR_OK; @@ -1120,15 +1316,150 @@ static int dsp563xx_soft_reset_halt(struct target *target) return ERROR_OK; } -static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) +{ + int i; + int retval = ERROR_OK; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + for (i = 0; i < num_mem_params; i++) + { + if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) + { + return retval; + } + } + + for (i = 0; i < num_reg_params; i++) + { + struct reg *reg = register_get_by_name(dsp563xx->core_cache, reg_params[i].reg_name, 0); + + if (!reg) + { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + continue; + } + + if (reg->size != reg_params[i].size) + { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + continue; + } + + if ((retval = dsp563xx_set_core_reg(reg, reg_params[i].value)) != ERROR_OK) + { + return retval; + } + } + + /* exec */ + if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) + { + return retval; + } + + if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) + { + return retval; + } + + for (i = 0; i < num_mem_params; i++) + { + if (mem_params[i].direction != PARAM_OUT) + retval = target_read_buffer(target, + mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) + return retval; + } + + for (i = 0; i < num_reg_params; i++) + { + if (reg_params[i].direction != PARAM_OUT) + { + + struct reg *reg = register_get_by_name(dsp563xx->core_cache, reg_params[i].reg_name, 0); + if (!reg) + { + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + continue; + } + + if (reg->size != reg_params[i].size) + { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + continue; + } + + buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); + } + } + + return ERROR_OK; +} + +/* global command context from openocd.c */ +extern struct command_context *global_cmd_ctx; + +static int dsp563xx_get_default_memory(void) +{ + Jim_Interp *interp; + Jim_Obj * memspace; + char * c; + + if ( !global_cmd_ctx ) + return MEM_P; + + interp = global_cmd_ctx->interp; + + if ( !interp ) + return MEM_P; + + memspace = Jim_GetGlobalVariableStr(interp,"memspace", JIM_NONE); + + if ( !memspace ) + return MEM_P; + + c = (char*)Jim_GetString(memspace,NULL); + + if ( !c ) + return MEM_P; + + switch(c[0]) + { + case '1': + return MEM_X; + case '2': + return MEM_Y; + case '3': + return MEM_L; + default: + break; + } + + return MEM_P; +} + +static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); uint32_t i, x; - uint32_t data, move_cmd; + uint32_t data, move_cmd = 0; uint8_t *b; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); + LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", mem_type,address, size, count); if (target->state != TARGET_HALTED) { @@ -1136,12 +1467,6 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad return ERROR_TARGET_NOT_HALTED; } - /* we only support 4 byte aligned data */ - if ( size != 4 ) - { - return ERROR_INVALID_ARGUMENTS; - } - switch (mem_type) { case MEM_X: @@ -1159,30 +1484,30 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad } /* we use r0 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R0].valid) - dsp563xx->read_core_reg(target, REG_NUM_R0); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0); /* we use r1 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R1].valid) - dsp563xx->read_core_reg(target, REG_NUM_R1); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1); /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; /* r1 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1; x = count; b = buffer; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0x60F400, address)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address)) != ERROR_OK) return err; for (i = 0; i < x; i++) { - if ((err = dsp563xx_once_execute_sw_ir_nq(target->tap, move_cmd)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd)) != ERROR_OK) return err; - if ((err = dsp563xx_once_execute_sw_ir_nq(target->tap, 0x08D13C)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, 0x08D13C)) != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_read_nq(target->tap, DSP563XX_ONCE_OGDBR, (uint32_t*)b)) != ERROR_OK) + if ((err = dsp563xx_once_reg_read(target->tap, 0, DSP563XX_ONCE_OGDBR, (uint32_t*)(void *)b)) != ERROR_OK) return err; b += 4; } @@ -1198,7 +1523,7 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad for (i = 0; i < x; i++) { - data = *((uint32_t*)b) & 0x00FFFFFF; + data = buf_get_u32(b, 0, 32) & 0x00FFFFFF; // LOG_DEBUG("R: %08X", *((uint32_t*)b)); target_buffer_set_u32(target, b, data); b += 4; @@ -1207,20 +1532,100 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad return ERROR_OK; } -static int dsp563xx_read_memory_p(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) { - return dsp563xx_read_memory(target, MEM_P, address, size, count, buffer); + int err; + uint32_t i,i1; + uint8_t *buffer_y,*buffer_x; + + /* if size equals zero we are called from target read memory + * and have to handle the parameter here */ + if ( (size == 0) && (count != 0) ) + { + size = count % 4; + + if ( size ) + { + LOG_DEBUG("size is not aligned to 4 byte"); + } + + count = (count - size) / 4; + size = 4; + } + + /* we only support 4 byte aligned data */ + if ( (size != 4) || (!count) ) + { + return ERROR_INVALID_ARGUMENTS; + } + + if ( mem_type != MEM_L ) + { + return dsp563xx_read_memory_core(target,mem_type,address,size,count,buffer); + } + + if ( !(buffer_y = malloc(size*count)) ) + { + return ERROR_INVALID_ARGUMENTS; + } + + if ( !(buffer_x = malloc(size*count)) ) + { + free(buffer_y); + return ERROR_INVALID_ARGUMENTS; + } + + err = dsp563xx_read_memory_core(target,MEM_Y,address,size,count/2,buffer_y); + + if ( err != ERROR_OK ) + { + free(buffer_y); + free(buffer_x); + return err; + } + + err = dsp563xx_read_memory_core(target,MEM_X,address,size,count/2,buffer_x); + + if ( err != ERROR_OK ) + { + free(buffer_y); + free(buffer_x); + return err; + } + + for(i=0,i1=0;istate != TARGET_HALTED) { @@ -1228,15 +1633,11 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a return ERROR_TARGET_NOT_HALTED; } - /* we only support 4 byte aligned data */ - if ( size != 4 ) - { - return ERROR_INVALID_ARGUMENTS; - } - switch (mem_type) { case MEM_X: + /* invalidate affected x registers */ + dsp563xx_invalidate_x_context(target,address,address+count-1); move_cmd = 0x615800; break; case MEM_Y: @@ -1250,21 +1651,21 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a } /* we use r0 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R0].valid) - dsp563xx->read_core_reg(target, REG_NUM_R0); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0); /* we use r1 to store temporary data */ - if (!dsp563xx->core_cache->reg_list[REG_NUM_R1].valid) - dsp563xx->read_core_reg(target, REG_NUM_R1); + if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid) + dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1); /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; /* r1 is no longer valid on target */ - dsp563xx->core_cache->reg_list[REG_NUM_R1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1; x = count; b = buffer; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0x60F400, address)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address)) != ERROR_OK) return err; for (i = 0; i < x; i++) @@ -1275,9 +1676,9 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a data &= 0x00ffffff; - if ((err = dsp563xx_once_execute_dw_ir_nq(target->tap, 0x61F400, data)) != ERROR_OK) + if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x61F400, data)) != ERROR_OK) return err; - if ((err = dsp563xx_once_execute_sw_ir_nq(target->tap, move_cmd)) != ERROR_OK) + if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd)) != ERROR_OK) return err; b += 4; } @@ -1291,14 +1692,112 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a return ERROR_OK; } -static int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer) { - return dsp563xx_write_memory(target, MEM_P, address, size, count, buffer); + int err; + uint32_t i,i1; + uint8_t *buffer_y,*buffer_x; + + /* if size equals zero we are called from target write memory + * and have to handle the parameter here */ + if ( (size == 0) && (count != 0) ) + { + size = count % 4; + + if ( size ) + { + LOG_DEBUG("size is not aligned to 4 byte"); + } + + count = (count - size) / 4; + size = 4; + } + + /* we only support 4 byte aligned data */ + if ( (size != 4) || (!count) ) + { + return ERROR_INVALID_ARGUMENTS; + } + + if ( mem_type != MEM_L ) + { + return dsp563xx_write_memory_core(target,mem_type,address,size,count,buffer); + } + + if ( !(buffer_y = malloc(size*count)) ) + { + return ERROR_INVALID_ARGUMENTS; + } + + if ( !(buffer_x = malloc(size*count)) ) + { + free(buffer_y); + return ERROR_INVALID_ARGUMENTS; + } + + for(i=0,i1=0;i