X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_swjdp.c;h=02cbe0040e805ad3d6ead6ad77b1d196ed754c7a;hp=dc50fea1c4a91ff18b64bb8c5f1d5338db447ee9;hb=503bb08f9993c59a4b3206600555a42fd18459b6;hpb=3aa95240ece4c99fdb1b5d33e4153d96d3f278ee diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index dc50fea1c4..02cbe0040e 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -2,6 +2,9 @@ * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -21,8 +24,8 @@ * * * CoreSight (Light?) SerialWireJtagDebugPort * * * - * CoreSight™ DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3™ TRM, ARM DDI 0337C * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * + * Cortex-M3(tm) TRM, ARM DDI 0337C * * * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -35,6 +38,7 @@ #include "cortex_swjdp.h" #include "jtag.h" #include "log.h" +#include "time_support.h" #include /* @@ -63,7 +67,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu jtag_add_end_state(TAP_RTI); arm_jtag_set_instr(jtag_info, instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; @@ -74,7 +78,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = outvalue; fields[1].out_mask = NULL; @@ -99,7 +103,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out jtag_add_end_state(TAP_RTI); arm_jtag_set_instr(jtag_info, instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; @@ -110,7 +114,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; buf_set_u32(out_value_buf, 0, 32, outvalue); fields[1].out_value = out_value_buf; @@ -171,23 +175,38 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u int swjdp_transaction_endcheck(swjdp_common_t *swjdp) { - int waitcount = 0; + int retval; u32 ctrlstat; + keep_alive(); + + /* Danger!!!! BROKEN!!!! */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? + R956 introduced the check on return value here and now Michael Schwingen reports + that this code no longer works.... + + https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html + */ + if ((retval=jtag_execute_queue())!=ERROR_OK) + { + LOG_ERROR("BUG: Why does this fail the first time????"); + } + /* Why??? second time it works??? */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; swjdp->ack = swjdp->ack & 0x7; + long long then=timeval_ms(); while (swjdp->ack != 2) { if (swjdp->ack == 1) { - waitcount++; - if (waitcount > 100) + if ((timeval_ms()-then) > 1000) { - LOG_WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction"); + LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction"); return ERROR_JTAG_DEVICE_ERROR; } } @@ -198,7 +217,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) } scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; swjdp->ack = swjdp->ack & 0x7; } @@ -224,7 +244,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Clear Sticky Error Bits */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; LOG_DEBUG("swjdp: status 0x%x", ctrlstat); @@ -235,7 +256,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar); LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar); } - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -966,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - usleep(10000); + alive_sleep(10); } while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) @@ -975,7 +997,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - usleep(10000); + alive_sleep(10); } swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);