X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=e034189a07978a6addbc1845f1e99c2da9fb66a1;hp=255fcd03453c4cf770cf1831b515621062c04ac2;hb=ef1cfb23947bd32798077c6abb5c25a049460ae9;hpb=18293612537125c8864d4627c7c4b2b4ba7cc882 diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 255fcd0345..e034189a07 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -45,9 +45,9 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx); /* forward declarations */ void cortex_m3_enable_breakpoints(struct target_s *target); void cortex_m3_enable_watchpoints(struct target_s *target); -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(); +int cortex_m3_quit(void); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); @@ -91,7 +91,7 @@ target_type_t cortexm3_target = .remove_watchpoint = cortex_m3_remove_watchpoint, .register_commands = cortex_m3_register_commands, - .target_command = cortex_m3_target_command, + .target_create = cortex_m3_target_create, .init_target = cortex_m3_init_target, .examine = cortex_m3_examine, .quit = cortex_m3_quit @@ -359,8 +359,10 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_examine_exception_reason(target); } - LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \ - *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); + LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", + armv7m_mode_strings[armv7m->core_mode], + *(u32*)(armv7m->core_cache->reg_list[15].value), + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (armv7m->post_debug_entry) armv7m->post_debug_entry(target); @@ -436,7 +438,7 @@ int cortex_m3_poll(target_t *target) #if 0 /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); + LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name( nvp_target_state, target->state )->name ); #endif return ERROR_OK; @@ -449,7 +451,8 @@ int cortex_m3_halt(target_t *target) cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); if (target->state == TARGET_HALTED) { @@ -523,7 +526,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target) LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout); } timeout++; - usleep(1000); + alive_sleep(1); } return ERROR_OK; @@ -676,7 +679,8 @@ int cortex_m3_assert_reset(target_t *target) swjdp_common_t *swjdp = &cortex_m3->swjdp_info; int assert_srst = 1; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -774,7 +778,8 @@ int cortex_m3_assert_reset(target_t *target) int cortex_m3_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -1374,7 +1379,7 @@ int cortex_m3_examine(struct target_s *target) return ERROR_OK; } -int cortex_m3_quit() +int cortex_m3_quit(void) { return ERROR_OK; @@ -1458,7 +1463,7 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant) +int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant) { armv7m_common_t *armv7m; armv7m = &cortex_m3->armv7m; @@ -1505,26 +1510,11 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in return ERROR_OK; } -/* target cortex_m3 */ -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t)); - memset(cortex_m3, 0, sizeof(*cortex_m3)); - - if (argc < 4) - { - LOG_ERROR("'target cortex_m3' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); + cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); - if (argc >= 5) - variant = args[4]; - - cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant); + cortex_m3_init_arch_info(target, cortex_m3, target->chain_position, target->variant); return ERROR_OK; } @@ -1537,3 +1527,11 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx) return retval; } + + +/* + * Local Variables: *** + * c-basic-offset: 4 *** + * tab-width: 4 *** + * End: *** + */