X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=d8a28796a25c066f53370165575014612c923bcb;hp=53ecd0a90d5309e89de466efed373f37a438308a;hb=8fb2baaa6b428bd50165f045749786c34857ab02;hpb=519896811600849b27f0803e08ee5f9152423f24 diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 53ecd0a90d..d8a28796a2 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -24,7 +24,7 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * * * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) * * * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -34,74 +34,38 @@ #include "cortex_m3.h" #include "target_request.h" #include "target_type.h" +#include "arm_disassembler.h" -/* cli handling */ -int cortex_m3_register_commands(struct command_context_s *cmd_ctx); -int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) + /* forward declarations */ -void cortex_m3_enable_breakpoints(struct target_s *target); -void cortex_m3_enable_watchpoints(struct target_s *target); -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(void); -int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); -int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t value); -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer); -int cortex_m3_examine(struct target_s *target); +static int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); +static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); +static void cortex_m3_enable_watchpoints(struct target_s *target); +static int cortex_m3_store_core_reg_u32(target_t *target, + enum armv7m_regtype type, uint32_t num, uint32_t value); #ifdef ARMV7_GDB_HACKS extern uint8_t armv7m_gdb_dummy_cpsr_value[]; extern reg_t armv7m_gdb_dummy_cpsr_reg; #endif -target_type_t cortexm3_target = +static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu) { - .name = "cortex_m3", - - .poll = cortex_m3_poll, - .arch_state = armv7m_arch_state, - - .target_request_data = cortex_m3_target_request_data, - - .halt = cortex_m3_halt, - .resume = cortex_m3_resume, - .step = cortex_m3_step, - - .assert_reset = cortex_m3_assert_reset, - .deassert_reset = cortex_m3_deassert_reset, - .soft_reset_halt = cortex_m3_soft_reset_halt, - - .get_gdb_reg_list = armv7m_get_gdb_reg_list, - - .read_memory = cortex_m3_read_memory, - .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, - .checksum_memory = armv7m_checksum_memory, - .blank_check_memory = armv7m_blank_check_memory, - - .run_algorithm = armv7m_run_algorithm, - - .add_breakpoint = cortex_m3_add_breakpoint, - .remove_breakpoint = cortex_m3_remove_breakpoint, - .add_watchpoint = cortex_m3_add_watchpoint, - .remove_watchpoint = cortex_m3_remove_watchpoint, - - .register_commands = cortex_m3_register_commands, - .target_create = cortex_m3_target_create, - .init_target = cortex_m3_init_target, - .examine = cortex_m3_examine, - .quit = cortex_m3_quit -}; + *has_mmu = false; + return ERROR_OK; +} -int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) +static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, + uint32_t *value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ + * we have to save/restore the DCB_DCRDR when used */ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); @@ -115,18 +79,24 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, i dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); retval = swjdp_transaction_endcheck(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } -int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum) +static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, + uint32_t value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ + * we have to save/restore the DCB_DCRDR when used */ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); @@ -140,13 +110,18 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, i dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); retval = swjdp_transaction_endcheck(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + return retval; } - -int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off) +static int cortex_m3_write_debug_halt_mask(target_t *target, + uint32_t mask_on, uint32_t mask_off) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -161,7 +136,7 @@ int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); } -int cortex_m3_clear_halt(target_t *target) +static int cortex_m3_clear_halt(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -173,14 +148,14 @@ int cortex_m3_clear_halt(target_t *target) /* Read Debug Fault Status Register */ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ + /* Clear Debug Fault Status */ mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr); return ERROR_OK; } -int cortex_m3_single_step_core(target_t *target) +static int cortex_m3_single_step_core(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -204,39 +179,7 @@ int cortex_m3_single_step_core(target_t *target) return ERROR_OK; } -int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t savedram; - int retvalue; - - mem_ap_read_u32(swjdp, 0x20000000, &savedram); - mem_ap_write_u32(swjdp, 0x20000000, opcode); - cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram); - - return retvalue; -} - -#if 0 -/* Enable interrupts */ -int cortex_m3_cpsie(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2); -} - -/* Disable interrupts */ -int cortex_m3_cpsid(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2); -} -#endif - -int cortex_m3_endreset_event(target_t *target) +static int cortex_m3_endreset_event(target_t *target) { int i; uint32_t dcb_demcr; @@ -280,9 +223,12 @@ int cortex_m3_endreset_event(target_t *target) /* Restore DWT registers */ for (i = 0; i < cortex_m3->dwt_num_comp; i++) { - target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, + dwt_list[i].comp); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 4, + dwt_list[i].mask); + target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, + dwt_list[i].function); } swjdp_transaction_endcheck(swjdp); @@ -294,7 +240,7 @@ int cortex_m3_endreset_event(target_t *target) return ERROR_OK; } -int cortex_m3_examine_debug_reason(target_t *target) +static int cortex_m3_examine_debug_reason(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -306,8 +252,6 @@ int cortex_m3_examine_debug_reason(target_t *target) if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - /* INCOMPLETE */ - if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; @@ -316,12 +260,16 @@ int cortex_m3_examine_debug_reason(target_t *target) } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; + else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) + target->debug_reason = DBG_REASON_BREAKPOINT; + else /* EXTERNAL, HALTED */ + target->debug_reason = DBG_REASON_UNDEFINED; } return ERROR_OK; } -int cortex_m3_examine_exception_reason(target_t *target) +static int cortex_m3_examine_exception_reason(target_t *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; @@ -371,7 +319,7 @@ int cortex_m3_examine_exception_reason(target_t *target) return ERROR_OK; } -int cortex_m3_debug_entry(target_t *target) +static int cortex_m3_debug_entry(target_t *target) { int i; uint32_t xPSR; @@ -383,8 +331,6 @@ int cortex_m3_debug_entry(target_t *target) swjdp_common_t *swjdp = &armv7m->swjdp_info; LOG_DEBUG(" "); - if (armv7m->pre_debug_entry) - armv7m->pre_debug_entry(target); cortex_m3_clear_halt(target); mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -394,7 +340,9 @@ int cortex_m3_debug_entry(target_t *target) /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7M_PRIMASK; i++) + int num_regs = armv7m->core_cache->num_regs; + + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -417,13 +365,6 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } - /* Now we can load SP core registers */ - for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) - { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); - } - /* Are we in an exception handler */ if (xPSR & 0x1FF) { @@ -452,7 +393,7 @@ int cortex_m3_debug_entry(target_t *target) return ERROR_OK; } -int cortex_m3_poll(target_t *target) +static int cortex_m3_poll(target_t *target) { int retval; enum target_state prev_target_state = target->state; @@ -529,7 +470,7 @@ int cortex_m3_poll(target_t *target) return ERROR_OK; } -int cortex_m3_halt(target_t *target) +static int cortex_m3_halt(target_t *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -571,7 +512,7 @@ int cortex_m3_halt(target_t *target) return ERROR_OK; } -int cortex_m3_soft_reset_halt(struct target_s *target) +static int cortex_m3_soft_reset_halt(struct target_s *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -612,7 +553,21 @@ int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void cortex_m3_enable_breakpoints(struct target_s *target) +{ + breakpoint_t *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (breakpoint->set == 0) + cortex_m3_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int cortex_m3_resume(struct target_s *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -667,9 +622,9 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int /* Single step past breakpoint at current address */ if ((breakpoint = breakpoint_find(target, resume_pc))) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", breakpoint->address, - breakpoint->unique_id ); + breakpoint->unique_id); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); cortex_m3_set_breakpoint(target, breakpoint); @@ -700,7 +655,8 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int } /* int irqstepcount = 0; */ -int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int cortex_m3_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -748,7 +704,7 @@ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int h return ERROR_OK; } -int cortex_m3_assert_reset(target_t *target) +static int cortex_m3_assert_reset(target_t *target) { armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -759,11 +715,14 @@ int cortex_m3_assert_reset(target_t *target) target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); + + /* + * We can reset Cortex-M3 targets using just the NVIC without + * requiring SRST, getting a SoC reset (or a core-only reset) + * instead of a system reset. + */ if (!(jtag_reset_config & RESET_HAS_SRST)) - { - LOG_ERROR("Can't assert SRST"); - return ERROR_FAIL; - } + assert_srst = 0; /* Enable debug requests */ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -793,15 +752,21 @@ int cortex_m3_assert_reset(target_t *target) mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); } - /* following hack is to handle luminary reset - * when srst is asserted the luminary device seesm to also clear the debug registers - * which does not match the armv7 debug TRM */ - + /* + * When nRST is asserted on most Stellaris devices, it clears some of + * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + * and OpenOCD depends on those TRMs. So we won't use SRST on those + * chips. (Only power-on reset should affect debug state, beyond a + * few specified bits; not the chip's nRST input, wired to SRST.) + * + * REVISIT current errata specs don't seem to cover this issue. + * Do we have more details than this email? + * https://lists.berlios.de/pipermail + * /openocd-development/2008-August/003065.html + */ if (strcmp(target->variant, "lm3s") == 0) { - /* get revision of lm3s target, only early silicon has this issue - * Fury Rev B, DustDevil Rev B, Tempest all ok */ - + /* Check for silicon revisions with the issue. */ uint32_t did0; if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) @@ -815,10 +780,16 @@ int cortex_m3_assert_reset(target_t *target) case 1: case 3: - /* only Fury/DustDevil rev A suffer reset problems */ + /* Fury and DustDevil rev A have + * this nRST problem. It should + * be fixed in rev B silicon. + */ if (((did0 >> 8) & 0xff) == 0) assert_srst = 0; break; + case 4: + /* Tempest should be fine. */ + break; } } } @@ -837,13 +808,20 @@ int cortex_m3_assert_reset(target_t *target) } else { - /* this causes the luminary device to reset using the watchdog */ - mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); - LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + /* Use a standard Cortex-M3 software reset mechanism. + * SYSRESETREQ will reset SoC peripherals outside the + * core, like watchdog timers, if the SoC wires it up + * correctly. Else VECRESET can reset just the core. + */ + mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | AIRCR_SYSRESETREQ); + LOG_DEBUG("Using Cortex-M3 SYSRESETREQ"); { - /* I do not know why this is necessary, but it fixes strange effects - * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + /* I do not know why this is necessary, but it + * fixes strange effects (step/resume cause NMI + * after reset) on LM3S6918 -- Michael Schwingen + */ uint32_t tmp; mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); } @@ -864,7 +842,7 @@ int cortex_m3_assert_reset(target_t *target) return ERROR_OK; } -int cortex_m3_deassert_reset(target_t *target) +static int cortex_m3_deassert_reset(target_t *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -875,20 +853,8 @@ int cortex_m3_deassert_reset(target_t *target) return ERROR_OK; } -void cortex_m3_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - cortex_m3_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; int fp_num = 0; @@ -948,7 +914,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) breakpoint->set = 0x11; /* Any nice value but 0 */ } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -958,7 +924,8 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; /* get pointers to arch-specific information */ @@ -972,7 +939,7 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -1014,7 +981,8 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } -int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -1064,12 +1032,14 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1092,7 +1062,8 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin return ERROR_OK; } -int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int dwt_num = 0; uint32_t mask, temp; @@ -1100,93 +1071,112 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; - if (watchpoint->set) - { - LOG_WARNING("watchpoint (%d) already set", watchpoint->unique_id ); - return ERROR_OK; + /* watchpoint params were validated earlier */ + mask = 0; + temp = watchpoint->length; + while (temp) { + temp >>= 1; + mask++; } + mask--; - if (watchpoint->mask == 0xffffffffu) - { - while (comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp)) - dwt_num++; - if (dwt_num >= cortex_m3->dwt_num_comp) - { - LOG_DEBUG("ERROR Can not find free DWT Comparator"); - LOG_WARNING("ERROR Can not find free DWT Comparator"); - return -1; - } - watchpoint->set = dwt_num + 1; - mask = 0; - temp = watchpoint->length; - while (temp > 1) - { - temp = temp / 2; - mask++; - } - comparator_list[dwt_num].used = 1; - comparator_list[dwt_num].comp = watchpoint->address; - comparator_list[dwt_num].mask = mask; - comparator_list[dwt_num].function = watchpoint->rw + 5; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); - LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); - } - else + /* REVISIT Don't fully trust these "not used" records ... users + * may set up breakpoints by hand, e.g. dual-address data value + * watchpoint using comparator #1; comparator #0 matching cycle + * count; send data trace info through ITM and TPIU; etc + */ + cortex_m3_dwt_comparator_t *comparator; + + for (comparator = cortex_m3->dwt_comparator_list; + comparator->used && dwt_num < cortex_m3->dwt_num_comp; + comparator++, dwt_num++) + continue; + if (dwt_num >= cortex_m3->dwt_num_comp) { - /* Move this test to add_watchpoint */ - LOG_WARNING("Cannot watch data values (id: %d)", - watchpoint->unique_id ); - return ERROR_OK; + LOG_ERROR("Can not find free DWT Comparator"); + return ERROR_FAIL; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address, watchpoint->set ); + comparator->used = 1; + watchpoint->set = dwt_num + 1; + + comparator->comp = watchpoint->address; + target_write_u32(target, comparator->dwt_comparator_address + 0, + comparator->comp); + + comparator->mask = mask; + target_write_u32(target, comparator->dwt_comparator_address + 4, + comparator->mask); + + switch (watchpoint->rw) { + case WPT_READ: + comparator->function = 5; + break; + case WPT_WRITE: + comparator->function = 6; + break; + case WPT_ACCESS: + comparator->function = 7; + break; + } + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + + LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", + watchpoint->unique_id, dwt_num, + (unsigned) comparator->comp, + (unsigned) comparator->mask, + (unsigned) comparator->function); return ERROR_OK; - } -int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; + cortex_m3_dwt_comparator_t *comparator; int dwt_num; if (!watchpoint->set) { - LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id ); + LOG_WARNING("watchpoint (wpid: %d) not set", + watchpoint->unique_id); return ERROR_OK; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address,watchpoint->set ); - dwt_num = watchpoint->set - 1; + LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", + watchpoint->unique_id, dwt_num, + (unsigned) watchpoint->address); + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } - comparator_list[dwt_num].used = 0; - comparator_list[dwt_num].function = 0; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); + + comparator = cortex_m3->dwt_comparator_list + dwt_num; + comparator->used = 0; + comparator->function = 0; + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); watchpoint->set = 0; return ERROR_OK; } -int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1195,11 +1185,41 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (cortex_m3->dwt_comp_available < 1) { + LOG_DEBUG("no comparators?"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) - { + /* hardware doesn't support data value masking */ + if (watchpoint->mask != ~(uint32_t)0) { + LOG_DEBUG("watchpoint value masks not supported"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* hardware allows address masks of up to 32K */ + unsigned mask; + + for (mask = 0; mask < 16; mask++) { + if ((1 << mask) == watchpoint->length) + break; + } + if (mask == 16) { + LOG_DEBUG("unsupported watchpoint length"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + if (watchpoint->address & ((1 << mask) - 1)) { + LOG_DEBUG("watchpoint address is unaligned"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* Caller doesn't seem to be able to describe watching for data + * values of zero; that flags "no value". + * + * REVISIT This DWT may well be able to watch for specific data + * values. Requires comparator #1 to set DATAVMATCH and match + * the data, and another comparator (DATAVADDR0) matching addr. + */ + if (watchpoint->value) { + LOG_DEBUG("data value watchpoint not YET supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1209,12 +1229,14 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1232,7 +1254,7 @@ int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoin return ERROR_OK; } -void cortex_m3_enable_watchpoints(struct target_s *target) +static void cortex_m3_enable_watchpoints(struct target_s *target) { watchpoint_t *watchpoint = target->watchpoints; @@ -1245,15 +1267,20 @@ void cortex_m3_enable_watchpoints(struct target_s *target) } } -int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) +static int cortex_m3_load_core_reg_u32(struct target_s *target, + enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: /* read a normal core register */ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); @@ -1263,42 +1290,49 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* read other registers */ + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, value, 20); switch (num) { - case 19: - *value = buf_get_u32((uint8_t*)value, 0, 8); + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t*)value, 0, 1); break; - case 20: + case ARMV7M_BASEPRI: *value = buf_get_u32((uint8_t*)value, 8, 8); break; - case 21: - *value = buf_get_u32((uint8_t*)value, 16, 8); + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t*)value, 16, 1); break; - case 22: - *value = buf_get_u32((uint8_t*)value, 24, 8); + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t*)value, 24, 2); break; } LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } return ERROR_OK; } -int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value) +static int cortex_m3_store_core_reg_u32(struct target_s *target, + enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; uint32_t reg; @@ -1312,14 +1346,19 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty * in "thumb" mode, or an INVSTATE exception will occur. This is a * hack to deal with the fact that gdb will sometimes "forge" * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) */ - - if (num == 14) + * printing expressions containing function calls, it sets LR = 0.) + * Valid exception return codes have bit 0 set too. + */ + if (num == ARMV7M_R14) value |= 0x01; #endif - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { @@ -1328,45 +1367,51 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* write other registers */ - + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); switch (num) { - case 19: - buf_set_u32((uint8_t*)®, 0, 8, value); + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t*)®, 0, 1, value); break; - case 20: + case ARMV7M_BASEPRI: buf_set_u32((uint8_t*)®, 8, 8, value); break; - case 21: - buf_set_u32((uint8_t*)®, 16, 8, value); + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t*)®, 16, 1, value); break; - case 22: - buf_set_u32((uint8_t*)®, 24, 8, value); + case ARMV7M_CONTROL: + buf_set_u32((uint8_t*)®, 24, 2, value); break; } cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } return ERROR_OK; } -int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_read_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -1398,7 +1443,8 @@ int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t si return retval; } -int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_write_memory(struct target_s *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -1428,26 +1474,28 @@ int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t s return retval; } -int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, + uint32_t count, uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } -void cortex_m3_build_reg_cache(target_t *target) +static void cortex_m3_build_reg_cache(target_t *target) { armv7m_build_reg_cache(target); } -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int cortex_m3_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { cortex_m3_build_reg_cache(target); return ERROR_OK; } -int cortex_m3_examine(struct target_s *target) +static int cortex_m3_examine(struct target_s *target) { int retval; - uint32_t cpuid, fpcr, dwtcr, ictr; + uint32_t cpuid, fpcr, dwtcr; int i; /* get pointers to arch-specific information */ @@ -1463,21 +1511,15 @@ int cortex_m3_examine(struct target_s *target) target_set_examined(target); /* Read from Device Identification Registers */ - if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + retval = target_read_u32(target, CPUID, &cpuid); + if (retval != ERROR_OK) return retval; if (((cpuid >> 4) & 0xc3f) == 0xc23) LOG_DEBUG("CORTEX-M3 processor detected"); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]); - } + /* NOTE: FPB and DWT are both optional. */ /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); @@ -1498,23 +1540,24 @@ int cortex_m3_examine(struct target_s *target) target_read_u32(target, DWT_CTRL, &dwtcr); cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); + cortex_m3->dwt_comparator_list = calloc( + cortex_m3->dwt_num_comp, + sizeof(cortex_m3_dwt_comparator_t)); for (i = 0; i < cortex_m3->dwt_num_comp; i++) { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + cortex_m3->dwt_comparator_list[i] + .dwt_comparator_address = DWT_COMP0 + 0x10 * i; } + if (cortex_m3->dwt_num_comp) + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + dwtcr, cortex_m3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); } return ERROR_OK; } -int cortex_m3_quit(void) -{ - - return ERROR_OK; -} - -int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) { uint16_t dcrdr; @@ -1535,7 +1578,8 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) return ERROR_OK; } -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) +static int cortex_m3_target_request_data(target_t *target, + uint32_t size, uint8_t *buffer) { armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; @@ -1552,7 +1596,7 @@ int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buff return ERROR_OK; } -int cortex_m3_handle_target_request(void *priv) +static int cortex_m3_handle_target_request(void *priv) { target_t *target = priv; if (!target_was_examined(target)) @@ -1590,7 +1634,8 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) +static int cortex_m3_init_arch_info(target_t *target, + cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) { int retval; armv7m_common_t *armv7m; @@ -1617,7 +1662,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; - armv7m->pre_debug_entry = NULL; armv7m->post_debug_entry = NULL; armv7m->pre_restore_context = NULL; @@ -1637,7 +1681,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt return ERROR_OK; } -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); @@ -1646,20 +1690,121 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } -int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +/* + * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well + * as at least ARM-1156T2. The interesting thing about Cortex-M is + * that *only* Thumb2 disassembly matters. There are also some small + * additions to Thumb2 that are specific to ARMv7-M. + */ +static int +handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { - int retval; - command_t *cortex_m3_cmd; + int retval = ERROR_OK; + target_t *target = get_current_target(cmd_ctx); + uint32_t address; + unsigned long count = 1; + arm_instruction_t cur_instruction; + + errno = 0; + switch (argc) { + case 2: + count = strtoul(args[1], NULL, 0); + if (errno) + return ERROR_FAIL; + /* FALL THROUGH */ + case 1: + address = strtoul(args[0], NULL, 0); + if (errno) + return ERROR_FAIL; + break; + default: + command_print(cmd_ctx, + "usage: cortex_m3 disassemble
[]"); + return ERROR_OK; + } - retval = armv7m_register_commands(cmd_ctx); + while (count--) { + retval = thumb2_opcode(target, address, &cur_instruction); + if (retval != ERROR_OK) + return retval; + command_print(cmd_ctx, "%s", cur_instruction.text); + address += cur_instruction.instruction_size; + } - cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands"); - register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']"); + return ERROR_OK; +} - return retval; +static const struct { + char name[10]; + unsigned mask; +} vec_ids[] = { + { "hard_err", VC_HARDERR, }, + { "int_err", VC_INTERR, }, + { "bus_err", VC_BUSERR, }, + { "state_err", VC_STATERR, }, + { "chk_err", VC_CHKERR, }, + { "nocp_err", VC_NOCPERR, }, + { "mm_err", VC_MMERR, }, + { "reset", VC_CORERESET, }, +}; + +static int +handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx, + char *cmd, char **argv, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + uint32_t demcr = 0; + int i; + + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + + if (argc > 0) { + unsigned catch = 0; + + if (argc == 1) { + if (strcmp(argv[0], "all") == 0) { + catch = VC_HARDERR | VC_INTERR | VC_BUSERR + | VC_STATERR | VC_CHKERR | VC_NOCPERR + | VC_MMERR | VC_CORERESET; + goto write; + } else if (strcmp(argv[0], "none") == 0) { + goto write; + } + } + while (argc-- > 0) { + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { + if (strcmp(argv[argc], vec_ids[i].name) != 0) + continue; + catch |= vec_ids[i].mask; + break; + } + if (i == ARRAY_SIZE(vec_ids)) { + LOG_ERROR("No CM3 vector '%s'", argv[argc]); + return ERROR_INVALID_ARGUMENTS; + } + } +write: + demcr &= ~0xffff; + demcr |= catch; + + /* write, but don't assume it stuck */ + mem_ap_write_u32(swjdp, DCB_DEMCR, demcr); + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + } + + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) + command_print(cmd_ctx, "%9s: %s", vec_ids[i].name, + (demcr & vec_ids[i].mask) ? "catch" : "ignore"); + + return ERROR_OK; } -int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int +handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; @@ -1692,3 +1837,66 @@ int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, return ERROR_OK; } + +static int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +{ + int retval; + command_t *cortex_m3_cmd; + + retval = armv7m_register_commands(cmd_ctx); + + cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", + NULL, COMMAND_ANY, "cortex_m3 specific commands"); + + register_command(cmd_ctx, cortex_m3_cmd, "disassemble", + handle_cortex_m3_disassemble_command, COMMAND_EXEC, + "disassemble Thumb2 instructions
[]"); + register_command(cmd_ctx, cortex_m3_cmd, "maskisr", + handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, + "mask cortex_m3 interrupts ['on'|'off']"); + register_command(cmd_ctx, cortex_m3_cmd, "vector_catch", + handle_cortex_m3_vector_catch_command, COMMAND_EXEC, + "catch hardware vectors ['all'|'none'|]"); + + return retval; +} + +target_type_t cortexm3_target = +{ + .name = "cortex_m3", + + .poll = cortex_m3_poll, + .arch_state = armv7m_arch_state, + + .target_request_data = cortex_m3_target_request_data, + + .halt = cortex_m3_halt, + .resume = cortex_m3_resume, + .step = cortex_m3_step, + + .assert_reset = cortex_m3_assert_reset, + .deassert_reset = cortex_m3_deassert_reset, + .soft_reset_halt = cortex_m3_soft_reset_halt, + + .get_gdb_reg_list = armv7m_get_gdb_reg_list, + + .read_memory = cortex_m3_read_memory, + .write_memory = cortex_m3_write_memory, + .bulk_write_memory = cortex_m3_bulk_write_memory, + .checksum_memory = armv7m_checksum_memory, + .blank_check_memory = armv7m_blank_check_memory, + + .run_algorithm = armv7m_run_algorithm, + + .add_breakpoint = cortex_m3_add_breakpoint, + .remove_breakpoint = cortex_m3_remove_breakpoint, + .add_watchpoint = cortex_m3_add_watchpoint, + .remove_watchpoint = cortex_m3_remove_watchpoint, + + .register_commands = cortex_m3_register_commands, + .target_create = cortex_m3_target_create, + .init_target = cortex_m3_init_target, + .has_mmu = cortex_m3_has_mmu, + .examine = cortex_m3_examine, +}; +