X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=d617817d14c8c17c8d85a39fb4d80a23bfd9bcdc;hp=d8a28796a25c066f53370165575014612c923bcb;hb=42ef503d37b18d907da16d26e99167566d5aabd1;hpb=8fb2baaa6b428bd50165f045749786c34857ab02 diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index d8a28796a2..d617817d14 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -37,6 +37,10 @@ #include "arm_disassembler.h" +/* NOTE: most of this should work fine for the Cortex-M1 and + * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M. + */ + #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) @@ -52,12 +56,6 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[]; extern reg_t armv7m_gdb_dummy_cpsr_reg; #endif -static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu) -{ - *has_mmu = false; - return ERROR_OK; -} - static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) { @@ -123,10 +121,8 @@ static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, static int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -138,10 +134,8 @@ static int cortex_m3_write_debug_halt_mask(target_t *target, static int cortex_m3_clear_halt(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* clear step if any */ cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); @@ -157,10 +151,8 @@ static int cortex_m3_clear_halt(target_t *target) static int cortex_m3_single_step_core(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dhcsr_save; /* backup dhcsr reg */ @@ -183,11 +175,8 @@ static int cortex_m3_endreset_event(target_t *target) { int i; uint32_t dcb_demcr; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; @@ -242,9 +231,7 @@ static int cortex_m3_endreset_event(target_t *target) static int cortex_m3_examine_debug_reason(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ @@ -272,9 +259,7 @@ static int cortex_m3_examine_debug_reason(target_t *target) static int cortex_m3_examine_exception_reason(target_t *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); @@ -324,10 +309,8 @@ static int cortex_m3_debug_entry(target_t *target) int i; uint32_t xPSR; int retval; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; swjdp_common_t *swjdp = &armv7m->swjdp_info; LOG_DEBUG(" "); @@ -397,11 +380,8 @@ static int cortex_m3_poll(target_t *target) { int retval; enum target_state prev_target_state = target->state; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -514,10 +494,8 @@ static int cortex_m3_halt(target_t *target) static int cortex_m3_soft_reset_halt(struct target_s *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; @@ -569,8 +547,7 @@ static void cortex_m3_enable_breakpoints(struct target_s *target) static int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); breakpoint_t *breakpoint = NULL; uint32_t resume_pc; @@ -658,9 +635,8 @@ static int cortex_m3_resume(struct target_s *target, int current, static int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; swjdp_common_t *swjdp = &armv7m->swjdp_info; breakpoint_t *breakpoint = NULL; @@ -672,12 +648,16 @@ static int cortex_m3_step(struct target_s *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value, + 0, 32, address); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)))) + if (handle_breakpoints) { + breakpoint = breakpoint_find(target, buf_get_u32(armv7m + ->core_cache->reg_list[15].value, 0, 32)); + if (breakpoint) cortex_m3_unset_breakpoint(target, breakpoint); + } target->debug_reason = DBG_REASON_SINGLESTEP; @@ -706,9 +686,8 @@ static int cortex_m3_step(struct target_s *target, int current, static int cortex_m3_assert_reset(target_t *target) { - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; int assert_srst = 1; LOG_DEBUG("target->state: %s", @@ -859,12 +838,8 @@ cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int retval; int fp_num = 0; uint32_t hilo; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list; if (breakpoint->set) { @@ -928,9 +903,7 @@ static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; if (!breakpoint->set) @@ -984,9 +957,7 @@ cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) static int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); if (cortex_m3->auto_bp_type) { @@ -1035,9 +1006,7 @@ cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) static int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1067,10 +1036,7 @@ cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int dwt_num = 0; uint32_t mask, temp; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* watchpoint params were validated earlier */ mask = 0; @@ -1133,9 +1099,7 @@ cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) static int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); cortex_m3_dwt_comparator_t *comparator; int dwt_num; @@ -1172,9 +1136,7 @@ cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) static int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1199,7 +1161,7 @@ cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) unsigned mask; for (mask = 0; mask < 16; mask++) { - if ((1 << mask) == watchpoint->length) + if ((1u << mask) == watchpoint->length) break; } if (mask == 16) { @@ -1232,9 +1194,7 @@ cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) static int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1271,8 +1231,7 @@ static int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; /* NOTE: we "know" here that the register identifiers used @@ -1336,9 +1295,7 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target, { int retval; uint32_t reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; #ifdef ARMV7_GDB_HACKS @@ -1413,8 +1370,7 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target, static int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; @@ -1446,8 +1402,7 @@ static int cortex_m3_read_memory(struct target_s *target, uint32_t address, static int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; @@ -1480,28 +1435,160 @@ static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, return cortex_m3_write_memory(target, address, 4, count, buffer); } -static void cortex_m3_build_reg_cache(target_t *target) +static int cortex_m3_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { armv7m_build_reg_cache(target); + return ERROR_OK; } -static int cortex_m3_init_target(struct command_context_s *cmd_ctx, - struct target_s *target) +/* REVISIT cache valid/dirty bits are unmaintained. We could set "valid" + * on r/w if the core is not running, and clear on resume or reset ... or + * at least, in a post_restore_context() method. + */ + +struct dwt_reg_state { + struct target_s *target; + uint32_t addr; + uint32_t value; /* scratch/cache */ +}; + +static int cortex_m3_dwt_get_reg(struct reg_s *reg) { - cortex_m3_build_reg_cache(target); - return ERROR_OK; + struct dwt_reg_state *state = reg->arch_info; + + return target_read_u32(state->target, state->addr, &state->value); +} + +static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf) +{ + struct dwt_reg_state *state = reg->arch_info; + + return target_write_u32(state->target, state->addr, + buf_get_u32(buf, 0, reg->size)); +} + +struct dwt_reg { + uint32_t addr; + char *name; + unsigned size; +}; + +static struct dwt_reg dwt_base_regs[] = { + { DWT_CTRL, "dwt_ctrl", 32, }, + { DWT_CYCCNT, "dwt_cyccnt", 32, }, + /* plus some 8 bit counters, useful for profiling with TPIU */ +}; + +static struct dwt_reg dwt_comp[] = { +#define DWT_COMPARATOR(i) \ + { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \ + { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \ + { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, } + DWT_COMPARATOR(0), + DWT_COMPARATOR(1), + DWT_COMPARATOR(2), + DWT_COMPARATOR(3), +#undef DWT_COMPARATOR +}; + +static int dwt_reg_type = -1; + +static void +cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d) +{ + struct dwt_reg_state *state; + + state = calloc(1, sizeof *state); + if (!state) + return; + state->addr = d->addr; + state->target = t; + + r->name = d->name; + r->size = d->size; + r->value = &state->value; + r->arch_info = state; + r->arch_type = dwt_reg_type; +} + +static void +cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target) +{ + uint32_t dwtcr; + struct reg_cache_s *cache; + cortex_m3_dwt_comparator_t *comparator; + int reg, i; + + target_read_u32(target, DWT_CTRL, &dwtcr); + if (!dwtcr) { + LOG_DEBUG("no DWT"); + return; + } + + if (dwt_reg_type < 0) + dwt_reg_type = register_reg_arch_type(cortex_m3_dwt_get_reg, + cortex_m3_dwt_set_reg); + + cm3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cm3->dwt_comp_available = cm3->dwt_num_comp; + cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp, + sizeof(cortex_m3_dwt_comparator_t)); + if (!cm3->dwt_comparator_list) { +fail0: + cm3->dwt_num_comp = 0; + LOG_ERROR("out of mem"); + return; + } + + cache = calloc(1, sizeof *cache); + if (!cache) { +fail1: + free(cm3->dwt_comparator_list); + goto fail0; + } + cache->name = "cortex-m3 dwt registers"; + cache->num_regs = 2 + cm3->dwt_num_comp * 3; + cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list); + if (!cache->reg_list) { + free(cache); + goto fail1; + } + + for (reg = 0; reg < 2; reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_base_regs + reg); + + comparator = cm3->dwt_comparator_list; + for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) { + int j; + + comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; + for (j = 0; j < 3; j++, reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_comp + 3 * i + j); + } + + *register_get_last_cache_p(&target->reg_cache) = cache; + cm3->dwt_cache = cache; + + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + dwtcr, cm3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + + /* REVISIT: if num_comp > 1, check whether comparator #1 can + * implement single-address data value watchpoints ... so we + * won't need to check it later, when asked to set one up. + */ } static int cortex_m3_examine(struct target_s *target) { int retval; - uint32_t cpuid, fpcr, dwtcr; + uint32_t cpuid, fpcr; int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info; if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) return retval; @@ -1537,21 +1624,7 @@ static int cortex_m3_examine(struct target_s *target) LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list = calloc( - cortex_m3->dwt_num_comp, - sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { - cortex_m3->dwt_comparator_list[i] - .dwt_comparator_address = DWT_COMP0 + 0x10 * i; - } - if (cortex_m3->dwt_num_comp) - LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", - dwtcr, cortex_m3->dwt_num_comp, - (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + cortex_m3_dwt_setup(cortex_m3, target); } return ERROR_OK; @@ -1581,7 +1654,7 @@ static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ct static int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) { - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; uint8_t data; uint8_t ctrl; @@ -1601,7 +1674,7 @@ static int cortex_m3_handle_target_request(void *priv) target_t *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common_s *armv7m = target_to_armv7m(target); swjdp_common_t *swjdp = &armv7m->swjdp_info; if (!target->dbg_msg_enabled) @@ -1635,11 +1708,10 @@ static int cortex_m3_handle_target_request(void *priv) } static int cortex_m3_init_arch_info(target_t *target, - cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) + cortex_m3_common_t *cortex_m3, struct jtag_tap *tap) { int retval; - armv7m_common_t *armv7m; - armv7m = &cortex_m3->armv7m; + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; armv7m_init_arch_info(target, armv7m); @@ -1654,11 +1726,6 @@ static int cortex_m3_init_arch_info(target_t *target, armv7m->swjdp_info.memaccess_tck = 8; armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */ - /* initialize arch-specific breakpoint handling */ - - cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; - cortex_m3->arch_info = NULL; - /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; @@ -1667,7 +1734,6 @@ static int cortex_m3_init_arch_info(target_t *target, armv7m->pre_restore_context = NULL; armv7m->post_restore_context = NULL; - armv7m->arch_info = cortex_m3; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; @@ -1685,38 +1751,56 @@ static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); + cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; cortex_m3_init_arch_info(target, cortex_m3, target->tap); return ERROR_OK; } +/*--------------------------------------------------------------------------*/ + +static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx, + struct cortex_m3_common_s *cm3) +{ + if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { + command_print(cmd_ctx, "target is not a Cortex-M3"); + return ERROR_TARGET_INVALID; + } + return ERROR_OK; +} + +/* + * Only stuff below this line should need to verify that its target + * is a Cortex-M3. Everything else should have indirected through the + * cortexm3_target structure, which is only used with CM3 targets. + */ + /* * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well * as at least ARM-1156T2. The interesting thing about Cortex-M is * that *only* Thumb2 disassembly matters. There are also some small * additions to Thumb2 that are specific to ARMv7-M. */ -static int -handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_disassemble_command) { - int retval = ERROR_OK; + int retval; target_t *target = get_current_target(cmd_ctx); + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); uint32_t address; unsigned long count = 1; arm_instruction_t cur_instruction; + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; + errno = 0; switch (argc) { case 2: - count = strtoul(args[1], NULL, 0); - if (errno) - return ERROR_FAIL; + COMMAND_PARSE_NUMBER(ulong, args[1], count); /* FALL THROUGH */ case 1: - address = strtoul(args[0], NULL, 0); - if (errno) - return ERROR_FAIL; + COMMAND_PARSE_NUMBER(u32, args[0], address); break; default: command_print(cmd_ctx, @@ -1749,40 +1833,44 @@ static const struct { { "reset", VC_CORERESET, }, }; -static int -handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx, - char *cmd, char **argv, int argc) +COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct armv7m_common_s *armv7m = &cortex_m3->armv7m; swjdp_common_t *swjdp = &armv7m->swjdp_info; uint32_t demcr = 0; + int retval; int i; + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); if (argc > 0) { unsigned catch = 0; if (argc == 1) { - if (strcmp(argv[0], "all") == 0) { + if (strcmp(args[0], "all") == 0) { catch = VC_HARDERR | VC_INTERR | VC_BUSERR | VC_STATERR | VC_CHKERR | VC_NOCPERR | VC_MMERR | VC_CORERESET; goto write; - } else if (strcmp(argv[0], "none") == 0) { + } else if (strcmp(args[0], "none") == 0) { goto write; } } while (argc-- > 0) { for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { - if (strcmp(argv[argc], vec_ids[i].name) != 0) + if (strcmp(args[argc], vec_ids[i].name) != 0) continue; catch |= vec_ids[i].mask; break; } if (i == ARRAY_SIZE(vec_ids)) { - LOG_ERROR("No CM3 vector '%s'", argv[argc]); + LOG_ERROR("No CM3 vector '%s'", args[argc]); return ERROR_INVALID_ARGUMENTS; } } @@ -1802,17 +1890,19 @@ write: return ERROR_OK; } -static int -handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) { target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + int retval; + + retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -1896,7 +1986,5 @@ target_type_t cortexm3_target = .register_commands = cortex_m3_register_commands, .target_create = cortex_m3_target_create, .init_target = cortex_m3_init_target, - .has_mmu = cortex_m3_has_mmu, .examine = cortex_m3_examine, }; -