X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=c1ebae3f10eede1c4f39aa7005dd2a3a0d73a9af;hp=f1513c7a360a2810fd192e782184436c923e5fb7;hb=89fa8ce2d8c58707f3dfda397138f8ee336e1a47;hpb=e27696f6b04459e935a0a5f65f7f668cb02970dd diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index f1513c7a36..9c3d2d9d69 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -1,9 +1,13 @@ /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * + * * * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -18,256 +22,370 @@ * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * * + * * + * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) * + * * ***************************************************************************/ #ifdef HAVE_CONFIG_H #include "config.h" #endif -#include "replacements.h" - +#include "breakpoints.h" #include "cortex_m3.h" -#include "armv7m.h" - +#include "target_request.h" +#include "target_type.h" +#include "arm_disassembler.h" #include "register.h" -#include "target.h" -#include "log.h" -#include "jtag.h" -#include "arm_jtag.h" - -#include -#include +#include "arm_opcodes.h" +#include "arm_semihosting.h" + +/* NOTE: most of this should work fine for the Cortex-M1 and + * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M. + * Some differences: M0/M1 doesn't have FBP remapping or the + * DWT tracing/profiling support. (So the cycle counter will + * not be usable; the other stuff isn't currently used here.) + * + * Although there are some workarounds for errata seen only in r0p0 + * silicon, such old parts are hard to find and thus not much tested + * any longer. + */ + +/** + * Returns the type of a break point required by address location + */ +#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT) -/* cli handling */ -int cortex_m3_register_commands(struct command_context_s *cmd_ctx); /* forward declarations */ -void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target); -void cortex_m3_enable_breakpoints(struct target_s *target); -void cortex_m3_enable_watchpoints(struct target_s *target); -void cortex_m3_disable_bkpts_and_wpts(struct target_s *target); -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(); -int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); -int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); - -target_type_t cortexm3_target = +static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); +static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +static void cortex_m3_enable_watchpoints(struct target *target); +static int cortex_m3_store_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t value); + +static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, + uint32_t *value, int regnum) { - .name = "cortex_m3", + int retval; + uint32_t dcrdr; - .poll = cortex_m3_poll, - .arch_state = armv7m_arch_state, + /* because the DCB_DCRDR is used for the emulated dcc channel + * we have to save/restore the DCB_DCRDR when used */ - .target_request_data = NULL, + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; - .halt = cortex_m3_halt, - .resume = cortex_m3_resume, - .step = cortex_m3_step, + /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); + if (retval != ERROR_OK) + return retval; - .assert_reset = cortex_m3_assert_reset, - .deassert_reset = cortex_m3_deassert_reset, - .soft_reset_halt = cortex_m3_soft_reset_halt, - .prepare_reset_halt = cortex_m3_prepare_reset_halt, - - .get_gdb_reg_list = armv7m_get_gdb_reg_list, + /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + if (retval != ERROR_OK) + return retval; - .read_memory = cortex_m3_read_memory, - .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, - .checksum_memory = armv7m_checksum_memory, - - .run_algorithm = armv7m_run_algorithm, - - .add_breakpoint = cortex_m3_add_breakpoint, - .remove_breakpoint = cortex_m3_remove_breakpoint, - .add_watchpoint = cortex_m3_add_watchpoint, - .remove_watchpoint = cortex_m3_remove_watchpoint, + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; - .register_commands = cortex_m3_register_commands, - .target_command = cortex_m3_target_command, - .init_target = cortex_m3_init_target, - .quit = cortex_m3_quit -}; + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); -int cortex_m3_clear_halt(target_t *target) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - /* Read Debug Fault Status Register */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ - ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); - DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); - - return ERROR_OK; + return retval; } -int cortex_m3_single_step_core(target_t *target) +static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, + uint32_t value, int regnum) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + int retval; + uint32_t dcrdr; - if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN ); - cortex_m3->dcb_dhcsr |= C_MASKINTS; - DEBUG(" "); - cortex_m3_clear_halt(target); - - return ERROR_OK; + /* because the DCB_DCRDR is used for the emulated dcc channel + * we have to save/restore the DCB_DCRDR when used */ + + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; + + /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + // XXX check retval + + /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + // XXX check retval + + retval = dap_run(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); + + return retval; } -int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_invalue, &r0_outvalue */ ) +static int cortex_m3_write_debug_halt_mask(struct target *target, + uint32_t mask_on, uint32_t mask_off) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - u32 savedram; - int retvalue; - - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - ahbap_write_system_u32(swjdp, 0x20000000, opcode); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = 1; - retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); - - return retvalue; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + + /* mask off status bits */ + cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); + /* create new register mask */ + cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on; + + return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); } -/* Enable interrupts */ -int cortex_m3_cpsie(target_t *target, u32 IF) +static int cortex_m3_clear_halt(struct target *target) { - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + int retval; + + /* clear step if any */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); + + /* Read Debug Fault Status Register */ + retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; + + /* Clear Debug Fault Status */ + retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr); + + return ERROR_OK; } -/* Disable interrupts */ -int cortex_m3_cpsid(target_t *target, u32 IF) +static int cortex_m3_single_step_core(struct target *target) { - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + uint32_t dhcsr_save; + int retval; + + /* backup dhcsr reg */ + dhcsr_save = cortex_m3->dcb_dhcsr; + + /* Mask interrupts before clearing halt, if done already. This avoids + * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing + * HALT can put the core into an unknown state. + */ + if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) + { + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG(" "); + + /* restore dhcsr reg */ + cortex_m3->dcb_dhcsr = dhcsr_save; + cortex_m3_clear_halt(target); + + return ERROR_OK; } -int cortex_m3_endreset_event(target_t *target) +static int cortex_m3_endreset_event(struct target *target) { int i; - u32 dcb_demcr; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; - cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; - - ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); - DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr); - + int retval; + uint32_t dcb_demcr; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; + struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; + + /* REVISIT The four debug monitor bits are currently ignored... */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr); + + /* this register is used for emulated dcc channel */ + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + if (retval != ERROR_OK) + return retval; + /* Enable debug requests */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); - /* Enable trace and dwt */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); - /* Monitor bus faults */ - ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA ); + { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + + /* clear any interrupt masking */ + cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS); + + /* Enable features controlled by ITM and DWT blocks, and catch only + * the vectors we were told to pay attention to. + * + * Target firmware is responsible for all fault handling policy + * choices *EXCEPT* explicitly scripted overrides like "vector_catch" + * or manual updates to the NVIC SHCSR and CCR registers. + */ + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr); + if (retval != ERROR_OK) + return retval; + + /* Paranoia: evidently some (early?) chips don't preserve all the + * debug state (including FBP, DWT, etc) across reset... + */ /* Enable FPB */ - target_write_u32(target, FP_CTRL, 3); + retval = target_write_u32(target, FP_CTRL, 3); + if (retval != ERROR_OK) + return retval; + + cortex_m3->fpb_enabled = 1; /* Restore FPB registers */ - for ( i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { - target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); + retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); + if (retval != ERROR_OK) + return retval; } - + /* Restore DWT registers */ - for ( i = 0; i < cortex_m3->dwt_num_comp; i++) - { - target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); - } - swjdp_transaction_endcheck(swjdp); - - /* Make sure working_areas are all free */ - target_free_all_working_areas(target); - - /* We are in process context */ - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - armv7m_invalidate_core_regs(target); - return ERROR_OK; + for (i = 0; i < cortex_m3->dwt_num_comp; i++) + { + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, + dwt_list[i].comp); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4, + dwt_list[i].mask); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, + dwt_list[i].function); + if (retval != ERROR_OK) + return retval; + } + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; + + register_cache_invalidate(cortex_m3->armv7m.core_cache); + + /* make sure we have latest dhcsr flags */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + + return retval; } -int cortex_m3_examine_debug_reason(target_t *target) +static int cortex_m3_examine_debug_reason(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ - + if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - - /* INCOPMPLETE */ - - if (cortex_m3->nvic_dfsr & 0x2) + if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; - if (cortex_m3->nvic_dfsr & 0x4) + if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WPTANDBKPT; } - else if (cortex_m3->nvic_dfsr & 0x4) + else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; + else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) + target->debug_reason = DBG_REASON_BREAKPOINT; + else /* EXTERNAL, HALTED */ + target->debug_reason = DBG_REASON_UNDEFINED; } return ERROR_OK; } -int cortex_m3_examine_exception_reason(target_t *target) +static int cortex_m3_examine_exception_reason(struct target *target) { - u32 shcsr, except_sr, cfsr = -1, except_ar = -1; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval; - ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr); + retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); + if (retval != ERROR_OK) + return retval; switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ - ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + if (retval != ERROR_OK) + return retval; if (except_sr & 0x40000000) { - ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); + if (retval != ERROR_OK) + return retval; } break; case 4: /* Memory Management */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); - ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 5: /* Bus Fault */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); - ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 6: /* Usage Fault */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 11: /* SVCall */ break; case 12: /* Debug Monitor */ - ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 14: /* PendSV */ break; @@ -277,106 +395,196 @@ int cortex_m3_examine_exception_reason(target_t *target) except_sr = 0; break; } - swjdp_transaction_endcheck(swjdp); - DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ - shcsr, except_sr, cfsr, except_ar); - return ERROR_OK; + retval = dap_run(swjdp); + if (retval == ERROR_OK) + LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 + ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32, + armv7m_exception_string(armv7m->exception_number), + shcsr, except_sr, cfsr, except_ar); + return retval; } -int cortex_m3_debug_entry(target_t *target) +/* PSP is used in some thread modes */ +static const int armv7m_psp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + +/* MSP is used in handler and some thread modes */ +static const int armv7m_msp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + +static int cortex_m3_debug_entry(struct target *target) { int i; - u32 xPSR; + uint32_t xPSR; int retval; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct arm *arm = &armv7m->arm; + struct adiv5_dap *swjdp = &armv7m->dap; + struct reg *r; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - DEBUG(" "); - if (armv7m->pre_debug_entry) - armv7m->pre_debug_entry(target); + LOG_DEBUG(" "); cortex_m3_clear_halt(target); - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK) return retval; /* Examine target state and mode */ - /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7M_PRIMASK; i++) + /* First load register acessible through core debug port*/ + int num_regs = armv7m->core_cache->num_regs; + + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + armv7m->read_core_reg(target, i); } - xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32); - - /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/ + r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + xPSR = buf_get_u32(r->value, 0, 32); + +#ifdef ARMV7_GDB_HACKS + /* FIXME this breaks on scan chains with more than one Cortex-M3. + * Instead, each CM3 should have its own dummy value... + */ + /* copy real xpsr reg for gdb, setting thumb bit */ + buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR); + buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1); + armv7m_gdb_dummy_cpsr_reg.valid = r->valid; + armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty; +#endif + + /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ if (xPSR & 0xf00) { - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + r->dirty = r->valid; cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } + /* Are we in an exception handler */ + if (xPSR & 0x1FF) + { + armv7m->core_mode = ARMV7M_MODE_HANDLER; + armv7m->exception_number = (xPSR & 0x1FF); - /* Now we can load SP core registers */ - for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) + arm->core_mode = ARM_MODE_HANDLER; + arm->map = armv7m_msp_reg_map; + } + else { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + unsigned control = buf_get_u32(armv7m->core_cache + ->reg_list[ARMV7M_CONTROL].value, 0, 2); + + /* is this thread privileged? */ + armv7m->core_mode = control & 1; + arm->core_mode = armv7m->core_mode + ? ARM_MODE_USER_THREAD + : ARM_MODE_THREAD; + + /* which stack is it using? */ + if (control & 2) + arm->map = armv7m_psp_reg_map; + else + arm->map = armv7m_msp_reg_map; + + armv7m->exception_number = 0; } - /* Are we in an exception handler */ - armv7m->core_mode = (xPSR & 0x1FF) ? ARMV7M_MODE_HANDLER : ARMV7M_MODE_THREAD; - armv7m->exception_number = xPSR & 0x1FF; if (armv7m->exception_number) { cortex_m3_examine_exception_reason(target); } - DEBUG("entered debug state at PC 0x%x, target->state: %s ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); + LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", + armv7m_mode_strings[armv7m->core_mode], + *(uint32_t*)(arm->pc->value), + target_state_name(target)); if (armv7m->post_debug_entry) - armv7m->post_debug_entry(target); + { + retval = armv7m->post_debug_entry(target); + if (retval != ERROR_OK) + return retval; + } return ERROR_OK; } -enum target_state cortex_m3_poll(target_t *target) +static int cortex_m3_poll(struct target *target) { - int retval; - u32 prev_target_state = target->state; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + int detected_failure = ERROR_OK; + int retval = ERROR_OK; + enum target_state prev_target_state = target->state; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* Read from Debug Halting Control and Status Register */ - retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) { target->state = TARGET_UNKNOWN; - return TARGET_UNKNOWN; + return retval; + } + + /* Recover from lockup. See ARMv7-M architecture spec, + * section B1.5.15 "Unrecoverable exception cases". + */ + if (cortex_m3->dcb_dhcsr & S_LOCKUP) { + LOG_ERROR("%s -- clearing lockup after double fault", + target_name(target)); + cortex_m3_write_debug_halt_mask(target, C_HALT, 0); + target->debug_reason = DBG_REASON_DBGRQ; + + /* We have to execute the rest (the "finally" equivalent, but + * still throw this exception again). + */ + detected_failure = ERROR_FAIL; + + /* refresh status bits */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; } - + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { - target->state = TARGET_RESET; - return target->state; + /* check if still in reset */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; + + if (cortex_m3->dcb_dhcsr & S_RESET_ST) + { + target->state = TARGET_RESET; + return ERROR_OK; + } } - else if (target->state == TARGET_RESET) + + if (target->state == TARGET_RESET) { - /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */ - DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr); + /* Cannot switch context while running so endreset is + * called with target->state == TARGET_RESET + */ + LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32, + cortex_m3->dcb_dhcsr); cortex_m3_endreset_event(target); target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; } - + if (cortex_m3->dcb_dhcsr & S_HALT) { target->state = TARGET_HALTED; @@ -384,56 +592,64 @@ enum target_state cortex_m3_poll(target_t *target) if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) { if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return TARGET_UNKNOWN; - + return retval; + + if (arm_semihosting(target, &retval) != 0) + return retval; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); } if (prev_target_state == TARGET_DEBUG_RUNNING) { - DEBUG(" "); + LOG_DEBUG(" "); if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return TARGET_UNKNOWN; + return retval; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } } - - /* - if (cortex_m3->dcb_dhcsr & S_SLEEP) - target->state = TARGET_SLEEP; - */ - /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); - return target->state; + /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state. + * How best to model low power modes? + */ + + if (target->state == TARGET_UNKNOWN) + { + /* check if processor is retiring instructions */ + if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) + { + target->state = TARGET_RUNNING; + retval = ERROR_OK; + } + } + + /* Did we detect a failure condition that we cleared? */ + if (detected_failure != ERROR_OK) + retval = detected_failure; + return retval; } -int cortex_m3_halt(target_t *target) +static int cortex_m3_halt(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - DEBUG("target->state: %s", target_state_strings[target->state]); - + LOG_DEBUG("target->state: %s", + target_state_name(target)); + if (target->state == TARGET_HALTED) { - WARNING("target was already halted"); - return ERROR_TARGET_ALREADY_HALTED; + LOG_DEBUG("target was already halted"); + return ERROR_OK; } - + if (target->state == TARGET_UNKNOWN) { - WARNING("target was in unknown state when halt was requested"); + LOG_WARNING("target was in unknown state when halt was requested"); } - - if (target->state == TARGET_RESET) + + if (target->state == TARGET_RESET) { - if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { - ERROR("can't request a halt while in reset if nSRST pulls nTRST"); + LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; } else @@ -442,413 +658,509 @@ int cortex_m3_halt(target_t *target) * debug entry was already prepared in cortex_m3_prepare_reset_halt() */ target->debug_reason = DBG_REASON_DBGRQ; - - return ERROR_OK; + + return ERROR_OK; } } /* Write to Debug Halting Control and Status Register */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); + cortex_m3_write_debug_halt_mask(target, C_HALT, 0); target->debug_reason = DBG_REASON_DBGRQ; - + return ERROR_OK; } -int cortex_m3_soft_reset_halt(struct target_s *target) +static int cortex_m3_soft_reset_halt(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - u32 dcb_dhcsr = 0; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + uint32_t dcb_dhcsr = 0; int retval, timeout = 0; - - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - DEBUG("Changing to process contex registers"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } - /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); - - /* Request a reset */ - ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET ); + /* Enter debug state on reset; restore DEMCR in endreset_event() */ + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + if (retval != ERROR_OK) + return retval; + + /* Request a core-only reset */ + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | AIRCR_VECTRESET); + if (retval != ERROR_OK) + return retval; target->state = TARGET_RESET; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); while (timeout < 100) { - retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) + retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, + &cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; + if ((dcb_dhcsr & S_HALT) + && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { - DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); + LOG_DEBUG("system reset-halted, DHCSR 0x%08x, " + "DFSR 0x%08x", + (unsigned) dcb_dhcsr, + (unsigned) cortex_m3->nvic_dfsr); cortex_m3_poll(target); + /* FIXME restore user's vector catch config */ return ERROR_OK; } else - DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout); + LOG_DEBUG("waiting for system reset-halt, " + "DHCSR 0x%08x, %d ms", + (unsigned) dcb_dhcsr, timeout); } timeout++; - usleep(1000); + alive_sleep(1); } - + return ERROR_OK; } -int cortex_m3_prepare_reset_halt(struct target_s *target) +static void cortex_m3_enable_breakpoints(struct target *target) { - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - u32 dcb_demcr, dcb_dhcsr; - - /* Enable debug requests */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); - - /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); - - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); - ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); - DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr); - - return ERROR_OK; + struct breakpoint *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (!breakpoint->set) + cortex_m3_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } } -int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) +static int cortex_m3_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - breakpoint_t *breakpoint = NULL; - u32 dcb_dhcsr, resume_pc; - + struct armv7m_common *armv7m = target_to_armv7m(target); + struct breakpoint *breakpoint = NULL; + uint32_t resume_pc; + struct reg *r; + if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (!debug_execution) { - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - WARNING("Incorrect context in resume"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } - target_free_all_working_areas(target); cortex_m3_enable_breakpoints(target); cortex_m3_enable_watchpoints(target); - - /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */ } - - dcb_dhcsr = DBGKEY | C_DEBUGEN; + if (debug_execution) { - /* Check that we are using debug_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT) - { - WARNING("Incorrect context in debug_exec resume"); - armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT); - } + r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK; + /* Disable interrupts */ - /* - We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, - This is probably the same inssue as Cortex-M3 Errata 377493: - C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. - */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + /* We disable interrupts in the PRIMASK register instead of + * masking with C_MASKINTS. This is probably the same issue + * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS + * in parallel with disabled interrupts can cause local faults + * to not be taken. + * + * REVISIT this clearly breaks non-debug execution, since the + * PRIMASK register state isn't saved/restored... workaround + * by never resuming app code after debug execution. + */ + buf_set_u32(r->value, 0, 1, 1); + r->dirty = true; + r->valid = true; + /* Make sure we are in Thumb mode */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24)); + r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + buf_set_u32(r->value, 24, 1, 1); + r->dirty = true; + r->valid = true; } /* current = 1: continue on current pc, otherwise continue at
*/ - if (!current) + r = armv7m->arm.pc; + if (!current) + { + buf_set_u32(r->value, 0, 32, address); + r->dirty = true; + r->valid = true; + } + + /* if we halted last time due to a bkpt instruction + * then we have to manually step over it, otherwise + * the core will break again */ + + if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32)) + && !debug_execution) { - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); - armv7m->core_cache->reg_list[15].dirty = 1; - armv7m->core_cache->reg_list[15].valid = 1; + armv7m_maybe_skip_bkpt_inst(target, NULL); } - - resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32); + + resume_pc = buf_get_u32(r->value, 0, 32); armv7m_restore_context(target); - + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { /* Single step past breakpoint at current address */ if ((breakpoint = breakpoint_find(target, resume_pc))) { - DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); - cortex_m3_unset_breakpoint(target, breakpoint); - cortex_m3_single_step_core(target); - cortex_m3_set_breakpoint(target, breakpoint); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + breakpoint->address, + breakpoint->unique_id); + cortex_m3_unset_breakpoint(target, breakpoint); + cortex_m3_single_step_core(target); + cortex_m3_set_breakpoint(target, breakpoint); } } - /* Set/Clear C_MASKINTS in a separate operation */ - if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); - /* Restart core */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); + cortex_m3_write_debug_halt_mask(target, 0, C_HALT); + target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(armv7m->core_cache); + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - DEBUG("target resumed at 0x%x",resume_pc); + LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - DEBUG("target debug resumed at 0x%x",resume_pc); + LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc); } - + return ERROR_OK; } -//int irqstepcount=0; -int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints) +/* int irqstepcount = 0; */ +static int cortex_m3_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - breakpoint_t *breakpoint = NULL; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct adiv5_dap *swjdp = &armv7m->dap; + struct breakpoint *breakpoint = NULL; + struct reg *pc = armv7m->arm.pc; + bool bkpt_inst_found = false; if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - - /* Check that we are using process_context, or change and print warning */ - if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) - { - WARNING("Incorrect context in step, must be process"); - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - } /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); - + buf_set_u32(pc->value, 0, 32, address); + + uint32_t pc_value = buf_get_u32(pc->value, 0, 32); + /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)))) + if (handle_breakpoints) { + breakpoint = breakpoint_find(target, pc_value); + if (breakpoint) cortex_m3_unset_breakpoint(target, breakpoint); - + } + + armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found); + target->debug_reason = DBG_REASON_SINGLESTEP; - + armv7m_restore_context(target); - - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - - if (cortex_m3->dcb_dhcsr & C_MASKINTS) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN); - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - - /* If we run in process context then registers are now invalid */ - if (armv7m_get_context(target) == ARMV7M_PROCESS_CONTEXT) - armv7m_invalidate_core_regs(target); - - if (breakpoint) - cortex_m3_set_breakpoint(target, breakpoint); - DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - cortex_m3_debug_entry(target); - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + /* if no bkpt instruction is found at pc then we can perform + * a normal step, otherwise we have to manually step over the bkpt + * instruction - as such simulate a step */ + if (bkpt_inst_found == false) + { + /* set step and clear halt */ + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + } + + int retval; + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; + + /* registers are now invalid */ + register_cache_invalidate(cortex_m3->armv7m.core_cache); + + if (breakpoint) + cortex_m3_set_breakpoint(target, breakpoint); + + LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + + retval = cortex_m3_debug_entry(target); + if (retval != ERROR_OK) + return retval; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + + LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); - DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); return ERROR_OK; } -int cortex_m3_assert_reset(target_t *target) +static int cortex_m3_assert_reset(struct target *target) { + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config; + + LOG_DEBUG("target->state: %s", + target_state_name(target)); + + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + /* allow scripts to override the reset event */ + + target_handle_event(target, TARGET_EVENT_RESET_ASSERT); + register_cache_invalidate(cortex_m3->armv7m.core_cache); + target->state = TARGET_RESET; + + return ERROR_OK; + } + + /* Enable debug requests */ int retval; - - DEBUG("target->state: %s", target_state_strings[target->state]); - - if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) - { - /* assert SRST and TRST */ - /* system would get ouf sync if we didn't reset test-logic, too */ - if ((retval = jtag_add_reset(1, 1)) != ERROR_OK) + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) + { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + if (retval != ERROR_OK) + return retval; + + if (!target->reset_halt) + { + /* Set/Clear C_MASKINTS in a separate operation */ + if (cortex_m3->dcb_dhcsr & C_MASKINTS) { - if (retval == ERROR_JTAG_RESET_CANT_SRST) - { - WARNING("can't assert srst"); + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_DEBUGEN | C_HALT); + if (retval != ERROR_OK) return retval; - } - else - { - ERROR("unknown error"); - exit(-1); - } } - jtag_add_sleep(5000); - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) + + /* clear any debug flags before resuming */ + cortex_m3_clear_halt(target); + + /* clear C_HALT in dhcsr reg */ + cortex_m3_write_debug_halt_mask(target, 0, C_HALT); + } + else + { + /* Halt in debug on reset; endreset_event() restores DEMCR. + * + * REVISIT catching BUSERR presumably helps to defend against + * bad vector table entries. Should this include MMERR or + * other flags too? + */ + retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + if (retval != ERROR_OK) + return retval; + } + + if (jtag_reset_config & RESET_HAS_SRST) + { + /* default to asserting srst */ + if (jtag_reset_config & RESET_SRST_PULLS_TRST) { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - WARNING("srst resets test logic, too"); - retval = jtag_add_reset(1, 1); - } + jtag_add_reset(1, 1); + } + else + { + jtag_add_reset(0, 1); } } else { - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) + /* Use a standard Cortex-M3 software reset mechanism. + * We default to using VECRESET as it is supported on all current cores. + * This has the disadvantage of not resetting the peripherals, so a + * reset-init event handler is needed to perform any peripheral resets. + */ + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ) + ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ) + ? "SYSRESETREQ" : "VECTRESET"); + + if (reset_config == CORTEX_M3_RESET_VECTRESET) { + LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event " + "handler to reset any peripherals"); + } + { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - WARNING("srst resets test logic, too"); - retval = jtag_add_reset(1, 1); - } - - if (retval == ERROR_JTAG_RESET_CANT_SRST) - { - WARNING("can't assert srsrt"); + /* I do not know why this is necessary, but it + * fixes strange effects (step/resume cause NMI + * after reset) on LM3S6918 -- Michael Schwingen + */ + uint32_t tmp; + retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); + if (retval != ERROR_OK) return retval; - } - else if (retval != ERROR_OK) - { - ERROR("unknown error"); - exit(-1); - } } } - + target->state = TARGET_RESET; jtag_add_sleep(50000); - - armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); - armv7m_invalidate_core_regs(target); - return ERROR_OK; -} + register_cache_invalidate(cortex_m3->armv7m.core_cache); + + if (target->reset_halt) + { + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + } -int cortex_m3_deassert_reset(target_t *target) -{ - DEBUG("target->state: %s", target_state_strings[target->state]); - - /* deassert reset lines */ - jtag_add_reset(0, 0); - return ERROR_OK; } -void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target) +static int cortex_m3_deassert_reset(struct target *target) { + LOG_DEBUG("target->state: %s", + target_state_name(target)); -} + /* deassert reset lines */ + jtag_add_reset(0, 0); -void cortex_m3_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - cortex_m3_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } + return ERROR_OK; } -int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { - int fp_num=0; - u32 hilo; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + int retval; + int fp_num = 0; + uint32_t hilo; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list; if (breakpoint->set) { - WARNING("breakpoint already set"); + LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id); return ERROR_OK; } if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); } if (breakpoint->type == BKPT_HARD) { - while(comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code)) + while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code)) fp_num++; if (fp_num >= cortex_m3->fp_num_code) { - DEBUG("ERROR Can not find free FP Comparator"); - WARNING("ERROR Can not find free FP Comparator"); - exit(-1); + LOG_ERROR("Can not find free FPB Comparator!"); + return ERROR_FAIL; } breakpoint->set = fp_num + 1; hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW; comparator_list[fp_num].used = 1; comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1; target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); - DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value); + LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value); + if (!cortex_m3->fpb_enabled) + { + LOG_DEBUG("FPB wasn't enabled, do it now"); + target_write_u32(target, FP_CTRL, 3); + } } else if (breakpoint->type == BKPT_SOFT) { - u8 code[4]; - buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); - target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code); - breakpoint->set = 0x11; /* Any nice value but 0 */ + uint8_t code[4]; + + /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for + * semihosting; don't use that. Otherwise the BKPT + * parameter is arbitrary. + */ + buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); + retval = target_read_memory(target, + breakpoint->address & 0xFFFFFFFE, + breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) + return retval; + retval = target_write_memory(target, + breakpoint->address & 0xFFFFFFFE, + breakpoint->length, 1, + code); + if (retval != ERROR_OK) + return retval; + breakpoint->set = true; } + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + breakpoint->unique_id, + (int)(breakpoint->type), + breakpoint->address, + breakpoint->length, + breakpoint->set); + return ERROR_OK; } -int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + int retval; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list; if (!breakpoint->set) { - WARNING("breakpoint not set"); + LOG_WARNING("breakpoint not set"); return ERROR_OK; } - + + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + breakpoint->unique_id, + (int)(breakpoint->type), + breakpoint->address, + breakpoint->length, + breakpoint->set); + if (breakpoint->type == BKPT_HARD) { int fp_num = breakpoint->set - 1; if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) { - DEBUG("Invalid FP Comparator number in breakpoint"); + LOG_DEBUG("Invalid FP Comparator number in breakpoint"); return ERROR_OK; } comparator_list[fp_num].used = 0; @@ -860,543 +1172,1073 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); + if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); + if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } } - breakpoint->set = 0; + breakpoint->set = false; return ERROR_OK; } -int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); +#ifdef ARMV7_GDB_HACKS + if (breakpoint->length != 2) { + /* XXX Hack: Replace all breakpoints with length != 2 with + * a hardware breakpoint. */ + breakpoint->type = BKPT_HARD; + breakpoint->length = 2; + } +#endif } - if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) - { - INFO("flash patch comparator requested outside code memory region"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) { + if (breakpoint->type == BKPT_HARD) + { + LOG_INFO("flash patch comparator requested outside code memory region"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000)) - { - INFO("soft breakpoint requested in code (flash) memory region"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (breakpoint->type == BKPT_SOFT) + { + LOG_INFO("soft breakpoint requested in code (flash) memory region"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } } if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) { - INFO("no flash patch comparator unit available for hardware breakpoint"); + LOG_INFO("no flash patch comparator unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if ((breakpoint->length != 2)) { - INFO("only breakpoints of two bytes length supported"); + LOG_INFO("only breakpoints of two bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - + if (breakpoint->type == BKPT_HARD) cortex_m3->fp_code_available--; - cortex_m3_set_breakpoint(target, breakpoint); - - return ERROR_OK; + + return cortex_m3_set_breakpoint(target, breakpoint); } -int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + + /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); } if (breakpoint->set) { cortex_m3_unset_breakpoint(target, breakpoint); } - + if (breakpoint->type == BKPT_HARD) cortex_m3->fp_code_available++; - + return ERROR_OK; } -int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { - int dwt_num=0; - u32 mask, temp; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; - - if (watchpoint->set) - { - WARNING("watchpoint already set"); - return ERROR_OK; - } - - if (watchpoint->mask == 0xffffffffu) - { - while(comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp)) - dwt_num++; - if (dwt_num >= cortex_m3->dwt_num_comp) - { - DEBUG("ERROR Can not find free DWT Comparator"); - WARNING("ERROR Can not find free DWT Comparator"); - return -1; - } - watchpoint->set = dwt_num + 1; - mask = 0; - temp = watchpoint->length; - while (temp > 1) - { - temp = temp / 2; - mask++; - } - comparator_list[dwt_num].used = 1; - comparator_list[dwt_num].comp = watchpoint->address; - comparator_list[dwt_num].mask = mask; - comparator_list[dwt_num].function = watchpoint->rw + 5; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function); - DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); - } - else - { - WARNING("Cannot watch data values"); /* Move this test to add_watchpoint */ - return ERROR_OK; - } - + int dwt_num = 0; + uint32_t mask, temp; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + + /* watchpoint params were validated earlier */ + mask = 0; + temp = watchpoint->length; + while (temp) { + temp >>= 1; + mask++; + } + mask--; + + /* REVISIT Don't fully trust these "not used" records ... users + * may set up breakpoints by hand, e.g. dual-address data value + * watchpoint using comparator #1; comparator #0 matching cycle + * count; send data trace info through ITM and TPIU; etc + */ + struct cortex_m3_dwt_comparator *comparator; + + for (comparator = cortex_m3->dwt_comparator_list; + comparator->used && dwt_num < cortex_m3->dwt_num_comp; + comparator++, dwt_num++) + continue; + if (dwt_num >= cortex_m3->dwt_num_comp) + { + LOG_ERROR("Can not find free DWT Comparator"); + return ERROR_FAIL; + } + comparator->used = 1; + watchpoint->set = dwt_num + 1; + + comparator->comp = watchpoint->address; + target_write_u32(target, comparator->dwt_comparator_address + 0, + comparator->comp); + + comparator->mask = mask; + target_write_u32(target, comparator->dwt_comparator_address + 4, + comparator->mask); + + switch (watchpoint->rw) { + case WPT_READ: + comparator->function = 5; + break; + case WPT_WRITE: + comparator->function = 6; + break; + case WPT_ACCESS: + comparator->function = 7; + break; + } + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + + LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", + watchpoint->unique_id, dwt_num, + (unsigned) comparator->comp, + (unsigned) comparator->mask, + (unsigned) comparator->function); return ERROR_OK; - } -int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_dwt_comparator *comparator; int dwt_num; - + if (!watchpoint->set) { - WARNING("watchpoint not set"); + LOG_WARNING("watchpoint (wpid: %d) not set", + watchpoint->unique_id); return ERROR_OK; } dwt_num = watchpoint->set - 1; + LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", + watchpoint->unique_id, dwt_num, + (unsigned) watchpoint->address); + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { - DEBUG("Invalid DWT Comparator number in watchpoint"); + LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } - comparator_list[dwt_num].used = 0; - comparator_list[dwt_num].function = 0; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function); - watchpoint->set = 0; + comparator = cortex_m3->dwt_comparator_list + dwt_num; + comparator->used = 0; + comparator->function = 0; + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + + watchpoint->set = false; return ERROR_OK; } -int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - if (target->state != TARGET_HALTED) - { - WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); if (cortex_m3->dwt_comp_available < 1) { + LOG_DEBUG("no comparators?"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - - if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) - { + + /* hardware doesn't support data value masking */ + if (watchpoint->mask != ~(uint32_t)0) { + LOG_DEBUG("watchpoint value masks not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - + + /* hardware allows address masks of up to 32K */ + unsigned mask; + + for (mask = 0; mask < 16; mask++) { + if ((1u << mask) == watchpoint->length) + break; + } + if (mask == 16) { + LOG_DEBUG("unsupported watchpoint length"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + if (watchpoint->address & ((1 << mask) - 1)) { + LOG_DEBUG("watchpoint address is unaligned"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* Caller doesn't seem to be able to describe watching for data + * values of zero; that flags "no value". + * + * REVISIT This DWT may well be able to watch for specific data + * values. Requires comparator #1 to set DATAVMATCH and match + * the data, and another comparator (DATAVADDR0) matching addr. + */ + if (watchpoint->value) { + LOG_DEBUG("data value watchpoint not YET supported"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + cortex_m3->dwt_comp_available--; - + LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available); + return ERROR_OK; } -int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (watchpoint->set) { cortex_m3_unset_watchpoint(target, watchpoint); } - + cortex_m3->dwt_comp_available++; - + LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available); + return ERROR_OK; } -void cortex_m3_enable_watchpoints(struct target_s *target) +static void cortex_m3_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; - + struct watchpoint *watchpoint = target->watchpoints; + /* set any pending watchpoints */ while (watchpoint) { - if (watchpoint->set == 0) + if (!watchpoint->set) cortex_m3_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; } } -int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 * value) +static int cortex_m3_load_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: /* read a normal core register */ - retval = ahbap_read_coreregister_u32(swjdp, value, num); - + retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); + if (retval != ERROR_OK) { - ERROR("JTAG failure %i",retval); + LOG_ERROR("JTAG failure %i",retval); return ERROR_JTAG_DEVICE_ERROR; } - //DEBUG("load from core reg %i value 0x%x",num,*value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* read other registers */ - /* cortex_m3_MRS(struct target_s *target, int num, u32* value) */ - u32 savedram; - u32 SYSm; - u32 instr; - SYSm = num & 0x1F; - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - instr = ARMV7M_T_MRS(0, SYSm); - ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MRS(0, SYSm)); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - ahbap_read_coreregister_u32(swjdp, value, 0); - armv7m->core_cache->reg_list[0].dirty = 1; - armv7m->core_cache->reg_list[15].dirty = 1; - ahbap_write_system_u32(swjdp, 0x20000000, savedram); - swjdp_transaction_endcheck(swjdp); - DEBUG("load from special reg %i value 0x%x", SYSm, *value); - } - else return ERROR_INVALID_ARGUMENTS; - + LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ + cortexm3_dap_read_coreregister_u32(swjdp, value, 20); + + switch (num) + { + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t*)value, 0, 1); + break; + + case ARMV7M_BASEPRI: + *value = buf_get_u32((uint8_t*)value, 8, 8); + break; + + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t*)value, 16, 1); + break; + + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t*)value, 24, 2); + break; + } + + LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); + break; + + default: + return ERROR_INVALID_ARGUMENTS; + } + return ERROR_OK; } -int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value) +static int cortex_m3_store_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + uint32_t reg; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + +#ifdef ARMV7_GDB_HACKS + /* If the LR register is being modified, make sure it will put us + * in "thumb" mode, or an INVSTATE exception will occur. This is a + * hack to deal with the fact that gdb will sometimes "forge" + * return addresses, and doesn't set the LSB correctly (i.e., when + * printing expressions containing function calls, it sets LR = 0.) + * Valid exception return codes have bit 0 set too. + */ + if (num == ARMV7M_R14) + value |= 0x01; +#endif - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { - retval = ahbap_write_coreregister_u32(swjdp, value, num); + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: + retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { - ERROR("JTAG failure %i", retval); - armv7m->core_cache->reg_list[num].dirty = 1; + struct reg *r; + + LOG_ERROR("JTAG failure"); + r = armv7m->core_cache->reg_list + num; + r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; } - DEBUG("write core reg %i value 0x%x", num, value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* write other registers */ - u32 savedram , tempr0; - u32 SYSm; - u32 instr; - SYSm = num & 0x1F; - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - instr = ARMV7M_T_MSR(SYSm, 0); - ahbap_write_system_u32(swjdp, 0x20000000, ARMV7M_T_MSR(SYSm, 0)); - ahbap_read_coreregister_u32(swjdp, &tempr0, 0); - ahbap_write_coreregister_u32(swjdp, value, 0); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - ahbap_write_coreregister_u32(swjdp, tempr0, 0); - armv7m->core_cache->reg_list[15].dirty = 1; - ahbap_write_system_u32(swjdp, 0x20000000, savedram); - swjdp_transaction_endcheck(swjdp); - DEBUG("write special reg %i value 0x%x ", SYSm, value); - } - else return ERROR_INVALID_ARGUMENTS; - - return ERROR_OK; + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ + cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); + + switch (num) + { + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t*)®, 0, 1, value); + break; + + case ARMV7M_BASEPRI: + buf_set_u32((uint8_t*)®, 8, 8, value); + break; + + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t*)®, 16, 1, value); + break; + + case ARMV7M_CONTROL: + buf_set_u32((uint8_t*)®, 24, 2, value); + break; + } + + cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); + + LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); + break; + + default: + return ERROR_INVALID_ARGUMENTS; + } + + return ERROR_OK; } -int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int cortex_m3_read_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval = ERROR_INVALID_ARGUMENTS; - if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) - return ERROR_TARGET_UNALIGNED_ACCESS; - - /* Is not optimal, autoincrement of tar should be used ( ahbap_block_read and CSW_ADDRINC_SINGLE ) */ - switch (size) - { + /* cortex_m3 handles unaligned memory access */ + if (count && buffer) { + switch (size) { case 4: - /* TODOLATER Check error return value ! */ - { - ahbap_read_buf(swjdp, buffer, 4 * count, address); - } + retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); break; case 2: - { - ahbap_read_buf_u16(swjdp, buffer, 2 * count, address); - } + retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); break; case 1: - { - ahbap_read_buf(swjdp, buffer, count, address); - } + retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); break; - default: - ERROR("BUG: we shouldn't get here"); - exit(-1); + } } - - return ERROR_OK; + + return retval; } -int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int cortex_m3_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval = ERROR_INVALID_ARGUMENTS; - if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) - return ERROR_TARGET_UNALIGNED_ACCESS; - - switch (size) - { + if (count && buffer) { + switch (size) { case 4: - /* TODOLATER Check error return value ! */ - { - ahbap_write_buf(swjdp, buffer, 4 * count, address); - } + retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); break; case 2: - { - ahbap_write_buf_u16(swjdp, buffer, 2 * count, address); - } + retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); break; case 1: - { - ahbap_write_buf(swjdp, buffer, count, address); - } + retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); break; - default: - ERROR("BUG: we shouldn't get here"); - exit(-1); + } } - - return ERROR_OK; + + return retval; } -int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, + uint32_t count, const uint8_t *buffer) { - cortex_m3_write_memory(target, address, 4, count, buffer); - - return ERROR_OK; + return cortex_m3_write_memory(target, address, 4, count, buffer); } -void cortex_m3_build_reg_cache(target_t *target) +static int cortex_m3_init_target(struct command_context *cmd_ctx, + struct target *target) { armv7m_build_reg_cache(target); + return ERROR_OK; +} + +/* REVISIT cache valid/dirty bits are unmaintained. We could set "valid" + * on r/w if the core is not running, and clear on resume or reset ... or + * at least, in a post_restore_context() method. + */ + +struct dwt_reg_state { + struct target *target; + uint32_t addr; + uint32_t value; /* scratch/cache */ +}; + +static int cortex_m3_dwt_get_reg(struct reg *reg) +{ + struct dwt_reg_state *state = reg->arch_info; + + return target_read_u32(state->target, state->addr, &state->value); } -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf) { - u32 cpuid, fpcr, dwtcr, ictr; + struct dwt_reg_state *state = reg->arch_info; + + return target_write_u32(state->target, state->addr, + buf_get_u32(buf, 0, reg->size)); +} + +struct dwt_reg { + uint32_t addr; + char *name; + unsigned size; +}; + +static struct dwt_reg dwt_base_regs[] = { + { DWT_CTRL, "dwt_ctrl", 32, }, + /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly + * increments while the core is asleep. + */ + { DWT_CYCCNT, "dwt_cyccnt", 32, }, + /* plus some 8 bit counters, useful for profiling with TPIU */ +}; + +static struct dwt_reg dwt_comp[] = { +#define DWT_COMPARATOR(i) \ + { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \ + { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \ + { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, } + DWT_COMPARATOR(0), + DWT_COMPARATOR(1), + DWT_COMPARATOR(2), + DWT_COMPARATOR(3), +#undef DWT_COMPARATOR +}; + +static const struct reg_arch_type dwt_reg_type = { + .get = cortex_m3_dwt_get_reg, + .set = cortex_m3_dwt_set_reg, +}; + +static void +cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) +{ + struct dwt_reg_state *state; + + state = calloc(1, sizeof *state); + if (!state) + return; + state->addr = d->addr; + state->target = t; + + r->name = d->name; + r->size = d->size; + r->value = &state->value; + r->arch_info = state; + r->type = &dwt_reg_type; +} + +static void +cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target) +{ + uint32_t dwtcr; + struct reg_cache *cache; + struct cortex_m3_dwt_comparator *comparator; + int reg, i; + + target_read_u32(target, DWT_CTRL, &dwtcr); + if (!dwtcr) { + LOG_DEBUG("no DWT"); + return; + } + + cm3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cm3->dwt_comp_available = cm3->dwt_num_comp; + cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp, + sizeof(struct cortex_m3_dwt_comparator)); + if (!cm3->dwt_comparator_list) { +fail0: + cm3->dwt_num_comp = 0; + LOG_ERROR("out of mem"); + return; + } + + cache = calloc(1, sizeof *cache); + if (!cache) { +fail1: + free(cm3->dwt_comparator_list); + goto fail0; + } + cache->name = "cortex-m3 dwt registers"; + cache->num_regs = 2 + cm3->dwt_num_comp * 3; + cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list); + if (!cache->reg_list) { + free(cache); + goto fail1; + } + + for (reg = 0; reg < 2; reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_base_regs + reg); + + comparator = cm3->dwt_comparator_list; + for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) { + int j; + + comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; + for (j = 0; j < 3; j++, reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_comp + 3 * i + j); + } + + *register_get_last_cache_p(&target->reg_cache) = cache; + cm3->dwt_cache = cache; + + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + dwtcr, cm3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + + /* REVISIT: if num_comp > 1, check whether comparator #1 can + * implement single-address data value watchpoints ... so we + * won't need to check it later, when asked to set one up. + */ +} + +static int cortex_m3_examine(struct target *target) +{ + int retval; + uint32_t cpuid, fpcr; int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - cortex_m3_build_reg_cache(target); - ahbap_debugport_init(swjdp); - - /* Read from Device Identification Registers */ - target_read_u32(target, CPUID, &cpuid); - if (((cpuid >> 4) & 0xc3f) == 0xc23) - DEBUG("CORTEX-M3 processor detected"); - DEBUG("cpuid: 0x%8.8x", cpuid); - - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); - } - - /* Setup FPB */ - target_read_u32(target, FP_CTRL, &fpcr); - cortex_m3->auto_bp_type = 1; - cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; - cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; - cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); - for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + + if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) + return retval; + + if (!target_was_examined(target)) + { + target_set_examined(target); + + /* Read from Device Identification Registers */ + retval = target_read_u32(target, CPUID, &cpuid); + if (retval != ERROR_OK) + return retval; + + if (((cpuid >> 4) & 0xc3f) == 0xc23) + LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected", + (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); + LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); + + /* NOTE: FPB and DWT are both optional. */ + + /* Setup FPB */ + target_read_u32(target, FP_CTRL, &fpcr); + cortex_m3->auto_bp_type = 1; + cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */ + cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; + cortex_m3->fp_code_available = cortex_m3->fp_num_code; + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator)); + cortex_m3->fpb_enabled = fpcr & 1; + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + { + cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; + cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + } + LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + + /* Setup DWT */ + cortex_m3_dwt_setup(cortex_m3, target); + + /* These hardware breakpoints only work for code in flash! */ + LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", + target_name(target), + cortex_m3->fp_num_code, + cortex_m3->dwt_num_comp); + } + + return ERROR_OK; +} + +static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) +{ + uint16_t dcrdr; + int retval; + + mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + *ctrl = (uint8_t)dcrdr; + *value = (uint8_t)(dcrdr >> 8); + + LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl); + + /* write ack back to software dcc register + * signify we have read data */ + if (dcrdr & (1 << 0)) { - cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; - cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + dcrdr = 0; + retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + if (retval != ERROR_OK) + return retval; } - DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); - - /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list=calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) + + return ERROR_OK; +} + +static int cortex_m3_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + uint8_t data; + uint8_t ctrl; + uint32_t i; + + for (i = 0; i < (size * 4); i++) { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + cortex_m3_dcc_read(swjdp, &data, &ctrl); + buffer[i] = data; } - + return ERROR_OK; } -int cortex_m3_quit() +static int cortex_m3_handle_target_request(void *priv) { - + struct target *target = priv; + if (!target_was_examined(target)) + return ERROR_OK; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + + if (!target->dbg_msg_enabled) + return ERROR_OK; + + if (target->state == TARGET_RUNNING) + { + uint8_t data; + uint8_t ctrl; + + cortex_m3_dcc_read(swjdp, &data, &ctrl); + + /* check if we have data */ + if (ctrl & (1 << 0)) + { + uint32_t request; + + /* we assume target is quick enough */ + request = data; + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 8); + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 16); + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 24); + target_request(target, request); + } + } + return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant) +static int cortex_m3_init_arch_info(struct target *target, + struct cortex_m3_common *cortex_m3, struct jtag_tap *tap) { - armv7m_common_t *armv7m; - armv7m = &cortex_m3->armv7m; + int retval; + struct armv7m_common *armv7m = &cortex_m3->armv7m; + + armv7m_init_arch_info(target, armv7m); /* prepare JTAG information for the new target */ - cortex_m3->jtag_info.chain_pos = chain_pos; + cortex_m3->jtag_info.tap = tap; cortex_m3->jtag_info.scann_size = 4; - - cortex_m3->swjdp_info.dp_select_value = -1; - cortex_m3->swjdp_info.ap_csw_value = -1; - cortex_m3->swjdp_info.ap_tar_value = -1; - cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info; - - /* initialize arch-specific breakpoint handling */ - - cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; - cortex_m3->arch_info = NULL; + + /* default reset mode is to use srst if fitted + * if not it will use CORTEX_M3_RESET_VECTRESET */ + cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; + + armv7m->arm.dap = &armv7m->dap; + + /* Leave (only) generic DAP stuff for debugport_init(); */ + armv7m->dap.jtag_info = &cortex_m3->jtag_info; + armv7m->dap.memaccess_tck = 8; + /* Cortex-M3 has 4096 bytes autoincrement range */ + armv7m->dap.tar_autoincr_block = (1 << 12); /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; - armv7m->pre_debug_entry = NULL; armv7m->post_debug_entry = NULL; - + armv7m->pre_restore_context = NULL; - armv7m->post_restore_context = NULL; - - armv7m_init_arch_info(target, armv7m); - armv7m->arch_info = cortex_m3; + armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; -// armv7m->full_context = cortex_m3_full_context; - + + target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target); + + if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK) + { + return retval; + } + + return ERROR_OK; +} + +static int cortex_m3_target_create(struct target *target, Jim_Interp *interp) +{ + struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common)); + + cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; + cortex_m3_init_arch_info(target, cortex_m3, target->tap); + return ERROR_OK; } -/* target cortex_m3 */ -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +/*--------------------------------------------------------------------------*/ + +static int cortex_m3_verify_pointer(struct command_context *cmd_ctx, + struct cortex_m3_common *cm3) { - int chain_pos; - char *variant = NULL; - cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t)); - - if (argc < 4) - { - ERROR("'target cortex_m3' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; - - cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant); - cortex_m3_register_commands(cmd_ctx); - + if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { + command_print(cmd_ctx, "target is not a Cortex-M3"); + return ERROR_TARGET_INVALID; + } return ERROR_OK; } -int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +/* + * Only stuff below this line should need to verify that its target + * is a Cortex-M3. Everything else should have indirected through the + * cortexm3_target structure, which is only used with CM3 targets. + */ + +static const struct { + char name[10]; + unsigned mask; +} vec_ids[] = { + { "hard_err", VC_HARDERR, }, + { "int_err", VC_INTERR, }, + { "bus_err", VC_BUSERR, }, + { "state_err", VC_STATERR, }, + { "chk_err", VC_CHKERR, }, + { "nocp_err", VC_NOCPERR, }, + { "mm_err", VC_MMERR, }, + { "reset", VC_CORERESET, }, +}; + +COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { + struct target *target = get_current_target(CMD_CTX); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct adiv5_dap *swjdp = &armv7m->dap; + uint32_t demcr = 0; int retval; - - retval = armv7m_register_commands(cmd_ctx); - - return retval; + + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); + if (retval != ERROR_OK) + return retval; + + retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC > 0) { + unsigned catch = 0; + + if (CMD_ARGC == 1) { + if (strcmp(CMD_ARGV[0], "all") == 0) { + catch = VC_HARDERR | VC_INTERR | VC_BUSERR + | VC_STATERR | VC_CHKERR | VC_NOCPERR + | VC_MMERR | VC_CORERESET; + goto write; + } else if (strcmp(CMD_ARGV[0], "none") == 0) { + goto write; + } + } + while (CMD_ARGC-- > 0) { + unsigned i; + for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { + if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0) + continue; + catch |= vec_ids[i].mask; + break; + } + if (i == ARRAY_SIZE(vec_ids)) { + LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]); + return ERROR_INVALID_ARGUMENTS; + } + } +write: + /* For now, armv7m->demcr only stores vector catch flags. */ + armv7m->demcr = catch; + + demcr &= ~0xffff; + demcr |= catch; + + /* write, but don't assume it stuck (why not??) */ + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr); + if (retval != ERROR_OK) + return retval; + + /* FIXME be sure to clear DEMCR on clean server shutdown. + * Otherwise the vector catch hardware could fire when there's + * no debugger hooked up, causing much confusion... + */ + } + + for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) + { + command_print(CMD_CTX, "%9s: %s", vec_ids[i].name, + (demcr & vec_ids[i].mask) ? "catch" : "ignore"); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + int retval; + + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); + if (retval != ERROR_OK) + return retval; + + if (target->state != TARGET_HALTED) + { + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_OK; + } + + if (CMD_ARGC > 0) + { + bool enable; + COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable); + uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0); + uint32_t mask_off = enable ? 0 : C_MASKINTS; + cortex_m3_write_debug_halt_mask(target, mask_on, mask_off); + } + + command_print(CMD_CTX, "cortex_m3 interrupt mask %s", + (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off"); + + return ERROR_OK; +} + +COMMAND_HANDLER(handle_cortex_m3_reset_config_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + int retval; + char *reset_config; + + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC > 0) + { + if (strcmp(*CMD_ARGV, "sysresetreq") == 0) + cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ; + else if (strcmp(*CMD_ARGV, "vectreset") == 0) + cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; + } + + switch (cortex_m3->soft_reset_config) + { + case CORTEX_M3_RESET_SYSRESETREQ: + reset_config = "sysresetreq"; + break; + + case CORTEX_M3_RESET_VECTRESET: + reset_config = "vectreset"; + break; + + default: + reset_config = "unknown"; + break; + } + + command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config); + + return ERROR_OK; } + +static const struct command_registration cortex_m3_exec_command_handlers[] = { + { + .name = "maskisr", + .handler = handle_cortex_m3_mask_interrupts_command, + .mode = COMMAND_EXEC, + .help = "mask cortex_m3 interrupts", + .usage = "['on'|'off']", + }, + { + .name = "vector_catch", + .handler = handle_cortex_m3_vector_catch_command, + .mode = COMMAND_EXEC, + .help = "configure hardware vectors to trigger debug entry", + .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]", + }, + { + .name = "reset_config", + .handler = handle_cortex_m3_reset_config_command, + .mode = COMMAND_ANY, + .help = "configure software reset handling", + .usage = "['srst'|'sysresetreq'|'vectreset']", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration cortex_m3_command_handlers[] = { + { + .chain = armv7m_command_handlers, + }, + { + .name = "cortex_m3", + .mode = COMMAND_EXEC, + .help = "Cortex-M3 command group", + .chain = cortex_m3_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +struct target_type cortexm3_target = +{ + .name = "cortex_m3", + + .poll = cortex_m3_poll, + .arch_state = armv7m_arch_state, + + .target_request_data = cortex_m3_target_request_data, + + .halt = cortex_m3_halt, + .resume = cortex_m3_resume, + .step = cortex_m3_step, + + .assert_reset = cortex_m3_assert_reset, + .deassert_reset = cortex_m3_deassert_reset, + .soft_reset_halt = cortex_m3_soft_reset_halt, + + .get_gdb_reg_list = armv7m_get_gdb_reg_list, + + .read_memory = cortex_m3_read_memory, + .write_memory = cortex_m3_write_memory, + .bulk_write_memory = cortex_m3_bulk_write_memory, + .checksum_memory = armv7m_checksum_memory, + .blank_check_memory = armv7m_blank_check_memory, + + .run_algorithm = armv7m_run_algorithm, + + .add_breakpoint = cortex_m3_add_breakpoint, + .remove_breakpoint = cortex_m3_remove_breakpoint, + .add_watchpoint = cortex_m3_add_watchpoint, + .remove_watchpoint = cortex_m3_remove_watchpoint, + + .commands = cortex_m3_command_handlers, + .target_create = cortex_m3_target_create, + .init_target = cortex_m3_init_target, + .examine = cortex_m3_examine, +};