X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=9c3d2d9d691ffa9b13f1fd9bbbaa4518f5cc43c5;hp=3f080f13369ad48284f622cc194aee690b1ea8e6;hb=89fa8ce2d8c58707f3dfda397138f8ee336e1a47;hpb=f176278e98536981a212c0cfcee75ec94ab2c158 diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 3f080f1336..9c3d2d9d69 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -51,6 +51,11 @@ * any longer. */ +/** + * Returns the type of a break point required by address location + */ +#define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT) + /* forward declarations */ static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); @@ -520,7 +525,8 @@ static int cortex_m3_debug_entry(struct target *target) static int cortex_m3_poll(struct target *target) { - int retval; + int detected_failure = ERROR_OK; + int retval = ERROR_OK; enum target_state prev_target_state = target->state; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; @@ -535,15 +541,18 @@ static int cortex_m3_poll(struct target *target) /* Recover from lockup. See ARMv7-M architecture spec, * section B1.5.15 "Unrecoverable exception cases". - * - * REVISIT Is there a better way to report and handle this? */ if (cortex_m3->dcb_dhcsr & S_LOCKUP) { - LOG_WARNING("%s -- clearing lockup after double fault", + LOG_ERROR("%s -- clearing lockup after double fault", target_name(target)); cortex_m3_write_debug_halt_mask(target, C_HALT, 0); target->debug_reason = DBG_REASON_DBGRQ; + /* We have to execute the rest (the "finally" equivalent, but + * still throw this exception again). + */ + detected_failure = ERROR_FAIL; + /* refresh status bits */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) @@ -610,11 +619,14 @@ static int cortex_m3_poll(struct target *target) if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) { target->state = TARGET_RUNNING; - return ERROR_OK; + retval = ERROR_OK; } } - return ERROR_OK; + /* Did we detect a failure condition that we cleared? */ + if (detected_failure != ERROR_OK) + retval = detected_failure; + return retval; } static int cortex_m3_halt(struct target *target) @@ -857,10 +869,11 @@ static int cortex_m3_step(struct target *target, int current, if (!current) buf_set_u32(pc->value, 0, 32, address); + uint32_t pc_value = buf_get_u32(pc->value, 0, 32); + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { - breakpoint = breakpoint_find(target, - buf_get_u32(pc->value, 0, 32)); + breakpoint = breakpoint_find(target, pc_value); if (breakpoint) cortex_m3_unset_breakpoint(target, breakpoint); } @@ -920,14 +933,14 @@ static int cortex_m3_assert_reset(struct target *target) enum reset_types jtag_reset_config = jtag_get_reset_config(); - /* - * We can reset Cortex-M3 targets using just the NVIC without - * requiring SRST, getting a SoC reset (or a core-only reset) - * instead of a system reset. - */ - if (!(jtag_reset_config & RESET_HAS_SRST) && - (cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) { - reset_config = CORTEX_M3_RESET_VECTRESET; + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + /* allow scripts to override the reset event */ + + target_handle_event(target, TARGET_EVENT_RESET_ASSERT); + register_cache_invalidate(cortex_m3->armv7m.core_cache); + target->state = TARGET_RESET; + + return ERROR_OK; } /* Enable debug requests */ @@ -977,7 +990,7 @@ static int cortex_m3_assert_reset(struct target *target) return retval; } - if (reset_config == CORTEX_M3_RESET_SRST) + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) @@ -1064,7 +1077,7 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); } if (breakpoint->type == BKPT_HARD) @@ -1184,7 +1197,7 @@ cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); #ifdef ARMV7_GDB_HACKS if (breakpoint->length != 2) { /* XXX Hack: Replace all breakpoints with length != 2 with @@ -1195,16 +1208,18 @@ cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) #endif } - if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) - { - LOG_INFO("flash patch comparator requested outside code memory region"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) { + if (breakpoint->type == BKPT_HARD) + { + LOG_INFO("flash patch comparator requested outside code memory region"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000)) - { - LOG_INFO("soft breakpoint requested in code (flash) memory region"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (breakpoint->type == BKPT_SOFT) + { + LOG_INFO("soft breakpoint requested in code (flash) memory region"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } } if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) @@ -1239,7 +1254,7 @@ cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; + breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); } if (breakpoint->set) @@ -1536,7 +1551,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target, { struct reg *r; - LOG_ERROR("JTAG failure %i", retval); + LOG_ERROR("JTAG failure"); r = armv7m->core_cache->reg_list + num; r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; @@ -1611,7 +1626,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, } static int cortex_m3_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); struct adiv5_dap *swjdp = &armv7m->dap; @@ -1635,7 +1650,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, } static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } @@ -1938,7 +1953,7 @@ static int cortex_m3_init_arch_info(struct target *target, /* default reset mode is to use srst if fitted * if not it will use CORTEX_M3_RESET_VECTRESET */ - cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST; + cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; armv7m->arm.dap = &armv7m->dap; @@ -2131,16 +2146,10 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command) cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ; else if (strcmp(*CMD_ARGV, "vectreset") == 0) cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; - else - cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST; } switch (cortex_m3->soft_reset_config) { - case CORTEX_M3_RESET_SRST: - reset_config = "srst"; - break; - case CORTEX_M3_RESET_SYSRESETREQ: reset_config = "sysresetreq"; break;