X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=6f51d91bdf32339142a47e75cbc787afeb17f034;hp=a90baafaf57f96fcdf48bb235448b9faeee4c191;hb=b6db182c0020051e0dc642ca0b1040ea7453dcd0;hpb=85fc1e06fa086dc12dddf20d826d705e6505250d diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index a90baafaf5..6f51d91bdf 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -5,6 +5,9 @@ * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -19,39 +22,33 @@ * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * * + * * + * Cortex-M3(tm) TRM, ARM DDI 0337C * + * * ***************************************************************************/ #ifdef HAVE_CONFIG_H #include "config.h" #endif -#include "replacements.h" - #include "cortex_m3.h" -#include "armv7m.h" - -#include "register.h" -#include "target.h" #include "target_request.h" -#include "log.h" -#include "jtag.h" -#include "arm_jtag.h" -#include -#include /* cli handling */ int cortex_m3_register_commands(struct command_context_s *cmd_ctx); +int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ void cortex_m3_enable_breakpoints(struct target_s *target); void cortex_m3_enable_watchpoints(struct target_s *target); -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(); +int cortex_m3_quit(void); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); -int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int cortex_m3_examine(struct target_s *target); #ifdef ARMV7_GDB_HACKS extern u8 armv7m_gdb_dummy_cpsr_value[]; @@ -91,26 +88,95 @@ target_type_t cortexm3_target = .remove_watchpoint = cortex_m3_remove_watchpoint, .register_commands = cortex_m3_register_commands, - .target_command = cortex_m3_target_command, + .target_create = cortex_m3_target_create, .init_target = cortex_m3_init_target, .examine = cortex_m3_examine, .quit = cortex_m3_quit }; +int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum) +{ + int retval; + u32 dcrdr; + + /* because the DCB_DCRDR is used for the emulated dcc channel + * we gave to save/restore the DCB_DCRDR when used */ + + mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ + dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum ); + + /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ + dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value ); + + mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); + retval = swjdp_transaction_endcheck(swjdp); + return retval; +} + +int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum) +{ + int retval; + u32 dcrdr; + + /* because the DCB_DCRDR is used for the emulated dcc channel + * we gave to save/restore the DCB_DCRDR when used */ + + mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + + swjdp->trans_mode = TRANS_MODE_COMPOSITE; + + /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ + dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value ); + + /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */ + dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR ); + + mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); + retval = swjdp_transaction_endcheck(swjdp); + return retval; +} + + +int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off) +{ + /* get pointers to arch-specific information */ + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + + /* mask off status bits */ + cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); + /* create new register mask */ + cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on; + + return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); +} + int cortex_m3_clear_halt(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - /* Read Debug Fault Status Register */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ - ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); - LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); - - return ERROR_OK; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + + /* clear step if any */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); + + /* Read Debug Fault Status Register */ + mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ + mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); + LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); + + return ERROR_OK; } int cortex_m3_single_step_core(target_t *target) @@ -118,13 +184,20 @@ int cortex_m3_single_step_core(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - + swjdp_common_t *swjdp = &armv7m->swjdp_info; + u32 dhcsr_save; + + /* backup dhcsr reg */ + dhcsr_save = cortex_m3->dcb_dhcsr; + + /* mask interrupts if not done already */ if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN ); - cortex_m3->dcb_dhcsr |= C_MASKINTS; + mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); + mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); LOG_DEBUG(" "); + + /* restore dhcsr reg */ + cortex_m3->dcb_dhcsr = dhcsr_save; cortex_m3_clear_halt(target); return ERROR_OK; @@ -134,17 +207,16 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; u32 savedram; int retvalue; - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - ahbap_write_system_u32(swjdp, 0x20000000, opcode); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); + mem_ap_read_u32(swjdp, 0x20000000, &savedram); + mem_ap_write_u32(swjdp, 0x20000000, opcode); + cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); + retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; } @@ -171,26 +243,32 @@ int cortex_m3_endreset_event(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; - ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr); - ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); + /* this regsiter is used for emulated dcc channel */ + mem_ap_write_u32(swjdp, DCB_DCRDR, 0); /* Enable debug requests */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + + /* clear any interrupt masking */ + cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS); + /* Enable trace and dwt */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR ); + mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); /* Monitor bus faults */ - ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA ); + mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA); /* Enable FPB */ target_write_u32(target, FP_CTRL, 3); + cortex_m3->fpb_enabled = 1; /* Restore FPB registers */ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) @@ -208,6 +286,10 @@ int cortex_m3_endreset_event(target_t *target) swjdp_transaction_endcheck(swjdp); armv7m_invalidate_core_regs(target); + + /* make sure we have latest dhcsr flags */ + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + return ERROR_OK; } @@ -244,36 +326,35 @@ int cortex_m3_examine_exception_reason(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; - ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr); + mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ - ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); if (except_sr & 0x40000000) { - ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr); + mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); } break; case 4: /* Memory Management */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); - ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar); + mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); break; case 5: /* Bus Fault */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); - ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar); + mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); break; case 6: /* Usage Fault */ - ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); + mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); break; case 11: /* SVCall */ break; case 12: /* Debug Monitor */ - ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr); + mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); break; case 14: /* PendSV */ break; @@ -284,8 +365,8 @@ int cortex_m3_examine_exception_reason(target_t *target) break; } swjdp_transaction_endcheck(swjdp); - LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ - shcsr, except_sr, cfsr, except_ar); + LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ + shcsr, except_sr, cfsr, except_ar); return ERROR_OK; } @@ -298,14 +379,14 @@ int cortex_m3_debug_entry(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; LOG_DEBUG(" "); if (armv7m->pre_debug_entry) armv7m->pre_debug_entry(target); cortex_m3_clear_halt(target); - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK) return retval; @@ -359,8 +440,10 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_examine_exception_reason(target); } - LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \ - *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); + LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", + armv7m_mode_strings[armv7m->core_mode], + *(u32*)(armv7m->core_cache->reg_list[15].value), + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (armv7m->post_debug_entry) armv7m->post_debug_entry(target); @@ -371,15 +454,15 @@ int cortex_m3_debug_entry(target_t *target) int cortex_m3_poll(target_t *target) { int retval; - u32 prev_target_state = target->state; + enum target_state prev_target_state = target->state; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; /* Read from Debug Halting Control and Status Register */ - retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) { target->state = TARGET_UNKNOWN; @@ -389,7 +472,7 @@ int cortex_m3_poll(target_t *target) if (cortex_m3->dcb_dhcsr & S_RESET_ST) { /* check if still in reset */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (cortex_m3->dcb_dhcsr & S_RESET_ST) { @@ -434,9 +517,9 @@ int cortex_m3_poll(target_t *target) */ #if 0 - /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); + /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ + mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); #endif return ERROR_OK; @@ -444,12 +527,8 @@ int cortex_m3_poll(target_t *target) int cortex_m3_halt(target_t *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name); if (target->state == TARGET_HALTED) { @@ -481,7 +560,7 @@ int cortex_m3_halt(target_t *target) } /* Write to Debug Halting Control and Status Register */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); + cortex_m3_write_debug_halt_mask(target, C_HALT, 0); target->debug_reason = DBG_REASON_DBGRQ; @@ -493,15 +572,15 @@ int cortex_m3_soft_reset_halt(struct target_s *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; u32 dcb_dhcsr = 0; int retval, timeout = 0; /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); /* Request a reset */ - ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET ); + mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET); target->state = TARGET_RESET; /* registers are now invalid */ @@ -509,10 +588,10 @@ int cortex_m3_soft_reset_halt(struct target_s *target) while (timeout < 100) { - retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { - ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); @@ -523,7 +602,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target) LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout); } timeout++; - usleep(1000); + alive_sleep(1); } return ERROR_OK; @@ -533,10 +612,8 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; breakpoint_t *breakpoint = NULL; - u32 dcb_dhcsr, resume_pc; + u32 resume_pc; if (target->state != TARGET_HALTED) { @@ -549,23 +626,23 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand target_free_all_working_areas(target); cortex_m3_enable_breakpoints(target); cortex_m3_enable_watchpoints(target); - - /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */ } - dcb_dhcsr = DBGKEY | C_DEBUGEN; if (debug_execution) { /* Disable interrupts */ - /* - We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, - This is probably the same inssue as Cortex-M3 Errata 377493: - C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. - */ + /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, + * This is probably the same issue as Cortex-M3 Errata 377493: + * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24)); + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } /* current = 1: continue on current pc, otherwise continue at
*/ @@ -592,13 +669,10 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand cortex_m3_set_breakpoint(target, breakpoint); } } - - /* Set/Clear C_MASKINTS in a separate operation */ - if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); /* Restart core */ - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); + cortex_m3_write_debug_halt_mask(target, 0, C_HALT); + target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ @@ -607,13 +681,13 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_DEBUG("target resumed at 0x%x",resume_pc); + LOG_DEBUG("target resumed at 0x%x", resume_pc); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_DEBUG("target debug resumed at 0x%x",resume_pc); + LOG_DEBUG("target debug resumed at 0x%x", resume_pc); } return ERROR_OK; @@ -625,7 +699,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; breakpoint_t *breakpoint = NULL; if (target->state != TARGET_HALTED) @@ -648,11 +722,10 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle armv7m_restore_context(target); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - - if (cortex_m3->dcb_dhcsr & C_MASKINTS) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN ); - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN); - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + + /* set step and clear halt */ + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); /* registers are now invalid */ armv7m_invalidate_core_regs(target); @@ -673,10 +746,11 @@ int cortex_m3_assert_reset(target_t *target) { armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; int assert_srst = 1; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -685,34 +759,38 @@ int cortex_m3_assert_reset(target_t *target) } /* Enable debug requests */ - ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); - ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); + mem_ap_write_u32(swjdp, DCB_DCRDR, 0 ); - if (target->reset_mode == RESET_RUN) + if (!target->reset_halt) { /* Set/Clear C_MASKINTS in a separate operation */ if (cortex_m3->dcb_dhcsr & C_MASKINTS) - ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); - + mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + + /* clear any debug flags before resuming */ cortex_m3_clear_halt(target); + + /* clear C_HALT in dhcsr reg */ + cortex_m3_write_debug_halt_mask(target, 0, C_HALT); /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); + mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); } else { /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); } /* following hack is to handle luminary reset * when srst is asserted the luminary device seesm to also clear the debug registers * which does not match the armv7 debug TRM */ - if (strcmp(cortex_m3->variant, "lm3s") == 0) + if (strcmp(target->variant, "lm3s") == 0) { /* get revision of lm3s target, only early silicon has this issue * Fury Rev B, DustDevil Rev B, Tempest all ok */ @@ -753,8 +831,15 @@ int cortex_m3_assert_reset(target_t *target) else { /* this causes the luminary device to reset using the watchdog */ - ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ ); + mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + + { + /* I do not know why this is necessary, but it fixes strange effects + * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + u32 tmp; + mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); + } } target->state = TARGET_RESET; @@ -762,12 +847,20 @@ int cortex_m3_assert_reset(target_t *target) armv7m_invalidate_core_regs(target); + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target))!=ERROR_OK) + return retval; + } + return ERROR_OK; } int cortex_m3_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -790,6 +883,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target) int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; int fp_num=0; u32 hilo; @@ -804,7 +898,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("breakpoint already set"); return ERROR_OK; } - + if (cortex_m3->auto_bp_type) { breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; @@ -826,13 +920,24 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1; target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value); + if (!cortex_m3->fpb_enabled) + { + LOG_DEBUG("FPB wasn't enabled, do it now"); + target_write_u32(target, FP_CTRL, 3); + } } else if (breakpoint->type == BKPT_SOFT) { u8 code[4]; buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); - target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code); + if((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK) + { + return retval; + } breakpoint->set = 0x11; /* Any nice value but 0 */ } @@ -841,6 +946,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { + int retval; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -869,11 +975,17 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } else { - target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); + if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + { + return retval; + } } } breakpoint->set = 0; @@ -1109,13 +1221,12 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ int retval; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) { /* read a normal core register */ - retval = ahbap_read_coreregister_u32(swjdp, value, num); + retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { @@ -1127,7 +1238,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ { /* read other registers */ - ahbap_read_coreregister_u32(swjdp, value, 20); + cortexm3_dap_read_coreregister_u32(swjdp, value, 20); switch (num) { @@ -1165,8 +1276,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -1181,7 +1291,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) { - retval = ahbap_write_coreregister_u32(swjdp, value, num); + retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { LOG_ERROR("JTAG failure %i", retval); @@ -1194,7 +1304,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty { /* write other registers */ - ahbap_read_coreregister_u32(swjdp, ®, 20); + cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); switch (num) { @@ -1215,7 +1325,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty break; } - ahbap_write_coreregister_u32(swjdp, reg, 20); + cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); LOG_DEBUG("write special reg %i value 0x%x ", num, value); } @@ -1231,8 +1341,7 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; /* sanitize arguments */ @@ -1244,13 +1353,13 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co switch (size) { case 4: - retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address); + retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); break; case 2: - retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address); + retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); break; case 1: - retval = ahbap_read_buf_u8(swjdp, buffer, count, address); + retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); break; default: LOG_ERROR("BUG: we shouldn't get here"); @@ -1264,8 +1373,7 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; int retval; /* sanitize arguments */ @@ -1275,13 +1383,13 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c switch (size) { case 4: - retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address); + retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); break; case 2: - retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address); + retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); break; case 1: - retval = ahbap_write_buf_u8(swjdp, buffer, count, address); + retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); break; default: LOG_ERROR("BUG: we shouldn't get here"); @@ -1307,7 +1415,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta return ERROR_OK; } -int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int cortex_m3_examine(struct target_s *target) { int retval; u32 cpuid, fpcr, dwtcr, ictr; @@ -1316,58 +1424,62 @@ int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; - target->type->examined = 1; - - if ((retval=ahbap_debugport_init(swjdp))!=ERROR_OK) - return retval; - - /* Read from Device Identification Registers */ - if ((retval=target_read_u32(target, CPUID, &cpuid))!=ERROR_OK) + if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) return retval; - if (((cpuid >> 4) & 0xc3f) == 0xc23) - LOG_DEBUG("CORTEX-M3 processor detected"); - LOG_DEBUG("cpuid: 0x%8.8x", cpuid); - - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); - } - - /* Setup FPB */ - target_read_u32(target, FP_CTRL, &fpcr); - cortex_m3->auto_bp_type = 1; - cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; - cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; - cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); - for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + if (!target->type->examined) { - cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; - cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; - } - LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + target->type->examined = 1; - /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list=calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + /* Read from Device Identification Registers */ + if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + return retval; + + if (((cpuid >> 4) & 0xc3f) == 0xc23) + LOG_DEBUG("CORTEX-M3 processor detected"); + LOG_DEBUG("cpuid: 0x%8.8x", cpuid); + + target_read_u32(target, NVIC_ICTR, &ictr); + cortex_m3->intlinesnum = (ictr & 0x1F) + 1; + cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); + for (i = 0; i < cortex_m3->intlinesnum; i++) + { + target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); + LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); + } + + /* Setup FPB */ + target_read_u32(target, FP_CTRL, &fpcr); + cortex_m3->auto_bp_type = 1; + cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */ + cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; + cortex_m3->fp_code_available = cortex_m3->fp_num_code; + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + cortex_m3->fpb_enabled = fpcr & 1; + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) + { + cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; + cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + } + LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + + /* Setup DWT */ + target_read_u32(target, DWT_CTRL, &dwtcr); + cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; + cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); + for (i = 0; i < cortex_m3->dwt_num_comp; i++) + { + cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; + } } return ERROR_OK; } -int cortex_m3_quit() +int cortex_m3_quit(void) { return ERROR_OK; @@ -1377,7 +1489,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl) { u16 dcrdr; - ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); + mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); *ctrl = (u8)dcrdr; *value = (u8)(dcrdr >> 8); @@ -1388,7 +1500,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl) if (dcrdr & (1 << 0)) { dcrdr = 0; - ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); + mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); } return ERROR_OK; @@ -1397,11 +1509,10 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl) int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer) { armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; u8 data; u8 ctrl; - int i; + u32 i; for (i = 0; i < (size * 4); i++) { @@ -1418,8 +1529,7 @@ int cortex_m3_handle_target_request(void *priv) if (!target->type->examined) return ERROR_OK; armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1451,19 +1561,19 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant) +int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) { armv7m_common_t *armv7m; armv7m = &cortex_m3->armv7m; /* prepare JTAG information for the new target */ - cortex_m3->jtag_info.chain_pos = chain_pos; + cortex_m3->jtag_info.tap = tap; cortex_m3->jtag_info.scann_size = 4; - cortex_m3->swjdp_info.dp_select_value = -1; - cortex_m3->swjdp_info.ap_csw_value = -1; - cortex_m3->swjdp_info.ap_tar_value = -1; - cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info; + armv7m->swjdp_info.dp_select_value = -1; + armv7m->swjdp_info.ap_csw_value = -1; + armv7m->swjdp_info.ap_tar_value = -1; + armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info; /* initialize arch-specific breakpoint handling */ @@ -1479,15 +1589,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in armv7m->pre_restore_context = NULL; armv7m->post_restore_context = NULL; - if (variant) - { - cortex_m3->variant = strdup(variant); - } - else - { - cortex_m3->variant = strdup(""); - } - armv7m_init_arch_info(target, armv7m); armv7m->arch_info = cortex_m3; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; @@ -1498,26 +1599,11 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in return ERROR_OK; } -/* target cortex_m3 */ -int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t)); - memset(cortex_m3, 0, sizeof(*cortex_m3)); - - if (argc < 4) - { - LOG_ERROR("'target cortex_m3' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; + cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); - cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant); + cortex_m3_init_arch_info(target, cortex_m3, target->tap); return ERROR_OK; } @@ -1525,8 +1611,46 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char int cortex_m3_register_commands(struct command_context_s *cmd_ctx) { int retval; + command_t *cortex_m3_cmd; retval = armv7m_register_commands(cmd_ctx); + cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands"); + register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']"); + return retval; } + +int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + + if (target->state != TARGET_HALTED) + { + command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + return ERROR_OK; + } + + if (argc > 0) + { + if (!strcmp(args[0], "on")) + { + cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0); + } + else if (!strcmp(args[0], "off")) + { + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } + else + { + command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']"); + } + } + + command_print(cmd_ctx, "cortex_m3 interrupt mask %s", + (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off"); + + return ERROR_OK; +}