X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=35ca5a5c125f4359872dc27053725020db30c135;hp=ae714462e3693d647a66f22c9f36bae40f0bda09;hb=aa7c449600d6f6d634f587de6091421a1a877af5;hpb=f96d6054e65708e7abdceac673f1a18fec3204b6 diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index ae714462e3..35ca5a5c12 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -31,6 +31,7 @@ #include "config.h" #endif +#include "breakpoints.h" #include "cortex_m3.h" #include "target_request.h" #include "target_type.h" @@ -45,15 +46,15 @@ /* forward declarations */ -static int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -static void cortex_m3_enable_watchpoints(struct target_s *target); -static int cortex_m3_store_core_reg_u32(target_t *target, +static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); +static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +static void cortex_m3_enable_watchpoints(struct target *target); +static int cortex_m3_store_core_reg_u32(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value); #ifdef ARMV7_GDB_HACKS extern uint8_t armv7m_gdb_dummy_cpsr_value[]; -extern reg_t armv7m_gdb_dummy_cpsr_reg; +extern struct reg armv7m_gdb_dummy_cpsr_reg; #endif static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, @@ -118,10 +119,10 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp, return retval; } -static int cortex_m3_write_debug_halt_mask(target_t *target, +static int cortex_m3_write_debug_halt_mask(struct target *target, uint32_t mask_on, uint32_t mask_off) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; /* mask off status bits */ @@ -132,9 +133,9 @@ static int cortex_m3_write_debug_halt_mask(target_t *target, return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); } -static int cortex_m3_clear_halt(target_t *target) +static int cortex_m3_clear_halt(struct target *target) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; /* clear step if any */ @@ -149,9 +150,9 @@ static int cortex_m3_clear_halt(target_t *target) return ERROR_OK; } -static int cortex_m3_single_step_core(target_t *target) +static int cortex_m3_single_step_core(struct target *target) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dhcsr_save; @@ -171,14 +172,14 @@ static int cortex_m3_single_step_core(target_t *target) return ERROR_OK; } -static int cortex_m3_endreset_event(target_t *target) +static int cortex_m3_endreset_event(struct target *target) { int i; uint32_t dcb_demcr; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; - cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; - cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; + struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; + struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr); @@ -229,9 +230,9 @@ static int cortex_m3_endreset_event(target_t *target) return ERROR_OK; } -static int cortex_m3_examine_debug_reason(target_t *target) +static int cortex_m3_examine_debug_reason(struct target *target) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ @@ -256,10 +257,10 @@ static int cortex_m3_examine_debug_reason(target_t *target) return ERROR_OK; } -static int cortex_m3_examine_exception_reason(target_t *target) +static int cortex_m3_examine_exception_reason(struct target *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); @@ -304,13 +305,13 @@ static int cortex_m3_examine_exception_reason(target_t *target) return ERROR_OK; } -static int cortex_m3_debug_entry(target_t *target) +static int cortex_m3_debug_entry(struct target *target) { int i; uint32_t xPSR; int retval; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - struct armv7m_common_s *armv7m = &cortex_m3->armv7m; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; struct swjdp_common *swjdp = &armv7m->swjdp_info; LOG_DEBUG(" "); @@ -376,11 +377,11 @@ static int cortex_m3_debug_entry(target_t *target) return ERROR_OK; } -static int cortex_m3_poll(target_t *target) +static int cortex_m3_poll(struct target *target) { int retval; enum target_state prev_target_state = target->state; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; /* Read from Debug Halting Control and Status Register */ @@ -450,7 +451,7 @@ static int cortex_m3_poll(target_t *target) return ERROR_OK; } -static int cortex_m3_halt(target_t *target) +static int cortex_m3_halt(struct target *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -492,9 +493,9 @@ static int cortex_m3_halt(target_t *target) return ERROR_OK; } -static int cortex_m3_soft_reset_halt(struct target_s *target) +static int cortex_m3_soft_reset_halt(struct target *target) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; @@ -531,9 +532,9 @@ static int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } -static void cortex_m3_enable_breakpoints(struct target_s *target) +static void cortex_m3_enable_breakpoints(struct target *target) { - breakpoint_t *breakpoint = target->breakpoints; + struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ while (breakpoint) @@ -544,11 +545,11 @@ static void cortex_m3_enable_breakpoints(struct target_s *target) } } -static int cortex_m3_resume(struct target_s *target, int current, +static int cortex_m3_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - struct armv7m_common_s *armv7m = target_to_armv7m(target); - breakpoint_t *breakpoint = NULL; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct breakpoint *breakpoint = NULL; uint32_t resume_pc; if (target->state != TARGET_HALTED) @@ -632,13 +633,13 @@ static int cortex_m3_resume(struct target_s *target, int current, } /* int irqstepcount = 0; */ -static int cortex_m3_step(struct target_s *target, int current, +static int cortex_m3_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - struct armv7m_common_s *armv7m = &cortex_m3->armv7m; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; struct swjdp_common *swjdp = &armv7m->swjdp_info; - breakpoint_t *breakpoint = NULL; + struct breakpoint *breakpoint = NULL; if (target->state != TARGET_HALTED) { @@ -684,9 +685,9 @@ static int cortex_m3_step(struct target_s *target, int current, return ERROR_OK; } -static int cortex_m3_assert_reset(target_t *target) +static int cortex_m3_assert_reset(struct target *target) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; int assert_srst = 1; @@ -821,7 +822,7 @@ static int cortex_m3_assert_reset(target_t *target) return ERROR_OK; } -static int cortex_m3_deassert_reset(target_t *target) +static int cortex_m3_deassert_reset(struct target *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -833,13 +834,13 @@ static int cortex_m3_deassert_reset(target_t *target) } static int -cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; int fp_num = 0; uint32_t hilo; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - cortex_m3_fp_comparator_t *comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list; if (breakpoint->set) { @@ -900,11 +901,11 @@ cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } static int -cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list; if (!breakpoint->set) { @@ -955,9 +956,9 @@ cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } static int -cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); if (cortex_m3->auto_bp_type) { @@ -1004,9 +1005,9 @@ cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } static int -cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1032,11 +1033,11 @@ cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } static int -cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int dwt_num = 0; uint32_t mask, temp; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* watchpoint params were validated earlier */ mask = 0; @@ -1052,7 +1053,7 @@ cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * watchpoint using comparator #1; comparator #0 matching cycle * count; send data trace info through ITM and TPIU; etc */ - cortex_m3_dwt_comparator_t *comparator; + struct cortex_m3_dwt_comparator *comparator; for (comparator = cortex_m3->dwt_comparator_list; comparator->used && dwt_num < cortex_m3->dwt_num_comp; @@ -1097,10 +1098,10 @@ cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } static int -cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - cortex_m3_dwt_comparator_t *comparator; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_dwt_comparator *comparator; int dwt_num; if (!watchpoint->set) @@ -1134,9 +1135,9 @@ cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } static int -cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1192,9 +1193,9 @@ cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) } static int -cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) @@ -1214,9 +1215,9 @@ cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -static void cortex_m3_enable_watchpoints(struct target_s *target) +static void cortex_m3_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ while (watchpoint) @@ -1227,11 +1228,11 @@ static void cortex_m3_enable_watchpoints(struct target_s *target) } } -static int cortex_m3_load_core_reg_u32(struct target_s *target, +static int cortex_m3_load_core_reg_u32(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; /* NOTE: we "know" here that the register identifiers used @@ -1290,12 +1291,12 @@ static int cortex_m3_load_core_reg_u32(struct target_s *target, return ERROR_OK; } -static int cortex_m3_store_core_reg_u32(struct target_s *target, +static int cortex_m3_store_core_reg_u32(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; uint32_t reg; - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; #ifdef ARMV7_GDB_HACKS @@ -1367,10 +1368,10 @@ static int cortex_m3_store_core_reg_u32(struct target_s *target, return ERROR_OK; } -static int cortex_m3_read_memory(struct target_s *target, uint32_t address, +static int cortex_m3_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; int retval; @@ -1399,10 +1400,10 @@ static int cortex_m3_read_memory(struct target_s *target, uint32_t address, return retval; } -static int cortex_m3_write_memory(struct target_s *target, uint32_t address, +static int cortex_m3_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; int retval; @@ -1429,14 +1430,14 @@ static int cortex_m3_write_memory(struct target_s *target, uint32_t address, return retval; } -static int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, +static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } -static int cortex_m3_init_target(struct command_context_s *cmd_ctx, - struct target_s *target) +static int cortex_m3_init_target(struct command_context *cmd_ctx, + struct target *target) { armv7m_build_reg_cache(target); return ERROR_OK; @@ -1448,19 +1449,19 @@ static int cortex_m3_init_target(struct command_context_s *cmd_ctx, */ struct dwt_reg_state { - struct target_s *target; + struct target *target; uint32_t addr; uint32_t value; /* scratch/cache */ }; -static int cortex_m3_dwt_get_reg(struct reg_s *reg) +static int cortex_m3_dwt_get_reg(struct reg *reg) { struct dwt_reg_state *state = reg->arch_info; return target_read_u32(state->target, state->addr, &state->value); } -static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf) +static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf) { struct dwt_reg_state *state = reg->arch_info; @@ -1495,7 +1496,7 @@ static struct dwt_reg dwt_comp[] = { static int dwt_reg_type = -1; static void -cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d) +cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) { struct dwt_reg_state *state; @@ -1513,11 +1514,11 @@ cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d) } static void -cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target) +cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target) { uint32_t dwtcr; - struct reg_cache_s *cache; - cortex_m3_dwt_comparator_t *comparator; + struct reg_cache *cache; + struct cortex_m3_dwt_comparator *comparator; int reg, i; target_read_u32(target, DWT_CTRL, &dwtcr); @@ -1533,7 +1534,7 @@ cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target) cm3->dwt_num_comp = (dwtcr >> 28) & 0xF; cm3->dwt_comp_available = cm3->dwt_num_comp; cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp, - sizeof(cortex_m3_dwt_comparator_t)); + sizeof(struct cortex_m3_dwt_comparator)); if (!cm3->dwt_comparator_list) { fail0: cm3->dwt_num_comp = 0; @@ -1582,12 +1583,12 @@ fail1: */ } -static int cortex_m3_examine(struct target_s *target) +static int cortex_m3_examine(struct target *target) { int retval; uint32_t cpuid, fpcr; int i; - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) @@ -1614,7 +1615,7 @@ static int cortex_m3_examine(struct target_s *target) cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */ cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator)); cortex_m3->fpb_enabled = fpcr & 1; for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { @@ -1651,10 +1652,10 @@ static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_ return ERROR_OK; } -static int cortex_m3_target_request_data(target_t *target, +static int cortex_m3_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; uint8_t data; uint8_t ctrl; @@ -1671,10 +1672,10 @@ static int cortex_m3_target_request_data(target_t *target, static int cortex_m3_handle_target_request(void *priv) { - target_t *target = priv; + struct target *target = priv; if (!target_was_examined(target)) return ERROR_OK; - struct armv7m_common_s *armv7m = target_to_armv7m(target); + struct armv7m_common *armv7m = target_to_armv7m(target); struct swjdp_common *swjdp = &armv7m->swjdp_info; if (!target->dbg_msg_enabled) @@ -1707,11 +1708,11 @@ static int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -static int cortex_m3_init_arch_info(target_t *target, - cortex_m3_common_t *cortex_m3, struct jtag_tap *tap) +static int cortex_m3_init_arch_info(struct target *target, + struct cortex_m3_common *cortex_m3, struct jtag_tap *tap) { int retval; - struct armv7m_common_s *armv7m = &cortex_m3->armv7m; + struct armv7m_common *armv7m = &cortex_m3->armv7m; armv7m_init_arch_info(target, armv7m); @@ -1747,9 +1748,9 @@ static int cortex_m3_init_arch_info(target_t *target, return ERROR_OK; } -static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_m3_target_create(struct target *target, Jim_Interp *interp) { - cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); + struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common)); cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; cortex_m3_init_arch_info(target, cortex_m3, target->tap); @@ -1759,8 +1760,8 @@ static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) /*--------------------------------------------------------------------------*/ -static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx, - struct cortex_m3_common_s *cm3) +static int cortex_m3_verify_pointer(struct command_context *cmd_ctx, + struct cortex_m3_common *cm3) { if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { command_print(cmd_ctx, "target is not a Cortex-M3"); @@ -1784,11 +1785,11 @@ static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx, COMMAND_HANDLER(handle_cortex_m3_disassemble_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct target *target = get_current_target(cmd_ctx); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); uint32_t address; unsigned long count = 1; - arm_instruction_t cur_instruction; + struct arm_instruction cur_instruction; retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); if (retval != ERROR_OK) @@ -1835,9 +1836,9 @@ static const struct { COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { - target_t *target = get_current_target(cmd_ctx); - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); - struct armv7m_common_s *armv7m = &cortex_m3->armv7m; + struct target *target = get_current_target(cmd_ctx); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; struct swjdp_common *swjdp = &armv7m->swjdp_info; uint32_t demcr = 0; int retval; @@ -1892,8 +1893,8 @@ write: COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) { - target_t *target = get_current_target(cmd_ctx); - struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); + struct target *target = get_current_target(cmd_ctx); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); int retval; retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); @@ -1928,10 +1929,10 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) return ERROR_OK; } -static int cortex_m3_register_commands(struct command_context_s *cmd_ctx) +static int cortex_m3_register_commands(struct command_context *cmd_ctx) { int retval; - command_t *cortex_m3_cmd; + struct command *cortex_m3_cmd; retval = armv7m_register_commands(cmd_ctx); @@ -1951,7 +1952,7 @@ static int cortex_m3_register_commands(struct command_context_s *cmd_ctx) return retval; } -target_type_t cortexm3_target = +struct target_type cortexm3_target = { .name = "cortex_m3",