X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=279d986a6b9b049df9b4f584b5240be6671d059a;hp=93521cf6e6936f5d3c20ab38deac4ee2d102ad83;hb=68b97e4b5c40a70b42dc2a970f1b90b9a3e9f13d;hpb=09883194f86725f4eae7e6db9eabcf6b3d1511de diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 93521cf6e6..279d986a6b 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -23,14 +23,14 @@ #include "config.h" #endif -#define USE_SP_REGS - #include "replacements.h" #include "cortex_m3.h" +#include "armv7m.h" #include "register.h" #include "target.h" +#include "target_request.h" #include "log.h" #include "jtag.h" #include "arm_jtag.h" @@ -51,7 +51,8 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta int cortex_m3_quit(); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); - +int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); + target_type_t cortexm3_target = { .name = "cortex_m3", @@ -59,6 +60,8 @@ target_type_t cortexm3_target = .poll = cortex_m3_poll, .arch_state = armv7m_arch_state, + .target_request_data = cortex_m3_target_request_data, + .halt = cortex_m3_halt, .resume = cortex_m3_resume, .step = cortex_m3_step, @@ -66,13 +69,15 @@ target_type_t cortexm3_target = .assert_reset = cortex_m3_assert_reset, .deassert_reset = cortex_m3_deassert_reset, .soft_reset_halt = cortex_m3_soft_reset_halt, - + .prepare_reset_halt = cortex_m3_prepare_reset_halt, + .get_gdb_reg_list = armv7m_get_gdb_reg_list, .read_memory = cortex_m3_read_memory, .write_memory = cortex_m3_write_memory, .bulk_write_memory = cortex_m3_bulk_write_memory, - + .checksum_memory = armv7m_checksum_memory, + .run_algorithm = armv7m_run_algorithm, .add_breakpoint = cortex_m3_add_breakpoint, @@ -88,7 +93,6 @@ target_type_t cortexm3_target = int cortex_m3_clear_halt(target_t *target) { - /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -98,7 +102,7 @@ int cortex_m3_clear_halt(target_t *target) ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */ ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); - DEBUG(" NVIC_DFSR 0x%x",cortex_m3->nvic_dfsr); + DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr); return ERROR_OK; } @@ -110,11 +114,11 @@ int cortex_m3_single_step_core(target_t *target) cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - if (!(cortex_m3->dcb_dhcsr&C_MASKINTS)) + if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN ); ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN ); cortex_m3->dcb_dhcsr |= C_MASKINTS; - DEBUG(""); + DEBUG(" "); cortex_m3_clear_halt(target); return ERROR_OK; @@ -128,15 +132,13 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval swjdp_common_t *swjdp = &cortex_m3->swjdp_info; u32 savedram; int retvalue; - - { - ahbap_read_system_u32(swjdp, 0x20000000, &savedram); - ahbap_write_system_u32(swjdp, 0x20000000, opcode); - ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty=1; - retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); - } + + ahbap_read_system_u32(swjdp, 0x20000000, &savedram); + ahbap_write_system_u32(swjdp, 0x20000000, opcode); + ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); + cortex_m3_single_step_core(target); + armv7m->core_cache->reg_list[15].dirty = 1; + retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram); return retvalue; } @@ -156,21 +158,26 @@ int cortex_m3_cpsid(target_t *target, u32 IF) int cortex_m3_endreset_event(target_t *target) { int i; + u32 dcb_demcr; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; - cortex_m3_dwt_comparator_t * dwt_list = cortex_m3->dwt_comparator_list; + cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; - DEBUG(""); + ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr); + + ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); + /* Enable debug requests */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (!(cortex_m3->dcb_dhcsr&C_DEBUGEN)) + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); /* Enable trace and dwt */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA|VC_HARDERR|VC_BUSERR|VC_CORERESET ); + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR ); /* Monitor bus faults */ ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA ); @@ -178,18 +185,19 @@ int cortex_m3_endreset_event(target_t *target) target_write_u32(target, FP_CTRL, 3); /* Restore FPB registers */ - for (i=0;ifp_num_code+cortex_m3->fp_num_lit;i++) + for ( i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); } /* Restore DWT registers */ - for (i=0;idwt_num_comp;i++) + for ( i = 0; i < cortex_m3->dwt_num_comp; i++) { target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp); - target_write_u32(target, dwt_list[i].dwt_comparator_address|0x4, dwt_list[i].mask); - target_write_u32(target, dwt_list[i].dwt_comparator_address|0x8, dwt_list[i].function); + target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); + target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); } + swjdp_transaction_endcheck(swjdp); /* Make sure working_areas are all free */ target_free_all_working_areas(target); @@ -205,24 +213,22 @@ int cortex_m3_examine_debug_reason(target_t *target) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &cortex_m3->swjdp_info; -/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ + /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { + /* INCOMPLETE */ - /* INCOPMPLETE */ - - if (cortex_m3->nvic_dfsr & 0x2) + if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; - if (cortex_m3->nvic_dfsr & 0x4) + if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WPTANDBKPT; } - else if (cortex_m3->nvic_dfsr & 0x4) + else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; } @@ -231,7 +237,7 @@ int cortex_m3_examine_debug_reason(target_t *target) int cortex_m3_examine_exception_reason(target_t *target) { - u32 shcsr,except_sr,cfsr=-1,except_ar=-1; + u32 shcsr, except_sr, cfsr = -1, except_ar = -1; /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -245,7 +251,7 @@ int cortex_m3_examine_exception_reason(target_t *target) break; case 3: /* Hard Fault */ ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr); - if (except_sr&0x40000000) + if (except_sr & 0x40000000) { ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr); } @@ -262,31 +268,27 @@ int cortex_m3_examine_exception_reason(target_t *target) ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr); break; case 11: /* SVCall */ - break; case 12: /* Debug Monitor */ ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr); break; case 14: /* PendSV */ - break; case 15: /* SysTick */ - break; default: except_sr = 0; break; - } swjdp_transaction_endcheck(swjdp); - DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x",armv7m_exception_string(armv7m->exception_number),shcsr,except_sr,cfsr, except_ar); + DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \ + shcsr, except_sr, cfsr, except_ar); return ERROR_OK; } - int cortex_m3_debug_entry(target_t *target) { - int i, irq_is_pending; + int i; u32 xPSR; int retval; @@ -295,7 +297,7 @@ int cortex_m3_debug_entry(target_t *target) cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - DEBUG(""); + DEBUG(" "); if (armv7m->pre_debug_entry) armv7m->pre_debug_entry(target); @@ -316,31 +318,29 @@ int cortex_m3_debug_entry(target_t *target) xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32); /* For IT instructions xPSR must be reloaded on resume and clear on debug exec*/ - if (xPSR&0xf00) + if (xPSR & 0xf00) { armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; - cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR&~0xff); + cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } /* Now we can load SP core registers */ -#ifdef USE_SP_REGS for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); } -#endif /* Are we in an exception handler */ - armv7m->core_mode = (xPSR&0x1FF)?ARMV7M_MODE_HANDLER:ARMV7M_MODE_THREAD; - armv7m->exception_number = xPSR&0x1FF;; + armv7m->core_mode = (xPSR & 0x1FF) ? ARMV7M_MODE_HANDLER : ARMV7M_MODE_THREAD; + armv7m->exception_number = xPSR & 0x1FF; if (armv7m->exception_number) { cortex_m3_examine_exception_reason(target); } - DEBUG("entered debug state at PC 0x%x ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); + DEBUG("entered debug state at PC 0x%x, target->state: %s ", *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]); if (armv7m->post_debug_entry) armv7m->post_debug_entry(target); @@ -348,38 +348,6 @@ int cortex_m3_debug_entry(target_t *target) return ERROR_OK; } -int cortex_m3_restore_context(target_t *target) -{ - int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - DEBUG(""); - - if (armv7m->pre_restore_context) - armv7m->pre_restore_context(target); - -#ifdef USE_SP_REGS - for (i = ARMV7NUMCOREREGS; i >= 0; i--) -#else - for (i = ARMV7M_PSP; i >= 0; i--) -#endif - { - if (armv7m->core_cache->reg_list[i].dirty) - { - armv7m->write_core_reg(target, i); - } - } - - if (armv7m->post_restore_context) - armv7m->post_restore_context(target); - - return ERROR_OK; -} - - enum target_state cortex_m3_poll(target_t *target) { int retval; @@ -398,51 +366,56 @@ enum target_state cortex_m3_poll(target_t *target) return TARGET_UNKNOWN; } - if (cortex_m3->dcb_dhcsr&S_RESET_ST) + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { - target->state = TARGET_RESET; - return target->state; + /* check if still in reset */ + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + + if (cortex_m3->dcb_dhcsr & S_RESET_ST) + { + target->state = TARGET_RESET; + return target->state; + } } - else if (target->state==TARGET_RESET) + + if (target->state == TARGET_RESET) { /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */ - DEBUG("Exit from reset with dcb_dhcsr %x", cortex_m3->dcb_dhcsr); + DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr); cortex_m3_endreset_event(target); target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; } - if (cortex_m3->dcb_dhcsr&S_HALT) + if (cortex_m3->dcb_dhcsr & S_HALT) { target->state = TARGET_HALTED; if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) { if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return retval; + return TARGET_UNKNOWN; target_call_event_callbacks(target, TARGET_EVENT_HALTED); } if (prev_target_state == TARGET_DEBUG_RUNNING) { - DEBUG(""); + DEBUG(" "); if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) - return retval; + return TARGET_UNKNOWN; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - } /* - if (cortex_m3->dcb_dhcsr&S_SLEEP) + if (cortex_m3->dcb_dhcsr & S_SLEEP) target->state = TARGET_SLEEP; */ - /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */ ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - DEBUG("dcb_dhcsr %x, nvic_dfsr %x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); + DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]); return target->state; } @@ -455,6 +428,35 @@ int cortex_m3_halt(target_t *target) DEBUG("target->state: %s", target_state_strings[target->state]); + if (target->state == TARGET_HALTED) + { + WARNING("target was already halted"); + return ERROR_TARGET_ALREADY_HALTED; + } + + if (target->state == TARGET_UNKNOWN) + { + WARNING("target was in unknown state when halt was requested"); + } + + if (target->state == TARGET_RESET) + { + if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) + { + ERROR("can't request a halt while in reset if nSRST pulls nTRST"); + return ERROR_TARGET_FAILURE; + } + else + { + /* we came here in a reset_halt or reset_init sequence + * debug entry was already prepared in cortex_m3_prepare_reset_halt() + */ + target->debug_reason = DBG_REASON_DBGRQ; + + return ERROR_OK; + } + } + /* Write to Debug Halting Control and Status Register */ ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); @@ -469,8 +471,8 @@ int cortex_m3_soft_reset_halt(struct target_s *target) armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; swjdp_common_t *swjdp = &cortex_m3->swjdp_info; - u32 dcb_dhcsr=0; - int retval, timeout=0; + u32 dcb_dhcsr = 0; + int retval, timeout = 0; /* Check that we are using process_context, or change and print warning */ if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT) @@ -480,7 +482,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target) } /* Enter debug state on reset, cf. end_reset_event() */ - ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA|VC_HARDERR|VC_BUSERR|VC_CORERESET ); + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); /* Request a reset */ ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET ); @@ -489,20 +491,20 @@ int cortex_m3_soft_reset_halt(struct target_s *target) /* registers are now invalid */ armv7m_invalidate_core_regs(target); - while (timeout<100) + while (timeout < 100) { retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - if ( (dcb_dhcsr&S_HALT)&&(cortex_m3->nvic_dfsr&DFSR_VCATCH) ) + if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { - DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x",dcb_dhcsr,cortex_m3->nvic_dfsr); + DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr); cortex_m3_poll(target); return ERROR_OK; } else - DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms",dcb_dhcsr,timeout); + DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout); } timeout++; usleep(1000); @@ -511,6 +513,28 @@ int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } +int cortex_m3_prepare_reset_halt(struct target_s *target) +{ + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + u32 dcb_demcr, dcb_dhcsr; + + /* Enable debug requests */ + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) + ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + + /* Enter debug state on reset, cf. end_reset_event() */ + ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET ); + + ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); + ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr); + + return ERROR_OK; +} + int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) { /* get pointers to arch-specific information */ @@ -534,14 +558,12 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand WARNING("Incorrect context in resume"); armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT); } - - + target_free_all_working_areas(target); cortex_m3_enable_breakpoints(target); cortex_m3_enable_watchpoints(target); /* TODOLATER Interrupt handling/disable for debug execution, cache ... ... */ - } dcb_dhcsr = DBGKEY | C_DEBUGEN; @@ -562,7 +584,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32)|(1<<24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24)); } /* current = 1: continue on current pc, otherwise continue at
*/ @@ -575,7 +597,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32); - cortex_m3_restore_context(target); + armv7m_restore_context(target); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) @@ -591,8 +613,9 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand } /* Set/Clear C_MASKINTS in a separate operation */ - if ((cortex_m3->dcb_dhcsr&C_MASKINTS) != (dcb_dhcsr&C_MASKINTS)) + if ((cortex_m3->dcb_dhcsr & C_MASKINTS) != (dcb_dhcsr & C_MASKINTS)) ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr | C_HALT ); + /* Restart core */ ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, dcb_dhcsr ); target->debug_reason = DBG_REASON_NOTHALTED; @@ -612,11 +635,10 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand DEBUG("target debug resumed at 0x%x",resume_pc); } - return ERROR_OK; } -int irqstepcount=0; +//int irqstepcount=0; int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints) { /* get pointers to arch-specific information */ @@ -649,11 +671,11 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle target->debug_reason = DBG_REASON_SINGLESTEP; - cortex_m3_restore_context(target); + armv7m_restore_context(target); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - if (cortex_m3->dcb_dhcsr&C_MASKINTS) + if (cortex_m3->dcb_dhcsr & C_MASKINTS) ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN ); ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY| C_STEP | C_DEBUGEN); ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -665,22 +687,39 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); - DEBUG("target stepped dcb_dhcsr=0x%x nvic_icsr=0x%x",cortex_m3->dcb_dhcsr,cortex_m3->nvic_icsr); + DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); cortex_m3_debug_entry(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); - DEBUG("target stepped dcb_dhcsr=0x%x nvic_icsr=0x%x",cortex_m3->dcb_dhcsr,cortex_m3->nvic_icsr); + DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); return ERROR_OK; - } int cortex_m3_assert_reset(target_t *target) { int retval; + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; DEBUG("target->state: %s", target_state_strings[target->state]); + ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 ); + + if (target->reset_mode == RESET_RUN) + { + /* Set/Clear C_MASKINTS in a separate operation */ + if (cortex_m3->dcb_dhcsr & C_MASKINTS) + ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT ); + + cortex_m3_clear_halt(target); + + /* Enter debug state on reset, cf. end_reset_event() */ + ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN ); + ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); + } + if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) { /* assert SRST and TRST */ @@ -738,24 +777,23 @@ int cortex_m3_assert_reset(target_t *target) armv7m_invalidate_core_regs(target); return ERROR_OK; - } int cortex_m3_deassert_reset(target_t *target) -{ +{ DEBUG("target->state: %s", target_state_strings[target->state]); /* deassert reset lines */ jtag_add_reset(0, 0); return ERROR_OK; - } void cortex_m3_unset_all_breakpoints_and_watchpoints(struct target_s *target) { } + void cortex_m3_enable_breakpoints(struct target_s *target) { breakpoint_t *breakpoint = target->breakpoints; @@ -788,37 +826,36 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address<0x20000000)?BKPT_HARD:BKPT_SOFT; + breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; } if (breakpoint->type == BKPT_HARD) { - while(comparator_list[fp_num].used && (fp_numfp_num_code)) + while(comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code)) fp_num++; - if (fp_num>=cortex_m3->fp_num_code) + if (fp_num >= cortex_m3->fp_num_code) { DEBUG("ERROR Can not find free FP Comparator"); WARNING("ERROR Can not find free FP Comparator"); exit(-1); } - breakpoint->set = fp_num+1; - hilo = (breakpoint->address & 0x2)? FPCR_REPLACE_BKPT_HIGH:FPCR_REPLACE_BKPT_LOW; + breakpoint->set = fp_num + 1; + hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW; comparator_list[fp_num].used = 1; - comparator_list[fp_num].fpcr_value = breakpoint->address&0x1FFFFFFC | hilo | 1; + comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1; target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); - DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value); + DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value); } else if (breakpoint->type == BKPT_SOFT) { u8 code[4]; buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); - target->type->read_memory(target, breakpoint->address&0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); - target->type->write_memory(target, breakpoint->address&0xFFFFFFFE, breakpoint->length, 1, code); + target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); + target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code); breakpoint->set = 0x11; /* Any nice value but 0 */ } return ERROR_OK; - } int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) @@ -836,8 +873,8 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint if (breakpoint->type == BKPT_HARD) { - int fp_num = breakpoint->set-1; - if ((fp_num<0)||(fp_num>=cortex_m3->fp_num_code)) + int fp_num = breakpoint->set - 1; + if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) { DEBUG("Invalid FP Comparator number in breakpoint"); return ERROR_OK; @@ -851,11 +888,11 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - target->type->write_memory(target, breakpoint->address&0xFFFFFFFE, 4, 1, breakpoint->orig_instr); + target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); } else { - target->type->write_memory(target, breakpoint->address&0xFFFFFFFE, 2, 1, breakpoint->orig_instr); + target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); } } breakpoint->set = 0; @@ -863,7 +900,6 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } - int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { /* get pointers to arch-specific information */ @@ -872,16 +908,16 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address<0x20000000)?BKPT_HARD:BKPT_SOFT; + breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; } - if ((breakpoint->type == BKPT_HARD) && (breakpoint->address>=0x20000000)) + if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000)) { INFO("flash patch comparator requested outside code memory region"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address<0x20000000)) + if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000)) { INFO("soft breakpoint requested in code (flash) memory region"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -920,7 +956,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin if (cortex_m3->auto_bp_type) { - breakpoint->type = (breakpoint->address<0x20000000)?BKPT_HARD:BKPT_SOFT; + breakpoint->type = (breakpoint->address < 0x20000000) ? BKPT_HARD : BKPT_SOFT; } if (breakpoint->set) @@ -934,19 +970,6 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin return ERROR_OK; } -void cortex_m3_enable_watchpoints(struct target_s *target) -{ - watchpoint_t *watchpoint = target->watchpoints; - - /* set any pending watchpoints */ - while (watchpoint) - { - if (watchpoint->set == 0) - cortex_m3_set_watchpoint(target, watchpoint); - watchpoint = watchpoint->next; - } -} - int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int dwt_num=0; @@ -965,30 +988,30 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (watchpoint->mask == 0xffffffffu) { - while(comparator_list[dwt_num].used && (dwt_numdwt_num_comp)) + while(comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp)) dwt_num++; - if (dwt_num>=cortex_m3->dwt_num_comp) + if (dwt_num >= cortex_m3->dwt_num_comp) { DEBUG("ERROR Can not find free DWT Comparator"); WARNING("ERROR Can not find free DWT Comparator"); return -1; } - watchpoint->set = dwt_num+1; + watchpoint->set = dwt_num + 1; mask = 0; temp = watchpoint->length; - while (temp>1) + while (temp > 1) { - temp = temp/2; + temp = temp / 2; mask++; } comparator_list[dwt_num].used = 1; comparator_list[dwt_num].comp = watchpoint->address; comparator_list[dwt_num].mask = mask; - comparator_list[dwt_num].function = watchpoint->rw+5; + comparator_list[dwt_num].function = watchpoint->rw + 5; target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp); target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask); target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function); - DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); + DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); } else { @@ -1014,9 +1037,9 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint return ERROR_OK; } - dwt_num = watchpoint->set-1; + dwt_num = watchpoint->set - 1; - if ((dwt_num<0)||(dwt_num>=cortex_m3->dwt_num_comp)) + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; @@ -1030,8 +1053,6 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint return ERROR_OK; } - - int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { /* get pointers to arch-specific information */ @@ -1081,6 +1102,18 @@ int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoin return ERROR_OK; } +void cortex_m3_enable_watchpoints(struct target_s *target) +{ + watchpoint_t *watchpoint = target->watchpoints; + + /* set any pending watchpoints */ + while (watchpoint) + { + if (watchpoint->set == 0) + cortex_m3_set_watchpoint(target, watchpoint); + watchpoint = watchpoint->next; + } +} int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 * value) { @@ -1116,16 +1149,15 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_read_coreregister_u32(swjdp, value, 0); - armv7m->core_cache->reg_list[0].dirty=1; - armv7m->core_cache->reg_list[15].dirty=1; + armv7m->core_cache->reg_list[0].dirty = 1; + armv7m->core_cache->reg_list[15].dirty = 1; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); - DEBUG("load from special reg %i value 0x%x",SYSm, *value); + DEBUG("load from special reg %i value 0x%x", SYSm, *value); } else return ERROR_INVALID_ARGUMENTS; return ERROR_OK; - } int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value) @@ -1142,11 +1174,11 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty retval = ahbap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { - ERROR("JTAG failure %i",retval); - armv7m->core_cache->reg_list[num].dirty=1; + ERROR("JTAG failure %i", retval); + armv7m->core_cache->reg_list[num].dirty = 1; return ERROR_JTAG_DEVICE_ERROR; } - DEBUG("write core reg %i value 0x%x",num, value); + DEBUG("write core reg %i value 0x%x", num, value); } else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ { @@ -1163,21 +1195,18 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty ahbap_write_coreregister_u32(swjdp, 0x20000000, 15); cortex_m3_single_step_core(target); ahbap_write_coreregister_u32(swjdp, tempr0, 0); - armv7m->core_cache->reg_list[15].dirty=1; + armv7m->core_cache->reg_list[15].dirty = 1; ahbap_write_system_u32(swjdp, 0x20000000, savedram); swjdp_transaction_endcheck(swjdp); - DEBUG("write special reg %i value 0x%x ",SYSm, value); + DEBUG("write special reg %i value 0x%x ", SYSm, value); } else return ERROR_INVALID_ARGUMENTS; - return ERROR_OK; - + return ERROR_OK; } - int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) { - /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -1196,12 +1225,12 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co case 4: /* TODOLATER Check error return value ! */ { - ahbap_read_buf(swjdp, buffer, 4*count, address); + ahbap_read_buf(swjdp, buffer, 4 * count, address); } break; case 2: { - ahbap_read_buf(swjdp, buffer, 2*count, address); + ahbap_read_buf_u16(swjdp, buffer, 2 * count, address); } break; case 1: @@ -1213,14 +1242,12 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co ERROR("BUG: we shouldn't get here"); exit(-1); } - - + return ERROR_OK; } int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) { - /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; cortex_m3_common_t *cortex_m3 = armv7m->arch_info; @@ -1238,12 +1265,12 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c case 4: /* TODOLATER Check error return value ! */ { - ahbap_write_buf(swjdp, buffer, 4*count, address); + ahbap_write_buf(swjdp, buffer, 4 * count, address); } break; case 2: { - ahbap_write_buf(swjdp, buffer, 2*count, address); + ahbap_write_buf_u16(swjdp, buffer, 2 * count, address); } break; case 1: @@ -1261,14 +1288,11 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { - - cortex_m3_write_memory(target, address, 4,count,buffer); + cortex_m3_write_memory(target, address, 4, count, buffer); return ERROR_OK; } - - void cortex_m3_build_reg_cache(target_t *target) { armv7m_build_reg_cache(target); @@ -1276,7 +1300,7 @@ void cortex_m3_build_reg_cache(target_t *target) int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - u32 did1, dc0, cpuid, fpcr, dwtcr, ictr; + u32 cpuid, fpcr, dwtcr, ictr; int i; /* get pointers to arch-specific information */ @@ -1287,48 +1311,43 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta cortex_m3_build_reg_cache(target); ahbap_debugport_init(swjdp); - /* Read from Device Identification Registers, IS THIS CORTEX OR Luminary Micro SPECIFIC ?? */ - target_read_u32(target, CPUID, &cpuid ); - if (cpuid == 0x410fc231) - DEBUG("CORTEX-M3 processor"); - DEBUG("cpuid %x",cpuid); - /* Probably only valid for LMI parts, move to flash/stellaris ? */ - target_read_u32(target, SYSTEM_CONTROL_BASE|0x04, &did1); - target_read_u32(target,SYSTEM_CONTROL_BASE|0x08,&dc0); - DEBUG("did1 %x",did1); - DEBUG("dc0 %x",dc0); + /* Read from Device Identification Registers */ + target_read_u32(target, CPUID, &cpuid); + if (((cpuid >> 4) & 0xc3f) == 0xc23) + DEBUG("CORTEX-M3 processor detected"); + DEBUG("cpuid: 0x%8.8x", cpuid); - target_read_u32(target,NVIC_ICTR,&ictr); - cortex_m3->intlinesnum = (ictr&0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum,4); - for (i=0;iintlinesnum;i++) + target_read_u32(target, NVIC_ICTR, &ictr); + cortex_m3->intlinesnum = (ictr & 0x1F) + 1; + cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); + for (i = 0; i < cortex_m3->intlinesnum; i++) { - target_read_u32(target,NVIC_ISE0+4*i,cortex_m3->intsetenable+i); - DEBUG(" interrupt enable[%i]=0x%x",i,cortex_m3->intsetenable[i]); + target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); + DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]); } /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); cortex_m3->auto_bp_type = 1; - cortex_m3->fp_num_code = (fpcr>>4)&0xF; - cortex_m3->fp_num_lit = (fpcr>>8)&0xF; + cortex_m3->fp_num_code = (fpcr >> 4) & 0xF; + cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list=calloc(cortex_m3->fp_num_code+cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); - for (i=0;ifp_num_code+cortex_m3->fp_num_lit;i++) + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { - cortex_m3->fp_comparator_list[i].type = (ifp_num_code)?FPCR_CODE:FPCR_LITERAL; - cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0+4*i; + cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; + cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; } - DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i",fpcr,cortex_m3->fp_num_code,cortex_m3->fp_num_lit); + DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); /* Setup DWT */ target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr>>28)&0xF; + cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; cortex_m3->dwt_comparator_list=calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i=0; idwt_num_comp; i++) + for (i = 0; i < cortex_m3->dwt_num_comp; i++) { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0+0x10*i; + cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; } return ERROR_OK; @@ -1340,13 +1359,82 @@ int cortex_m3_quit() return ERROR_OK; } +int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl) +{ + u16 dcrdr; + + ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); + *ctrl = (u8)dcrdr; + *value = (u8)(dcrdr >> 8); + + DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl); + + /* write ack back to software dcc register + * signify we have read data */ + dcrdr = 0; + ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR); + return ERROR_OK; +} + +int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer) +{ + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + u8 data; + u8 ctrl; + int i; + + for (i = 0; i < (size * 4); i++) + { + cortex_m3_dcc_read(swjdp, &data, &ctrl); + buffer[i] = data; + } + + return ERROR_OK; +} + +int cortex_m3_handle_target_request(void *priv) +{ + target_t *target = priv; + armv7m_common_t *armv7m = target->arch_info; + cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + swjdp_common_t *swjdp = &cortex_m3->swjdp_info; + + if (!target->dbg_msg_enabled) + return ERROR_OK; + + if (target->state == TARGET_RUNNING) + { + u8 data; + u8 ctrl; + + cortex_m3_dcc_read(swjdp, &data, &ctrl); + + /* check if we have data */ + if (ctrl & (1<<0)) + { + u32 request; + + request = data; + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 8); + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 16); + cortex_m3_dcc_read(swjdp, &data, &ctrl); + request |= (data << 24); + target_request(target, request); + } + } + + return ERROR_OK; +} + int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant) { armv7m_common_t *armv7m; armv7m = &cortex_m3->armv7m; - arm_jtag_t * jtag_info = &cortex_m3->jtag_info; - /* prepare JTAG information for the new target */ cortex_m3->jtag_info.chain_pos = chain_pos; cortex_m3->jtag_info.scann_size = 4; @@ -1376,6 +1464,8 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; // armv7m->full_context = cortex_m3_full_context; + target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target); + return ERROR_OK; }