X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=12f0eec15501694e618e9ea52d74d8b17a2f9f26;hp=e157805046adc3e60cb9d5f9967edd3ed368b1e7;hb=7269ba5eb6c4c0e3b8dfceba9d5f2c2f4dfc1618;hpb=da739aa25733b5a252a2b0b8ad76a3dc886f1132

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index e157805046..12f0eec155 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -56,12 +56,6 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[];
 extern reg_t armv7m_gdb_dummy_cpsr_reg;
 #endif
 
-static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu)
-{
-	*has_mmu = false;
-	return ERROR_OK;
-}
-
 static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
 		uint32_t *value, int regnum)
 {
@@ -1578,7 +1572,7 @@ fail1:
 	*register_get_last_cache_p(&target->reg_cache) = cache;
 	cm3->dwt_cache = cache;
 
-	LOG_INFO("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
+	LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
 			dwtcr, cm3->dwt_num_comp,
 			(dwtcr & (0xf << 24)) ? " only" : "/trigger");
 
@@ -1998,6 +1992,5 @@ target_type_t cortexm3_target =
 	.register_commands = cortex_m3_register_commands,
 	.target_create = cortex_m3_target_create,
 	.init_target = cortex_m3_init_target,
-	.has_mmu = cortex_m3_has_mmu,
 	.examine = cortex_m3_examine,
 };