X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.h;h=c33486273fc08f44eae89db6a2336238f69bd444;hp=cdda0fafd0f0d0506f218870549aa5968be7e7f6;hb=c734202dc89bb3ee05a204140b3c890451e79686;hpb=d998ea40f3a323cfbc7b80d9c9d5057fbc76c6a9 diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index cdda0fafd0..c33486273f 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -19,24 +19,23 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see . * ***************************************************************************/ -#ifndef CORTEX_M3_H -#define CORTEX_M3_H +#ifndef OPENOCD_TARGET_CORTEX_M_H +#define OPENOCD_TARGET_CORTEX_M_H #include "armv7m.h" -#define CORTEX_M3_COMMON_MAGIC 0x1A451A45 +#define CORTEX_M_COMMON_MAGIC 0x1A451A45 #define SYSTEM_CONTROL_BASE 0x400FE000 -#define ITM_TER 0xE0000E00 +#define ITM_TER0 0xE0000E00 #define ITM_TPR 0xE0000E40 #define ITM_TCR 0xE0000E80 #define ITM_LAR 0xE0000FB0 +#define ITM_LAR_KEY 0xC5ACCE55 #define CPUID 0xE000ED00 /* Debug Control Block */ @@ -49,6 +48,7 @@ #define DWT_CTRL 0xE0001000 #define DWT_CYCCNT 0xE0001004 +#define DWT_PCSR 0xE000101C #define DWT_COMP0 0xE0001020 #define DWT_MASK0 0xE0001024 #define DWT_FUNCTION0 0xE0001028 @@ -69,13 +69,13 @@ #define FPU_FPCAR 0xE000EF38 #define FPU_FPDSCR 0xE000EF3C -#define TPI_SSPSR 0xE0040000 -#define TPI_CSPSR 0xE0040004 -#define TPI_ACPR 0xE0040010 -#define TPI_SPPR 0xE00400F0 -#define TPI_FFSR 0xE0040300 -#define TPI_FFCR 0xE0040304 -#define TPI_FSCR 0xE0040308 +#define TPIU_SSPSR 0xE0040000 +#define TPIU_CSPSR 0xE0040004 +#define TPIU_ACPR 0xE0040010 +#define TPIU_SPPR 0xE00400F0 +#define TPIU_FFSR 0xE0040300 +#define TPIU_FFCR 0xE0040304 +#define TPIU_FSCR 0xE0040308 /* DCB_DHCSR bit and field definitions */ #define DBGKEY (0xA05F << 16) @@ -135,35 +135,35 @@ #define FPCR_REPLACE_BKPT_HIGH (2 << 30) #define FPCR_REPLACE_BKPT_BOTH (3 << 30) -struct cortex_m3_fp_comparator { - int used; +struct cortex_m_fp_comparator { + bool used; int type; uint32_t fpcr_value; uint32_t fpcr_address; }; -struct cortex_m3_dwt_comparator { - int used; +struct cortex_m_dwt_comparator { + bool used; uint32_t comp; uint32_t mask; uint32_t function; uint32_t dwt_comparator_address; }; -enum cortex_m3_soft_reset_config { - CORTEX_M3_RESET_SYSRESETREQ, - CORTEX_M3_RESET_VECTRESET, +enum cortex_m_soft_reset_config { + CORTEX_M_RESET_SYSRESETREQ, + CORTEX_M_RESET_VECTRESET, }; -enum cortex_m3_isrmasking_mode { - CORTEX_M3_ISRMASK_AUTO, - CORTEX_M3_ISRMASK_OFF, - CORTEX_M3_ISRMASK_ON, +enum cortex_m_isrmasking_mode { + CORTEX_M_ISRMASK_AUTO, + CORTEX_M_ISRMASK_OFF, + CORTEX_M_ISRMASK_ON, + CORTEX_M_ISRMASK_STEPONLY, }; -struct cortex_m3_common { +struct cortex_m_common { int common_magic; - struct arm_jtag jtag_info; /* Context information */ uint32_t dcb_dhcsr; @@ -173,42 +173,51 @@ struct cortex_m3_common { /* Flash Patch and Breakpoint (FPB) */ int fp_num_lit; int fp_num_code; - int fp_code_available; - int fpb_enabled; - int auto_bp_type; - struct cortex_m3_fp_comparator *fp_comparator_list; + int fp_rev; + bool fpb_enabled; + struct cortex_m_fp_comparator *fp_comparator_list; /* Data Watchpoint and Trace (DWT) */ int dwt_num_comp; int dwt_comp_available; - struct cortex_m3_dwt_comparator *dwt_comparator_list; + struct cortex_m_dwt_comparator *dwt_comparator_list; struct reg_cache *dwt_cache; - enum cortex_m3_soft_reset_config soft_reset_config; + enum cortex_m_soft_reset_config soft_reset_config; + bool vectreset_supported; - enum cortex_m3_isrmasking_mode isrmasking_mode; + enum cortex_m_isrmasking_mode isrmasking_mode; struct armv7m_common armv7m; + + int apsel; + + /* Whether this target has the erratum that makes C_MASKINTS not apply to + * already pending interrupts */ + bool maskints_erratum; }; -static inline struct cortex_m3_common * -target_to_cm3(struct target *target) +static inline struct cortex_m_common * +target_to_cm(struct target *target) { return container_of(target->arch_info, - struct cortex_m3_common, armv7m); + struct cortex_m_common, armv7m); } -int cortex_m3_examine(struct target *target); -int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); -int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); -int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint); -int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); -int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint); -int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint); -int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint); -int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); -void cortex_m3_enable_breakpoints(struct target *target); -void cortex_m3_enable_watchpoints(struct target *target); -void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target); - -#endif /* CORTEX_M3_H */ +int cortex_m_examine(struct target *target); +int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint); +int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint); +int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); +int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint); +int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint); +int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint); +int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); +void cortex_m_enable_breakpoints(struct target *target); +void cortex_m_enable_watchpoints(struct target *target); +void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target); +void cortex_m_deinit_target(struct target *target); +int cortex_m_profiling(struct target *target, uint32_t *samples, + uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); + +#endif /* OPENOCD_TARGET_CORTEX_M_H */