X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.h;h=b375d1111d308c3c577e86ee5c1b0cb55e53c1cd;hp=8a284bd9887f8ff90544e8b587fdbd667f15092e;hb=351ef7bf3cce048ec854c8d19d8af5aa2b97c3a9;hpb=1c975fe30b8fb380907133462cc38a0b2e9de565

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 8a284bd988..b375d1111d 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -19,13 +19,11 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef CORTEX_M_H
-#define CORTEX_M_H
+#ifndef OPENOCD_TARGET_CORTEX_M_H
+#define OPENOCD_TARGET_CORTEX_M_H
 
 #include "armv7m.h"
 
@@ -33,10 +31,11 @@
 
 #define SYSTEM_CONTROL_BASE 0x400FE000
 
-#define ITM_TER		0xE0000E00
+#define ITM_TER0	0xE0000E00
 #define ITM_TPR		0xE0000E40
 #define ITM_TCR		0xE0000E80
 #define ITM_LAR		0xE0000FB0
+#define ITM_LAR_KEY	0xC5ACCE55
 
 #define CPUID		0xE000ED00
 /* Debug Control Block */
@@ -49,6 +48,7 @@
 
 #define DWT_CTRL	0xE0001000
 #define DWT_CYCCNT	0xE0001004
+#define DWT_PCSR	0xE000101C
 #define DWT_COMP0	0xE0001020
 #define DWT_MASK0	0xE0001024
 #define DWT_FUNCTION0	0xE0001028
@@ -69,13 +69,13 @@
 #define FPU_FPCAR	0xE000EF38
 #define FPU_FPDSCR	0xE000EF3C
 
-#define TPI_SSPSR	0xE0040000
-#define TPI_CSPSR	0xE0040004
-#define TPI_ACPR	0xE0040010
-#define TPI_SPPR	0xE00400F0
-#define TPI_FFSR	0xE0040300
-#define TPI_FFCR	0xE0040304
-#define TPI_FSCR	0xE0040308
+#define TPIU_SSPSR	0xE0040000
+#define TPIU_CSPSR	0xE0040004
+#define TPIU_ACPR	0xE0040010
+#define TPIU_SPPR	0xE00400F0
+#define TPIU_FFSR	0xE0040300
+#define TPIU_FFCR	0xE0040304
+#define TPIU_FSCR	0xE0040308
 
 /* DCB_DHCSR bit and field definitions */
 #define DBGKEY		(0xA05F << 16)
@@ -136,14 +136,14 @@
 #define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 
 struct cortex_m_fp_comparator {
-	int used;
+	bool used;
 	int type;
 	uint32_t fpcr_value;
 	uint32_t fpcr_address;
 };
 
 struct cortex_m_dwt_comparator {
-	int used;
+	bool used;
 	uint32_t comp;
 	uint32_t mask;
 	uint32_t function;
@@ -163,7 +163,6 @@ enum cortex_m_isrmasking_mode {
 
 struct cortex_m_common {
 	int common_magic;
-	struct arm_jtag jtag_info;
 
 	/* Context information */
 	uint32_t dcb_dhcsr;
@@ -174,8 +173,8 @@ struct cortex_m_common {
 	int fp_num_lit;
 	int fp_num_code;
 	int fp_code_available;
-	int fpb_enabled;
-	int auto_bp_type;
+	int fp_rev;
+	bool fpb_enabled;
 	struct cortex_m_fp_comparator *fp_comparator_list;
 
 	/* Data Watchpoint and Trace (DWT) */
@@ -185,10 +184,13 @@ struct cortex_m_common {
 	struct reg_cache *dwt_cache;
 
 	enum cortex_m_soft_reset_config soft_reset_config;
+	bool vectreset_supported;
 
 	enum cortex_m_isrmasking_mode isrmasking_mode;
 
 	struct armv7m_common armv7m;
+
+	int apsel;
 };
 
 static inline struct cortex_m_common *
@@ -210,5 +212,8 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo
 void cortex_m_enable_breakpoints(struct target *target);
 void cortex_m_enable_watchpoints(struct target *target);
 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
+void cortex_m_deinit_target(struct target *target);
+int cortex_m_profiling(struct target *target, uint32_t *samples,
+	uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 
-#endif /* CORTEX_M_H */
+#endif /* OPENOCD_TARGET_CORTEX_M_H */