X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=ea8a086027e42edb498a3f3bdc093b889197f5af;hp=09a51b7b3b35f53996feaebe564f91d87e23ea60;hb=c8492ee2d468bcee8e2b7bb0560e6329c12a86e2;hpb=7743e0fb4390d09c315ce9c6edbb2c3ba6b8c2d9 diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 09a51b7b3b..ea8a086027 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -21,7 +21,7 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * * * * * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) * @@ -61,7 +61,7 @@ /* forward declarations */ static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value); + uint32_t num, uint32_t value); static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, uint32_t *value, int regnum) @@ -149,7 +149,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, uint32_t mask_on, uint32_t mask_off) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -162,7 +162,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, static int cortex_m3_clear_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; int retval; /* clear step if any */ @@ -185,7 +185,7 @@ static int cortex_m3_clear_halt(struct target *target) static int cortex_m3_single_step_core(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; uint32_t dhcsr_save; int retval; @@ -222,7 +222,7 @@ static int cortex_m3_endreset_event(struct target *target) uint32_t dcb_demcr; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; @@ -298,7 +298,7 @@ static int cortex_m3_endreset_event(struct target *target) if (retval != ERROR_OK) return retval; - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(armv7m->arm.core_cache); /* make sure we have latest dhcsr flags */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -334,7 +334,7 @@ static int cortex_m3_examine_exception_reason(struct target *target) { uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval; retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); @@ -406,7 +406,7 @@ static int cortex_m3_debug_entry(struct target *target) struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; struct arm *arm = &armv7m->arm; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; struct reg *r; LOG_DEBUG(" "); @@ -421,48 +421,36 @@ static int cortex_m3_debug_entry(struct target *target) return retval; /* Examine target state and mode - * First load register acessible through core debug port*/ - int num_regs = armv7m->core_cache->num_regs; + * First load register accessible through core debug port */ + int num_regs = arm->core_cache->num_regs; for (i = 0; i < num_regs; i++) { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + r = &armv7m->arm.core_cache->reg_list[i]; + if (!r->valid) + arm->read_core_reg(target, r, i, ARM_MODE_ANY); } - r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + r = arm->cpsr; xPSR = buf_get_u32(r->value, 0, 32); -#ifdef ARMV7_GDB_HACKS - /* FIXME this breaks on scan chains with more than one Cortex-M3. - * Instead, each CM3 should have its own dummy value... - */ - /* copy real xpsr reg for gdb, setting thumb bit */ - buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR); - buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1); - armv7m_gdb_dummy_cpsr_reg.valid = r->valid; - armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty; -#endif - /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ if (xPSR & 0xf00) { r->dirty = r->valid; - cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR & ~0xff); + cortex_m3_store_core_reg_u32(target, 16, xPSR & ~0xff); } /* Are we in an exception handler */ if (xPSR & 0x1FF) { - armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { - unsigned control = buf_get_u32(armv7m->core_cache + unsigned control = buf_get_u32(arm->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 2); /* is this thread privileged? */ - armv7m->core_mode = control & 1; - arm->core_mode = armv7m->core_mode + arm->core_mode = control & 1 ? ARM_MODE_USER_THREAD : ARM_MODE_THREAD; @@ -479,7 +467,7 @@ static int cortex_m3_debug_entry(struct target *target) cortex_m3_examine_exception_reason(target); LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", - armv7m_mode_strings[armv7m->core_mode], + arm_mode_name(arm->core_mode), *(uint32_t *)(arm->pc->value), target_state_name(target)); @@ -498,7 +486,7 @@ static int cortex_m3_poll(struct target *target) int retval = ERROR_OK; enum target_state prev_target_state = target->state; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -629,10 +617,16 @@ static int cortex_m3_halt(struct target *target) static int cortex_m3_soft_reset_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; + /* soft_reset_halt is deprecated on cortex_m as the same functionality + * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset' + * As this reset only used VC_CORERESET it would only ever reset the cortex_m + * core, not the peripherals */ + LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead."); + /* Enter debug state on reset; restore DEMCR in endreset_event() */ retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); @@ -647,7 +641,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) target->state = TARGET_RESET; /* registers are now invalid */ - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); while (timeout < 100) { retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); @@ -677,7 +671,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) return ERROR_OK; } -static void cortex_m3_enable_breakpoints(struct target *target) +void cortex_m3_enable_breakpoints(struct target *target) { struct breakpoint *breakpoint = target->breakpoints; @@ -709,7 +703,7 @@ static int cortex_m3_resume(struct target *target, int current, } if (debug_execution) { - r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK; + r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK; /* Disable interrupts */ /* We disable interrupts in the PRIMASK register instead of @@ -727,7 +721,7 @@ static int cortex_m3_resume(struct target *target, int current, r->valid = true; /* Make sure we are in Thumb mode */ - r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + r = armv7m->arm.cpsr; buf_set_u32(r->value, 24, 1, 1); r->dirty = true; r->valid = true; @@ -773,7 +767,7 @@ static int cortex_m3_resume(struct target *target, int current, target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - register_cache_invalidate(armv7m->core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (!debug_execution) { target->state = TARGET_RUNNING; @@ -794,7 +788,7 @@ static int cortex_m3_step(struct target *target, int current, { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; struct breakpoint *breakpoint = NULL; struct reg *pc = armv7m->arm.pc; bool bkpt_inst_found = false; @@ -854,45 +848,78 @@ static int cortex_m3_step(struct target *target, int current, * */ - /* Set a temporary break point */ - retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value)); - bool tmp_bp_set = (retval == ERROR_OK); - - /* No more breakpoints left, just do a step */ - if (!tmp_bp_set) + /* 2012-09-29 ph + * + * If a break point is already set on the lower half word then a break point on + * the upper half word will not break again when the core is restarted. So we + * just step over the instruction with interrupts disabled. + * + * The documentation has no information about this, it was found by observation + * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to + * suffer from this problem. + * + * To add some confusion: pc_value has bit 0 always set, while the breakpoint + * address has it always cleared. The former is done to indicate thumb mode + * to gdb. + * + */ + if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) { + LOG_DEBUG("Stepping over next instruction with interrupts disabled"); + cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0); cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + /* Re-enable interrupts */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } else { - /* Start the core */ - LOG_DEBUG("Starting core to serve pending interrupts"); - int64_t t_start = timeval_ms(); - cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP); - - /* Wait for pending handlers to complete or timeout */ - do { - retval = mem_ap_read_atomic_u32(swjdp, - DCB_DHCSR, - &cortex_m3->dcb_dhcsr); - if (retval != ERROR_OK) { - target->state = TARGET_UNKNOWN; - return retval; - } - isr_timed_out = ((timeval_ms() - t_start) > 500); - } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out)); - - /* Remove the temporary breakpoint */ - breakpoint_remove(target, pc_value); - - if (isr_timed_out) { - LOG_DEBUG("Interrupt handlers didn't complete within time, " - "leaving target running"); - } else { - /* Step over next instruction with interrupts disabled */ - cortex_m3_write_debug_halt_mask(target, - C_HALT | C_MASKINTS, - 0); + + /* Set a temporary break point */ + if (breakpoint) + retval = cortex_m3_set_breakpoint(target, breakpoint); + else + retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value)); + bool tmp_bp_set = (retval == ERROR_OK); + + /* No more breakpoints left, just do a step */ + if (!tmp_bp_set) cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); - /* Re-enable interrupts */ - cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + else { + /* Start the core */ + LOG_DEBUG("Starting core to serve pending interrupts"); + int64_t t_start = timeval_ms(); + cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP); + + /* Wait for pending handlers to complete or timeout */ + do { + retval = mem_ap_read_atomic_u32(swjdp, + DCB_DHCSR, + &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) { + target->state = TARGET_UNKNOWN; + return retval; + } + isr_timed_out = ((timeval_ms() - t_start) > 500); + } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out)); + + /* only remove breakpoint if we created it */ + if (breakpoint) + cortex_m3_unset_breakpoint(target, breakpoint); + else { + /* Remove the temporary breakpoint */ + breakpoint_remove(target, pc_value); + } + + if (isr_timed_out) { + LOG_DEBUG("Interrupt handlers didn't complete within time, " + "leaving target running"); + } else { + /* Step over next instruction with interrupts disabled */ + cortex_m3_write_debug_halt_mask(target, + C_HALT | C_MASKINTS, + 0); + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + /* Re-enable interrupts */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } } } } @@ -903,7 +930,7 @@ static int cortex_m3_step(struct target *target, int current, return retval; /* registers are now invalid */ - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); @@ -934,7 +961,7 @@ static int cortex_m3_step(struct target *target, int current, static int cortex_m3_assert_reset(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config; LOG_DEBUG("target->state: %s", @@ -946,12 +973,23 @@ static int cortex_m3_assert_reset(struct target *target) /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); target->state = TARGET_RESET; return ERROR_OK; } + /* some cores support connecting while srst is asserted + * use that mode is it has been configured */ + + bool srst_asserted = false; + + if ((jtag_reset_config & RESET_HAS_SRST) && + (jtag_reset_config & RESET_SRST_NO_GATING)) { + adapter_assert_reset(); + srst_asserted = true; + } + /* Enable debug requests */ int retval; retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -963,6 +1001,14 @@ static int cortex_m3_assert_reset(struct target *target) return retval; } + /* If the processor is sleeping in a WFI or WFE instruction, the + * C_HALT bit must be asserted to regain control */ + if (cortex_m3->dcb_dhcsr & S_SLEEP) { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); if (retval != ERROR_OK) return retval; @@ -996,7 +1042,8 @@ static int cortex_m3_assert_reset(struct target *target) if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ - adapter_assert_reset(); + if (!srst_asserted) + adapter_assert_reset(); } else { /* Use a standard Cortex-M3 software reset mechanism. * We default to using VECRESET as it is supported on all current cores. @@ -1009,12 +1056,12 @@ static int cortex_m3_assert_reset(struct target *target) if (retval != ERROR_OK) return retval; - LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ) + LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ) ? "SYSRESETREQ" : "VECTRESET"); if (reset_config == CORTEX_M3_RESET_VECTRESET) { - LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event " - "handler to reset any peripherals"); + LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event " + "handler to reset any peripherals or configure hardware srst support."); } { @@ -1032,7 +1079,7 @@ static int cortex_m3_assert_reset(struct target *target) target->state = TARGET_RESET; jtag_add_sleep(50000); - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); if (target->reset_halt) { retval = target_halt(target); @@ -1174,17 +1221,8 @@ int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoin { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - if (cortex_m3->auto_bp_type) { + if (cortex_m3->auto_bp_type) breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); -#ifdef ARMV7_GDB_HACKS - if (breakpoint->length != 2) { - /* XXX Hack: Replace all breakpoints with length != 2 with - * a hardware breakpoint. */ - breakpoint->type = BKPT_HARD; - breakpoint->length = 2; - } -#endif - } if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) { if (breakpoint->type == BKPT_HARD) { @@ -1414,11 +1452,11 @@ void cortex_m3_enable_watchpoints(struct target *target) } static int cortex_m3_load_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t *value) + uint32_t num, uint32_t *value) { int retval; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1475,24 +1513,12 @@ static int cortex_m3_load_core_reg_u32(struct target *target, } static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value) + uint32_t num, uint32_t value) { int retval; uint32_t reg; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; - -#ifdef ARMV7_GDB_HACKS - /* If the LR register is being modified, make sure it will put us - * in "thumb" mode, or an INVSTATE exception will occur. This is a - * hack to deal with the fact that gdb will sometimes "forge" - * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) - * Valid exception return codes have bit 0 set too. - */ - if (num == ARMV7M_R14) - value |= 0x01; -#endif + struct adiv5_dap *swjdp = armv7m->arm.dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1505,7 +1531,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target, struct reg *r; LOG_ERROR("JTAG failure"); - r = armv7m->core_cache->reg_list + num; + r = armv7m->arm.core_cache->reg_list + num; r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; } @@ -1556,55 +1582,30 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; - int retval = ERROR_COMMAND_SYNTAX_ERROR; - - /* cortex_m3 handles unaligned memory access */ - if (count && buffer) { - switch (size) { - case 4: - retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); - break; - } + struct adiv5_dap *swjdp = armv7m->arm.dap; + + if (armv7m->arm.is_armv6m) { + /* armv6m does not handle unaligned memory access */ + if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) + return ERROR_TARGET_UNALIGNED_ACCESS; } - return retval; + return mem_ap_read(swjdp, buffer, size, count, address, true); } static int cortex_m3_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; - int retval = ERROR_COMMAND_SYNTAX_ERROR; + struct adiv5_dap *swjdp = armv7m->arm.dap; - if (count && buffer) { - switch (size) { - case 4: - retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); - break; - } + if (armv7m->arm.is_armv6m) { + /* armv6m does not handle unaligned memory access */ + if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) + return ERROR_TARGET_UNALIGNED_ACCESS; } - return retval; -} - -static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) -{ - return cortex_m3_write_memory(target, address, 4, count, buffer); + return mem_ap_write(swjdp, buffer, size, count, address, true); } static int cortex_m3_init_target(struct command_context *cmd_ctx, @@ -1739,6 +1740,9 @@ fail1: for (j = 0; j < 3; j++, reg++) cortex_m3_dwt_addreg(target, cache->reg_list + reg, dwt_comp + 3 * i + j); + + /* make sure we clear any watchpoints enabled on the target */ + target_write_u32(target, comparator->dwt_comparator_address + 8, 0); } *register_get_last_cache_p(&target->reg_cache) = cache; @@ -1766,12 +1770,16 @@ int cortex_m3_examine(struct target *target) uint32_t cpuid, fpcr, mvfr0, mvfr1; int i; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; struct armv7m_common *armv7m = target_to_armv7m(target); - retval = ahbap_debugport_init(swjdp); - if (retval != ERROR_OK) - return retval; + /* stlink shares the examine handler but does not support + * all its calls */ + if (!armv7m->stlink) { + retval = ahbap_debugport_init(swjdp); + if (retval != ERROR_OK) + return retval; + } if (!target_was_examined(target)) { target_set_examined(target); @@ -1797,6 +1805,14 @@ int cortex_m3_examine(struct target *target) LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); armv7m->fp_feature = FPv4_SP; } + } else if (i == 0) { + /* Cortex-M0 does not support unaligned memory access */ + armv7m->arm.is_armv6m = true; + } + + if (i == 4 || i == 3) { + /* Cortex-M3/M4 has 4096 bytes autoincrement range */ + armv7m->dap.tar_autoincr_block = (1 << 12); } /* NOTE: FPB and DWT are both optional. */ @@ -1818,6 +1834,9 @@ int cortex_m3_examine(struct target *target) cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + + /* make sure we clear any breakpoints enabled on the target */ + target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0); } LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, @@ -1842,7 +1861,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t * uint16_t dcrdr; int retval; - mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR); + mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR); *ctrl = (uint8_t)dcrdr; *value = (uint8_t)(dcrdr >> 8); @@ -1852,7 +1871,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t * * signify we have read data */ if (dcrdr & (1 << 0)) { dcrdr = 0; - retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR); + retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR); if (retval != ERROR_OK) return retval; } @@ -1864,7 +1883,7 @@ static int cortex_m3_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; uint8_t data; uint8_t ctrl; uint32_t i; @@ -1883,7 +1902,7 @@ static int cortex_m3_handle_target_request(void *priv) if (!target_was_examined(target)) return ERROR_OK; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1934,8 +1953,11 @@ static int cortex_m3_init_arch_info(struct target *target, /* Leave (only) generic DAP stuff for debugport_init(); */ armv7m->dap.jtag_info = &cortex_m3->jtag_info; armv7m->dap.memaccess_tck = 8; - /* Cortex-M3 has 4096 bytes autoincrement range */ - armv7m->dap.tar_autoincr_block = (1 << 12); + + /* Cortex-M3/M4 has 4096 bytes autoincrement range + * but set a safe default to 1024 to support Cortex-M0 + * this will be changed in cortex_m3_examine if a M3/M4 is detected */ + armv7m->dap.tar_autoincr_block = (1 << 10); /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; @@ -1972,7 +1994,7 @@ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx, struct cortex_m3_common *cm3) { if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { - command_print(cmd_ctx, "target is not a Cortex-M3"); + command_print(cmd_ctx, "target is not a Cortex-M"); return ERROR_TARGET_INVALID; } return ERROR_OK; @@ -2003,7 +2025,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; uint32_t demcr = 0; int retval; @@ -2107,7 +2129,7 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) } n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode); - command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name); + command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name); return ERROR_OK; } @@ -2144,7 +2166,7 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command) break; } - command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config); + command_print(CMD_CTX, "cortex_m reset_config %s", reset_config); return ERROR_OK; } @@ -2154,7 +2176,7 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = { .name = "maskisr", .handler = handle_cortex_m3_mask_interrupts_command, .mode = COMMAND_EXEC, - .help = "mask cortex_m3 interrupts", + .help = "mask cortex_m interrupts", .usage = "['auto'|'on'|'off']", }, { @@ -2178,9 +2200,9 @@ static const struct command_registration cortex_m3_command_handlers[] = { .chain = armv7m_command_handlers, }, { - .name = "cortex_m3", + .name = "cortex_m", .mode = COMMAND_EXEC, - .help = "Cortex-M3 command group", + .help = "Cortex-M command group", .usage = "", .chain = cortex_m3_exec_command_handlers, }, @@ -2188,7 +2210,8 @@ static const struct command_registration cortex_m3_command_handlers[] = { }; struct target_type cortexm3_target = { - .name = "cortex_m3", + .name = "cortex_m", + .deprecated_name = "cortex_m3", .poll = cortex_m3_poll, .arch_state = armv7m_arch_state, @@ -2207,7 +2230,6 @@ struct target_type cortexm3_target = { .read_memory = cortex_m3_read_memory, .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, .checksum_memory = armv7m_checksum_memory, .blank_check_memory = armv7m_blank_check_memory,