X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=89d70beceb7769b604825bf39399c84fdc3c877c;hp=625065c57957e876e9eecb8227b564b8f9771555;hb=fc2abe63fd3cea7497da7be2955d333bd3f800b9;hpb=374127301ec1d72033b9d573b72c7abdfd61990d diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 625065c579..89d70beceb 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -31,6 +31,7 @@ #include "config.h" #endif +#include "jtag/interface.h" #include "breakpoints.h" #include "cortex_m.h" #include "target_request.h" @@ -148,7 +149,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, uint32_t mask_on, uint32_t mask_off) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -161,7 +162,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, static int cortex_m3_clear_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; int retval; /* clear step if any */ @@ -184,7 +185,7 @@ static int cortex_m3_clear_halt(struct target *target) static int cortex_m3_single_step_core(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; uint32_t dhcsr_save; int retval; @@ -221,7 +222,7 @@ static int cortex_m3_endreset_event(struct target *target) uint32_t dcb_demcr; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; @@ -333,7 +334,7 @@ static int cortex_m3_examine_exception_reason(struct target *target) { uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval; retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); @@ -405,7 +406,7 @@ static int cortex_m3_debug_entry(struct target *target) struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; struct arm *arm = &armv7m->arm; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; struct reg *r; LOG_DEBUG(" "); @@ -450,18 +451,16 @@ static int cortex_m3_debug_entry(struct target *target) /* Are we in an exception handler */ if (xPSR & 0x1FF) { - armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; } else { - unsigned control = buf_get_u32(armv7m->core_cache + unsigned control = buf_get_u32(arm->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 2); /* is this thread privileged? */ - armv7m->core_mode = control & 1; - arm->core_mode = armv7m->core_mode + arm->core_mode = control & 1 ? ARM_MODE_USER_THREAD : ARM_MODE_THREAD; @@ -478,7 +477,7 @@ static int cortex_m3_debug_entry(struct target *target) cortex_m3_examine_exception_reason(target); LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", - armv7m_mode_strings[armv7m->core_mode], + arm_mode_name(arm->core_mode), *(uint32_t *)(arm->pc->value), target_state_name(target)); @@ -497,7 +496,7 @@ static int cortex_m3_poll(struct target *target) int retval = ERROR_OK; enum target_state prev_target_state = target->state; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -609,7 +608,7 @@ static int cortex_m3_halt(struct target *target) return ERROR_TARGET_FAILURE; } else { /* we came here in a reset_halt or reset_init sequence - * debug entry was already prepared in cortex_m3_prepare_reset_halt() + * debug entry was already prepared in cortex_m3_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; @@ -628,7 +627,7 @@ static int cortex_m3_halt(struct target *target) static int cortex_m3_soft_reset_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; @@ -676,7 +675,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) return ERROR_OK; } -static void cortex_m3_enable_breakpoints(struct target *target) +void cortex_m3_enable_breakpoints(struct target *target) { struct breakpoint *breakpoint = target->breakpoints; @@ -793,7 +792,7 @@ static int cortex_m3_step(struct target *target, int current, { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; struct breakpoint *breakpoint = NULL; struct reg *pc = armv7m->arm.pc; bool bkpt_inst_found = false; @@ -853,45 +852,78 @@ static int cortex_m3_step(struct target *target, int current, * */ - /* Set a temporary break point */ - retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value)); - bool tmp_bp_set = (retval == ERROR_OK); - - /* No more breakpoints left, just do a step */ - if (!tmp_bp_set) + /* 2012-09-29 ph + * + * If a break point is already set on the lower half word then a break point on + * the upper half word will not break again when the core is restarted. So we + * just step over the instruction with interrupts disabled. + * + * The documentation has no information about this, it was found by observation + * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to + * suffer from this problem. + * + * To add some confusion: pc_value has bit 0 always set, while the breakpoint + * address has it always cleared. The former is done to indicate thumb mode + * to gdb. + * + */ + if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) { + LOG_DEBUG("Stepping over next instruction with interrupts disabled"); + cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0); cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + /* Re-enable interrupts */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } else { - /* Start the core */ - LOG_DEBUG("Starting core to serve pending interrupts"); - int64_t t_start = timeval_ms(); - cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP); - - /* Wait for pending handlers to complete or timeout */ - do { - retval = mem_ap_read_atomic_u32(swjdp, - DCB_DHCSR, - &cortex_m3->dcb_dhcsr); - if (retval != ERROR_OK) { - target->state = TARGET_UNKNOWN; - return retval; - } - isr_timed_out = ((timeval_ms() - t_start) > 500); - } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out)); - - /* Remove the temporary breakpoint */ - breakpoint_remove(target, pc_value); - - if (isr_timed_out) { - LOG_DEBUG("Interrupt handlers didn't complete within time, " - "leaving target running"); - } else { - /* Step over next instruction with interrupts disabled */ - cortex_m3_write_debug_halt_mask(target, - C_HALT | C_MASKINTS, - 0); + + /* Set a temporary break point */ + if (breakpoint) + retval = cortex_m3_set_breakpoint(target, breakpoint); + else + retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value)); + bool tmp_bp_set = (retval == ERROR_OK); + + /* No more breakpoints left, just do a step */ + if (!tmp_bp_set) cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); - /* Re-enable interrupts */ - cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + else { + /* Start the core */ + LOG_DEBUG("Starting core to serve pending interrupts"); + int64_t t_start = timeval_ms(); + cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP); + + /* Wait for pending handlers to complete or timeout */ + do { + retval = mem_ap_read_atomic_u32(swjdp, + DCB_DHCSR, + &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) { + target->state = TARGET_UNKNOWN; + return retval; + } + isr_timed_out = ((timeval_ms() - t_start) > 500); + } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out)); + + /* only remove breakpoint if we created it */ + if (breakpoint) + cortex_m3_unset_breakpoint(target, breakpoint); + else { + /* Remove the temporary breakpoint */ + breakpoint_remove(target, pc_value); + } + + if (isr_timed_out) { + LOG_DEBUG("Interrupt handlers didn't complete within time, " + "leaving target running"); + } else { + /* Step over next instruction with interrupts disabled */ + cortex_m3_write_debug_halt_mask(target, + C_HALT | C_MASKINTS, + 0); + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + /* Re-enable interrupts */ + cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); + } } } } @@ -933,7 +965,7 @@ static int cortex_m3_step(struct target *target, int current, static int cortex_m3_assert_reset(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config; LOG_DEBUG("target->state: %s", @@ -951,6 +983,16 @@ static int cortex_m3_assert_reset(struct target *target) return ERROR_OK; } + /* some cores support connecting while srst is asserted + * use that mode is it has been configured */ + + bool srst_asserted = false; + + if (jtag_reset_config & RESET_SRST_NO_GATING) { + adapter_assert_reset(); + srst_asserted = true; + } + /* Enable debug requests */ int retval; retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -962,6 +1004,14 @@ static int cortex_m3_assert_reset(struct target *target) return retval; } + /* If the processor is sleeping in a WFI or WFE instruction, the + * C_HALT bit must be asserted to regain control */ + if (cortex_m3->dcb_dhcsr & S_SLEEP) { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); if (retval != ERROR_OK) return retval; @@ -995,10 +1045,8 @@ static int cortex_m3_assert_reset(struct target *target) if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ - if (jtag_reset_config & RESET_SRST_PULLS_TRST) - jtag_add_reset(1, 1); - else - jtag_add_reset(0, 1); + if (!srst_asserted) + adapter_assert_reset(); } else { /* Use a standard Cortex-M3 software reset mechanism. * We default to using VECRESET as it is supported on all current cores. @@ -1016,7 +1064,7 @@ static int cortex_m3_assert_reset(struct target *target) if (reset_config == CORTEX_M3_RESET_VECTRESET) { LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event " - "handler to reset any peripherals"); + "handler to reset any peripherals or configure hardware srst support."); } { @@ -1051,7 +1099,7 @@ static int cortex_m3_deassert_reset(struct target *target) target_state_name(target)); /* deassert reset lines */ - jtag_add_reset(0, 0); + adapter_deassert_reset(); return ERROR_OK; } @@ -1420,7 +1468,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target, { int retval; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1482,7 +1530,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target, int retval; uint32_t reg; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -1558,9 +1606,15 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; + if (armv7m->arm.is_armv6m) { + /* armv6m does not handle unaligned memory access */ + if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) + return ERROR_TARGET_UNALIGNED_ACCESS; + } + /* cortex_m3 handles unaligned memory access */ if (count && buffer) { switch (size) { @@ -1583,9 +1637,15 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; + if (armv7m->arm.is_armv6m) { + /* armv6m does not handle unaligned memory access */ + if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) + return ERROR_TARGET_UNALIGNED_ACCESS; + } + if (count && buffer) { switch (size) { case 4: @@ -1756,17 +1816,28 @@ fail1: */ } -static int cortex_m3_examine(struct target *target) +#define MVFR0 0xe000ef40 +#define MVFR1 0xe000ef44 + +#define MVFR0_DEFAULT_M4 0x10110021 +#define MVFR1_DEFAULT_M4 0x11000011 + +int cortex_m3_examine(struct target *target) { int retval; - uint32_t cpuid, fpcr; + uint32_t cpuid, fpcr, mvfr0, mvfr1; int i; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap; + struct armv7m_common *armv7m = target_to_armv7m(target); - retval = ahbap_debugport_init(swjdp); - if (retval != ERROR_OK) - return retval; + /* stlink shares the examine handler but does not support + * all its calls */ + if (!armv7m->stlink) { + retval = ahbap_debugport_init(swjdp); + if (retval != ERROR_OK) + return retval; + } if (!target_was_examined(target)) { target_set_examined(target); @@ -1776,11 +1847,32 @@ static int cortex_m3_examine(struct target *target) if (retval != ERROR_OK) return retval; - if (((cpuid >> 4) & 0xc3f) == 0xc23) - LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected", - (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); + /* Get CPU Type */ + i = (cpuid >> 4) & 0xf; + + LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected", + i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); + /* test for floating point feature on cortex-m4 */ + if (i == 4) { + target_read_u32(target, MVFR0, &mvfr0); + target_read_u32(target, MVFR1, &mvfr1); + + if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { + LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); + armv7m->fp_feature = FPv4_SP; + } + } else if (i == 0) { + /* Cortex-M0 does not support unaligned memory access */ + armv7m->arm.is_armv6m = true; + } + + if (i == 4 || i == 3) { + /* Cortex-M3/M4 has 4096 bytes autoincrement range */ + armv7m->dap.tar_autoincr_block = (1 << 12); + } + /* NOTE: FPB and DWT are both optional. */ /* Setup FPB */ @@ -1846,7 +1938,7 @@ static int cortex_m3_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; uint8_t data; uint8_t ctrl; uint32_t i; @@ -1865,7 +1957,7 @@ static int cortex_m3_handle_target_request(void *priv) if (!target_was_examined(target)) return ERROR_OK; struct armv7m_common *armv7m = target_to_armv7m(target); - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1916,8 +2008,11 @@ static int cortex_m3_init_arch_info(struct target *target, /* Leave (only) generic DAP stuff for debugport_init(); */ armv7m->dap.jtag_info = &cortex_m3->jtag_info; armv7m->dap.memaccess_tck = 8; - /* Cortex-M3 has 4096 bytes autoincrement range */ - armv7m->dap.tar_autoincr_block = (1 << 12); + + /* Cortex-M3/M4 has 4096 bytes autoincrement range + * but set a safe default to 1024 to support Cortex-M0 + * this will be changed in cortex_m3_examine if a M3/M4 is detected */ + armv7m->dap.tar_autoincr_block = (1 << 10); /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; @@ -1985,7 +2080,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct adiv5_dap *swjdp = &armv7m->dap; + struct adiv5_dap *swjdp = armv7m->arm.dap; uint32_t demcr = 0; int retval;