X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=7094b0708f250bf91daf8f77ebb7a54472915334;hp=99b967aa539f72e59fd9ab6b632eccc25e2e47ac;hb=67607fb64c92e069b693423642e5da6ca5a3be25;hpb=85ed6ea59fdc3cc15de33f95f04441b75b9439bf diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 99b967aa53..7094b0708f 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -298,7 +298,7 @@ static int cortex_m3_endreset_event(struct target *target) if (retval != ERROR_OK) return retval; - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(armv7m->arm.core_cache); /* make sure we have latest dhcsr flags */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -421,15 +421,16 @@ static int cortex_m3_debug_entry(struct target *target) return retval; /* Examine target state and mode - * First load register acessible through core debug port*/ - int num_regs = armv7m->core_cache->num_regs; + * First load register accessible through core debug port */ + int num_regs = arm->core_cache->num_regs; for (i = 0; i < num_regs; i++) { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); + r = &armv7m->arm.core_cache->reg_list[i]; + if (!r->valid) + arm->read_core_reg(target, r, i, ARM_MODE_ANY); } - r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + r = arm->core_cache->reg_list + ARMV7M_xPSR; xPSR = buf_get_u32(r->value, 0, 32); #ifdef ARMV7_GDB_HACKS @@ -645,7 +646,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) target->state = TARGET_RESET; /* registers are now invalid */ - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); while (timeout < 100) { retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); @@ -707,7 +708,7 @@ static int cortex_m3_resume(struct target *target, int current, } if (debug_execution) { - r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK; + r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK; /* Disable interrupts */ /* We disable interrupts in the PRIMASK register instead of @@ -725,7 +726,7 @@ static int cortex_m3_resume(struct target *target, int current, r->valid = true; /* Make sure we are in Thumb mode */ - r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR; buf_set_u32(r->value, 24, 1, 1); r->dirty = true; r->valid = true; @@ -771,7 +772,7 @@ static int cortex_m3_resume(struct target *target, int current, target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - register_cache_invalidate(armv7m->core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (!debug_execution) { target->state = TARGET_RUNNING; @@ -934,7 +935,7 @@ static int cortex_m3_step(struct target *target, int current, return retval; /* registers are now invalid */ - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(armv7m->arm.core_cache); if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); @@ -977,7 +978,7 @@ static int cortex_m3_assert_reset(struct target *target) /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); target->state = TARGET_RESET; return ERROR_OK; @@ -1082,7 +1083,7 @@ static int cortex_m3_assert_reset(struct target *target) target->state = TARGET_RESET; jtag_add_sleep(50000); - register_cache_invalidate(cortex_m3->armv7m.core_cache); + register_cache_invalidate(cortex_m3->armv7m.arm.core_cache); if (target->reset_halt) { retval = target_halt(target); @@ -1555,7 +1556,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target, struct reg *r; LOG_ERROR("JTAG failure"); - r = armv7m->core_cache->reg_list + num; + r = armv7m->arm.core_cache->reg_list + num; r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; } @@ -1619,7 +1620,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, if (count && buffer) { switch (size) { case 4: - retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); + retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address, true); break; case 2: retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); @@ -1649,7 +1650,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, if (count && buffer) { switch (size) { case 4: - retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); + retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address, true); break; case 2: retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); @@ -1663,12 +1664,6 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, return retval; } -static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) -{ - return cortex_m3_write_memory(target, address, 4, count, buffer); -} - static int cortex_m3_init_target(struct command_context *cmd_ctx, struct target *target) { @@ -1801,6 +1796,9 @@ fail1: for (j = 0; j < 3; j++, reg++) cortex_m3_dwt_addreg(target, cache->reg_list + reg, dwt_comp + 3 * i + j); + + /* make sure we clear any watchpoints enabled on the target */ + target_write_u32(target, comparator->dwt_comparator_address + 8, 0); } *register_get_last_cache_p(&target->reg_cache) = cache; @@ -1892,6 +1890,9 @@ int cortex_m3_examine(struct target *target) cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; + + /* make sure we clear any breakpoints enabled on the target */ + target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0); } LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, @@ -2284,7 +2285,6 @@ struct target_type cortexm3_target = { .read_memory = cortex_m3_read_memory, .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, .checksum_memory = armv7m_checksum_memory, .blank_check_memory = armv7m_blank_check_memory,