X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=26e556948c0bdd95b05776a649b5feffcd00094e;hp=c436bad482a592431fa6b8c1d30b6125b2bbd62c;hb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee;hpb=4315142ea0d7035fe117b9e344beaf98c91ee35c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index c436bad482..26e556948c 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  *                                                                         *
  *                                                                         *
  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
@@ -989,7 +989,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	bool srst_asserted = false;
 
-	if (jtag_reset_config & RESET_SRST_NO_GATING) {
+	if ((jtag_reset_config & RESET_HAS_SRST) &&
+	    (jtag_reset_config & RESET_SRST_NO_GATING)) {
 		adapter_assert_reset();
 		srst_asserted = true;
 	}
@@ -1060,11 +1061,11 @@ static int cortex_m3_assert_reset(struct target *target)
 		if (retval != ERROR_OK)
 			return retval;
 
-		LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+		LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
 			? "SYSRESETREQ" : "VECTRESET");
 
 		if (reset_config == CORTEX_M3_RESET_VECTRESET) {
-			LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
+			LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
 				"handler to reset any peripherals or configure hardware srst support.");
 		}
 
@@ -1796,6 +1797,9 @@ fail1:
 		for (j = 0; j < 3; j++, reg++)
 			cortex_m3_dwt_addreg(target, cache->reg_list + reg,
 				dwt_comp + 3 * i + j);
+
+		/* make sure we clear any watchpoints enabled on the target */
+		target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
 	}
 
 	*register_get_last_cache_p(&target->reg_cache) = cache;
@@ -1887,6 +1891,9 @@ int cortex_m3_examine(struct target *target)
 			cortex_m3->fp_comparator_list[i].type =
 				(i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
 			cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
+
+			/* make sure we clear any breakpoints enabled on the target */
+			target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0);
 		}
 		LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
 			fpcr,
@@ -2044,7 +2051,7 @@ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
 	struct cortex_m3_common *cm3)
 {
 	if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not a Cortex-M3");
+		command_print(cmd_ctx, "target is not a Cortex-M");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -2250,9 +2257,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 		.chain = armv7m_command_handlers,
 	},
 	{
-		.name = "cortex_m3",
+		.name = "cortex_m",
 		.mode = COMMAND_EXEC,
-		.help = "Cortex-M3 command group",
+		.help = "Cortex-M command group",
 		.usage = "",
 		.chain = cortex_m3_exec_command_handlers,
 	},
@@ -2260,7 +2267,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-	.name = "cortex_m3",
+	.name = "cortex_m",
+	.deprecated_name = "cortex_m3",
 
 	.poll = cortex_m3_poll,
 	.arch_state = armv7m_arch_state,