X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=bcdb526017dc3063972d82c2b4747a7bc5b4de4f;hp=57e4bcdf8bafe54a49ac829a116193a7238f26fe;hb=ff5deeeeaa4f394931e3c5ccfb4cfd33beda0743;hpb=31e3ea7c19d39589ac9a8b2220331206b6d1e25c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 57e4bcdf8b..bcdb526017 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -38,6 +38,7 @@
 #include "register.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
@@ -1460,7 +1461,8 @@ static int cortex_a8_examine_first(struct target *target)
 	int retval = ERROR_OK;
 	uint32_t didr, ctypr, ttypr, cpuid;
 
-	LOG_DEBUG("TODO");
+	/* stop assuming this is an OMAP! */
+	LOG_DEBUG("TODO - autoconfigure");
 
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1473,28 +1475,28 @@ static int cortex_a8_examine_first(struct target *target)
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CPUID");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "TTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "DIDR");
 		return retval;
 	}
 
@@ -1602,7 +1604,7 @@ static int cortex_a8_init_arch_info(struct target *target,
 //	arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
 	/* REVISIT v7a setup should be in a v7a-specific routine */
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@@ -1641,13 +1643,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 static const struct command_registration cortex_a8_exec_command_handlers[] = {
 	{
 		.name = "cache_info",
-		.handler = &cortex_a8_handle_cache_info_command,
+		.handler = cortex_a8_handle_cache_info_command,
 		.mode = COMMAND_EXEC,
 		.help = "display information about target caches",
 	},
 	{
 		.name = "dbginit",
-		.handler = &cortex_a8_handle_dbginit_command,
+		.handler = cortex_a8_handle_dbginit_command,
 		.mode = COMMAND_EXEC,
 		.help = "Initialize core debug",
 	},
@@ -1685,7 +1687,8 @@ struct target_type cortexa8_target = {
 	.deassert_reset = cortex_a8_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	/* REVISIT allow exporting VFP3 registers ... */
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,