X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=bcdb526017dc3063972d82c2b4747a7bc5b4de4f;hp=01b7aee808b931d8482fe958a1e4a4b0f8877c5b;hb=ff5deeeeaa4f394931e3c5ccfb4cfd33beda0743;hpb=d7760352e8044e8eb8cd9b381574e34093e1f26f

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 01b7aee808..bcdb526017 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -38,10 +38,11 @@
 #include "register.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
-static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_restore_context(struct target *target, bool bpwp);
 static int cortex_a8_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint, uint8_t matchmode);
 static int cortex_a8_unset_breakpoint(struct target *target,
@@ -89,15 +90,25 @@ static int cortex_a8_init_debug_access(struct target *target)
 	return retval;
 }
 
-int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
+/* To reduce needless round-trips, pass in a pointer to the current
+ * DSCR value.  Initialize it to zero if you just need to know the
+ * value on return from this function; or DSCR_INSTR_COMP if you
+ * happen to know that no instruction is pending.
+ */
+static int cortex_a8_exec_opcode(struct target *target,
+		uint32_t opcode, uint32_t *dscr_p)
 {
 	uint32_t dscr;
 	int retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+	dscr = dscr_p ? *dscr_p : 0;
+
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
-	do
+
+	/* Wait for InstrCompl bit to be set */
+	while ((dscr & DSCR_INSTR_COMP) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -107,7 +118,6 @@ int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
 			return retval;
 		}
 	}
-	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
 
@@ -121,7 +131,10 @@ int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
 			return retval;
 		}
 	}
-	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
+
+	if (dscr_p)
+		*dscr_p = dscr;
 
 	return retval;
 }
@@ -139,7 +152,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
 
 	cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
 	cortex_a8_dap_write_coreregister_u32(target, address, 0);
-	cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0));
+	cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
 	dap_ap_select(swjdp, swjdp_memoryap);
 	mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
 	dap_ap_select(swjdp, swjdp_debugap);
@@ -147,93 +160,12 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
 	return retval;
 }
 
-static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
-		uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-{
-	int retval;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
-	/* Move R0 to DTRTX */
-	cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
-
-	/* Read DCCTX */
-	retval = mem_ap_read_atomic_u32(swjdp,
-			armv7a->debug_base + CPUDBG_DTRTX, value);
-
-	return retval;
-}
-
-static int cortex_a8_write_cp(struct target *target, uint32_t value,
-	uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-{
-	int retval;
-	uint32_t dscr;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
-
-	/* Check that DCCRX is not full */
-	retval = mem_ap_read_atomic_u32(swjdp,
-				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	if (dscr & (1 << DSCR_DTR_RX_FULL))
-	{
-		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
-		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-	}
-
-	retval = mem_ap_write_u32(swjdp,
-			armv7a->debug_base + CPUDBG_DTRRX, value);
-	/* Move DTRRX to r0 */
-	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-
-	cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2));
-	return retval;
-}
-
-static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
-		uint32_t CRn, uint32_t CRm, uint32_t *value)
-{
-	return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
-}
-
-static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
-		uint32_t CRn, uint32_t CRm, uint32_t value)
-{
-	return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
-}
-
-static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
-{
-	if (cpnum!=15)
-	{
-		LOG_ERROR("Only cp15 is supported");
-		return ERROR_FAIL;
-	}
-	return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
-}
-
-static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
-{
-	if (cpnum!=15)
-	{
-		LOG_ERROR("Only cp15 is supported");
-		return ERROR_FAIL;
-	}
-	return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
-}
-
-
-
 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 		uint32_t *value, int regnum)
 {
 	int retval = ERROR_OK;
 	uint8_t reg = regnum&0xFF;
-	uint32_t dscr;
+	uint32_t dscr = 0;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
@@ -243,30 +175,35 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 	if (reg < 15)
 	{
 		/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
+				&dscr);
 	}
 	else if (reg == 15)
 	{
 		/* "MOV r0, r15"; then move r0 to DCCTX */
-		cortex_a8_exec_opcode(target, 0xE1A0000F);
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 	else
 	{
 		/* "MRS r0, CPSR" or "MRS r0, SPSR"
 		 * then move r0 to DCCTX
 		 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1));
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 
-	/* Read DTRRTX */
-	do
+	/* Wait for DTRRXfull then read DTRRTX */
+	while ((dscr & DSCR_DTR_TX_FULL) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
 	retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRTX, value);
@@ -289,17 +226,18 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 	/* Check that DCCRX is not full */
 	retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	if (dscr & (1 << DSCR_DTR_RX_FULL))
+	if (dscr & DSCR_DTR_RX_FULL)
 	{
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 
 	if (Rd > 17)
 		return retval;
 
-	/* Write to DCCRX */
+	/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
 	LOG_DEBUG("write DCC 0x%08" PRIx32, value);
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
@@ -307,28 +245,33 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 	if (Rd < 15)
 	{
 		/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+				&dscr);
 	}
 	else if (Rd == 15)
 	{
 		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
 		 * then "mov r15, r0"
 		 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-		cortex_a8_exec_opcode(target, 0xE1A0F000);
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+		cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
 	}
 	else
 	{
 		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
 		 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
 		 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+				&dscr);
 
 		/* "Prefetch flush" after modifying execution status in CPSR */
 		if (Rd == 16)
 			cortex_a8_exec_opcode(target,
-					ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+					&dscr);
 	}
 
 	return retval;
@@ -346,6 +289,267 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_
 	return retval;
 }
 
+/*
+ * Cortex-A8 implementation of Debug Programmer's Model
+ *
+ * NOTE the invariant:  these routines return with DSCR_INSTR_COMP set,
+ * so there's no need to poll for it before executing an instruction.
+ *
+ * NOTE that in several of these cases the "stall" mode might be useful.
+ * It'd let us queue a few operations together... prepare/finish might
+ * be the places to enable/disable that mode.
+ */
+
+static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+{
+	return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+}
+
+static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+{
+	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
+	return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
+			a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+}
+
+static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+		uint32_t *dscr_p)
+{
+	struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	if (dscr_p)
+		dscr = *dscr_p;
+
+	/* Wait for DTRRXfull */
+	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
+		retval = mem_ap_read_atomic_u32(swjdp,
+				a8->armv7a_common.debug_base + CPUDBG_DSCR,
+				&dscr);
+	}
+
+	retval = mem_ap_read_atomic_u32(swjdp,
+			a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+	//LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+
+	if (dscr_p)
+		*dscr_p = dscr;
+
+	return retval;
+}
+
+static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+	uint32_t dscr;
+	int retval;
+
+	/* set up invariant:  INSTR_COMP is set after ever DPM operation */
+	do {
+		retval = mem_ap_read_atomic_u32(swjdp,
+				a8->armv7a_common.debug_base + CPUDBG_DSCR,
+				&dscr);
+	} while ((dscr & DSCR_INSTR_COMP) == 0);
+
+	/* this "should never happen" ... */
+	if (dscr & DSCR_DTR_RX_FULL) {
+		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+		/* Clear DCCRX */
+		retval = cortex_a8_exec_opcode(
+				a8->armv7a_common.armv4_5_common.target,
+				ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+	}
+
+	return retval;
+}
+
+static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+{
+	/* REVISIT what could be done here? */
+	return ERROR_OK;
+}
+
+static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	int retval;
+	uint32_t dscr = DSCR_INSTR_COMP;
+
+	retval = cortex_a8_write_dcc(a8, data);
+
+	return cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+}
+
+static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	retval = cortex_a8_write_dcc(a8, data);
+
+	/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+			&dscr);
+
+	/* then the opcode, taking data from R0 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	return retval;
+}
+
+static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+{
+	struct target *target = dpm->arm->target;
+	uint32_t dscr = DSCR_INSTR_COMP;
+
+	/* "Prefetch flush" after modifying execution status in CPSR */
+	return cortex_a8_exec_opcode(target,
+			ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+			&dscr);
+}
+
+static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t *data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	int retval;
+	uint32_t dscr = DSCR_INSTR_COMP;
+
+	/* the opcode, writing data to DCC */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+
+static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t *data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	/* the opcode, writing data to R0 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	/* write R0 to DCC */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+			&dscr);
+
+	return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+		uint32_t addr, uint32_t control)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t vr = a8->armv7a_common.debug_base;
+	uint32_t cr = a8->armv7a_common.debug_base;
+	int retval;
+
+	switch (index) {
+	case 0 ... 15:		/* breakpoints */
+		vr += CPUDBG_BVR_BASE;
+		cr += CPUDBG_BCR_BASE;
+		break;
+	case 16 ... 31:		/* watchpoints */
+		vr += CPUDBG_WVR_BASE;
+		cr += CPUDBG_WCR_BASE;
+		index -= 16;
+		break;
+	default:
+		return ERROR_FAIL;
+	}
+	vr += 4 * index;
+	cr += 4 * index;
+
+	LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+			(unsigned) vr, (unsigned) cr);
+
+	retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+			vr, addr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+			cr, control);
+	return retval;
+}
+
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t cr;
+
+	switch (index) {
+	case 0 ... 15:
+		cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+		break;
+	case 16 ... 31:
+		cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+		index -= 16;
+		break;
+	default:
+		return ERROR_FAIL;
+	}
+	cr += 4 * index;
+
+	LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+
+	/* clear control register */
+	return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+}
+
+static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+{
+	struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+	int retval;
+
+	dpm->arm = &a8->armv7a_common.armv4_5_common;
+	dpm->didr = didr;
+
+	dpm->prepare = cortex_a8_dpm_prepare;
+	dpm->finish = cortex_a8_dpm_finish;
+
+	dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
+	dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
+	dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+
+	dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
+	dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+
+	dpm->bpwp_enable = cortex_a8_bpwp_enable;
+	dpm->bpwp_disable = cortex_a8_bpwp_disable;
+
+	retval = arm_dpm_setup(dpm);
+	if (retval == ERROR_OK)
+		retval = arm_dpm_initialize(dpm);
+
+	return retval;
+}
+
+
 /*
  * Cortex-A8 Run control
  */
@@ -436,7 +640,7 @@ static int cortex_a8_halt(struct target *target)
 	 */
 	mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	retval = mem_ap_write_atomic_u32(swjdp,
-		armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+		armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
 
 	if (retval != ERROR_OK)
 		goto out;
@@ -444,7 +648,7 @@ static int cortex_a8_halt(struct target *target)
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+	} while ((dscr & DSCR_CORE_HALTED) == 0);
 
 	target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -457,7 +661,7 @@ static int cortex_a8_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 //	struct breakpoint *breakpoint = NULL;
@@ -467,11 +671,7 @@ static int cortex_a8_resume(struct target *target, int current,
 	dap_ap_select(swjdp, swjdp_debugap);
 
 	if (!debug_execution)
-	{
 		target_free_all_working_areas(target);
-//		cortex_m3_enable_breakpoints(target);
-//		cortex_m3_enable_watchpoints(target);
-	}
 
 #if 0
 	if (debug_execution)
@@ -496,8 +696,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	resume_pc = buf_get_u32(
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+			armv4_5->core_cache->reg_list[15].value,
 			0, 32);
 	if (!current)
 		resume_pc = address;
@@ -507,31 +706,28 @@ static int cortex_a8_resume(struct target *target, int current,
 	 */
 	switch (armv4_5->core_state)
 	{
-	case ARMV4_5_STATE_ARM:
+	case ARM_STATE_ARM:
 		resume_pc &= 0xFFFFFFFC;
 		break;
-	case ARMV4_5_STATE_THUMB:
+	case ARM_STATE_THUMB:
 	case ARM_STATE_THUMB_EE:
 		/* When the return address is loaded into PC
 		 * bit 0 must be 1 to stay in Thumb state
 		 */
 		resume_pc |= 0x1;
 		break;
-	case ARMV4_5_STATE_JAZELLE:
+	case ARM_STATE_JAZELLE:
 		LOG_ERROR("How do I resume into Jazelle state??");
 		return ERROR_FAIL;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+	buf_set_u32(armv4_5->core_cache->reg_list[15].value,
 			0, 32, resume_pc);
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).dirty = 1;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).valid = 1;
+	armv4_5->core_cache->reg_list[15].dirty = 1;
+	armv4_5->core_cache->reg_list[15].valid = 1;
+
+	cortex_a8_restore_context(target, handle_breakpoints);
 
-	cortex_a8_restore_context(target);
-//	arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
 #if 0
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
@@ -547,13 +743,18 @@ static int cortex_a8_resume(struct target *target, int current,
 	}
 
 #endif
-	/* Restart core and wait for it to be started */
+	/* Restart core and wait for it to be started
+	 * NOTE: this clears DSCR_ITR_EN and other bits.
+	 *
+	 * REVISIT: for single stepping, we probably want to
+	 * disable IRQs by default, with optional override...
+	 */
 	mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
 
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+	} while ((dscr & DSCR_CORE_RESTARTED) == 0);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
@@ -582,43 +783,46 @@ static int cortex_a8_resume(struct target *target, int current,
 static int cortex_a8_debug_entry(struct target *target)
 {
 	int i;
-	uint32_t regfile[16], pc, cpsr, dscr;
+	uint32_t regfile[16], cpsr, dscr;
 	int retval = ERROR_OK;
 	struct working_area *regfile_working_area = NULL;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 	struct reg *reg;
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
-	/* Enable the ITR execution once we are in debug mode */
+	/* REVISIT surely we should not re-read DSCR !! */
 	mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	dscr |= (1 << DSCR_EXT_INT_EN);
+
+	/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+	 * imprecise data aborts get discarded by issuing a Data
+	 * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
+	 */
+
+	/* Enable the ITR execution once we are in debug mode */
+	dscr |= DSCR_ITR_EN;
 	retval = mem_ap_write_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 
 	/* Examine debug reason */
-	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
-	{
-		case 0:
-		case 4:
-			target->debug_reason = DBG_REASON_DBGRQ;
-			break;
-		case 1:
-		case 3:
-			target->debug_reason = DBG_REASON_BREAKPOINT;
-			break;
-		case 10:
-			target->debug_reason = DBG_REASON_WATCHPOINT;
-			break;
-		default:
-			target->debug_reason = DBG_REASON_UNDEFINED;
-			break;
+	arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+	/* save address of instruction that triggered the watchpoint? */
+	if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+		uint32_t wfar;
+
+		retval = mem_ap_read_atomic_u32(swjdp,
+				armv7a->debug_base + CPUDBG_WFAR,
+				&wfar);
+		arm_dpm_report_wfar(&armv7a->dpm, wfar);
 	}
 
+	/* REVISIT fast_reg_read is never set ... */
+
 	/* Examine target state and mode */
 	if (cortex_a8->fast_reg_read)
 		target_alloc_working_area(target, 64, &regfile_working_area);
@@ -626,12 +830,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	/* First load register acessible through core debug port*/
 	if (!regfile_working_area)
 	{
-		/* FIXME we don't actually need all these registers;
-		 * reading them slows us down.  Just R0, PC, CPSR...
-		 */
-		for (i = 0; i <= 15; i++)
-			cortex_a8_dap_read_coreregister_u32(target,
-					&regfile[i], i);
+		retval = arm_dpm_read_current_registers(&armv7a->dpm);
 	}
 	else
 	{
@@ -640,76 +839,40 @@ static int cortex_a8_debug_entry(struct target *target)
 				regfile_working_area->address, regfile);
 		dap_ap_select(swjdp, swjdp_memoryap);
 		target_free_working_area(target, regfile_working_area);
-	}
 
-	/* read Current PSR */
-	cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
-	pc = regfile[15];
-	dap_ap_select(swjdp, swjdp_debugap);
-	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
+		/* read Current PSR */
+		cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+		dap_ap_select(swjdp, swjdp_debugap);
+		LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-	armv4_5->core_mode = cpsr & 0x1F;
+		arm_set_cpsr(armv4_5, cpsr);
 
-	i = (cpsr >> 5) & 1;	/* T */
-	i |= (cpsr >> 23) & 1;	/* J << 1 */
-	switch (i) {
-	case 0:	/* J = 0, T = 0 */
-		armv4_5->core_state = ARMV4_5_STATE_ARM;
-		break;
-	case 1:	/* J = 0, T = 1 */
-		armv4_5->core_state = ARMV4_5_STATE_THUMB;
-		break;
-	case 2:	/* J = 1, T = 0 */
-		LOG_WARNING("Jazelle state -- not handled");
-		armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
-		break;
-	case 3:	/* J = 1, T = 1 */
-		/* ThumbEE is very much like Thumb, but some of the
-		 * instructions are different.  Single stepping and
-		 * breakpoints need updating...
-		 */
-		LOG_WARNING("ThumbEE -- incomplete support");
-		armv4_5->core_state = ARM_STATE_THUMB_EE;
-		break;
-	}
-
-	/* update cache */
-	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
-	buf_set_u32(reg->value, 0, 32, cpsr);
-	reg->valid = 1;
-	reg->dirty = 0;
+		/* update cache */
+		for (i = 0; i <= ARM_PC; i++)
+		{
+			reg = arm_reg_current(armv4_5, i);
 
-	for (i = 0; i <= ARM_PC; i++)
-	{
-		reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i);
+			buf_set_u32(reg->value, 0, 32, regfile[i]);
+			reg->valid = 1;
+			reg->dirty = 0;
+		}
 
-		buf_set_u32(reg->value, 0, 32, regfile[i]);
-		reg->valid = 1;
-		reg->dirty = 0;
-	}
+		/* Fixup PC Resume Address */
+		if (cpsr & (1 << 5))
+		{
+			// T bit set for Thumb or ThumbEE state
+			regfile[ARM_PC] -= 4;
+		}
+		else
+		{
+			// ARM state
+			regfile[ARM_PC] -= 8;
+		}
 
-	/* Fixup PC Resume Address */
-	if (cpsr & (1 << 5))
-	{
-		// T bit set for Thumb or ThumbEE state
-		regfile[ARM_PC] -= 4;
-	}
-	else
-	{
-		// ARM state
-		regfile[ARM_PC] -= 8;
+		reg = armv4_5->core_cache->reg_list + 15;
+		buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+		reg->dirty = reg->valid;
 	}
-	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, ARM_PC).value,
-			0, 32, regfile[ARM_PC]);
-
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).valid;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-		.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).valid;
 
 #if 0
 /* TODO, Move this */
@@ -729,29 +892,33 @@ static int cortex_a8_debug_entry(struct target *target)
 	if (armv7a->post_debug_entry)
 		armv7a->post_debug_entry(target);
 
-
-
 	return retval;
-
 }
 
 static void cortex_a8_post_debug_entry(struct target *target)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+	int retval;
 
-//	cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
-	/* examine cp15 control reg */
-	armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
-	jtag_execute_queue();
+	/* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
+	retval = armv7a->armv4_5_common.mrc(target, 15,
+			0, 0,	/* op1, op2 */
+			1, 0,	/* CRn, CRm */
+			&cortex_a8->cp15_control_reg);
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
 
 	if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
 		uint32_t cache_type_reg;
-		/* identify caches */
-		armv7a->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-		jtag_execute_queue();
+
+		/* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
+		retval = armv7a->armv4_5_common.mrc(target, 15,
+				0, 1,	/* op1, op2 */
+				0, 0,	/* CRn, CRm */
+				&cache_type_reg);
+		LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
+
 		/* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
 		armv4_5_identify_cache(cache_type_reg,
 				&armv7a->armv4_5_mmu.armv4_5_cache);
@@ -771,9 +938,10 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 		int handle_breakpoints)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct breakpoint *breakpoint = NULL;
 	struct breakpoint stepbreakpoint;
+	struct reg *r;
 
 	int timeout = 100;
 
@@ -784,17 +952,14 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	}
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
+	r = armv4_5->core_cache->reg_list + 15;
 	if (!current)
 	{
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, ARM_PC).value,
-				0, 32, address);
+		buf_set_u32(r->value, 0, 32, address);
 	}
 	else
 	{
-		address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, ARM_PC).value,
-				0, 32);
+		address = buf_get_u32(r->value, 0, 32);
 	}
 
 	/* The front-end may request us not to handle breakpoints.
@@ -803,18 +968,14 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	 */
 	handle_breakpoints = 1;
 	if (handle_breakpoints) {
-		breakpoint = breakpoint_find(target,
-				buf_get_u32(ARMV4_5_CORE_REG_MODE(
-					armv4_5->core_cache,
-					armv4_5->core_mode, 15).value,
-			0, 32));
+		breakpoint = breakpoint_find(target, address);
 		if (breakpoint)
 			cortex_a8_unset_breakpoint(target, breakpoint);
 	}
 
 	/* Setup single step breakpoint */
 	stepbreakpoint.address = address;
-	stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+	stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB)
 			? 2 : 4;
 	stepbreakpoint.type = BKPT_HARD;
 	stepbreakpoint.set = 0;
@@ -837,7 +998,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	}
 
 	cortex_a8_unset_breakpoint(target, &stepbreakpoint);
-	if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
+	if (timeout > 0)
+		target->debug_reason = DBG_REASON_BREAKPOINT;
 
 	if (breakpoint)
 		cortex_a8_set_breakpoint(target, breakpoint, 0);
@@ -848,31 +1010,16 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	return ERROR_OK;
 }
 
-static int cortex_a8_restore_context(struct target *target)
+static int cortex_a8_restore_context(struct target *target, bool bpwp)
 {
-	int i;
-	uint32_t value;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
 
 	LOG_DEBUG(" ");
 
 	if (armv7a->pre_restore_context)
 		armv7a->pre_restore_context(target);
 
-	for (i = 15; i >= 0; i--)
-	{
-		if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i).dirty)
-		{
-			value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
-						armv4_5->core_cache,
-						armv4_5->core_mode, i).value,
-					0, 32);
-			/* TODO Check return values */
-			cortex_a8_dap_write_coreregister_u32(target, value, i);
-		}
-	}
+	arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
 
 	if (armv7a->post_restore_context)
 		armv7a->post_restore_context(target);
@@ -881,206 +1028,6 @@ static int cortex_a8_restore_context(struct target *target)
 }
 
 
-#if 0
-/*
- * Cortex-A8 Core register functions
- */
-static int cortex_a8_load_core_reg_u32(struct target *target, int num,
-		armv4_5_mode_t mode, uint32_t * value)
-{
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	if ((num <= ARM_CPSR))
-	{
-		/* read a normal core register */
-		retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
-
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("JTAG failure %i", retval);
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-		LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
-	}
-	else
-	{
-		return ERROR_INVALID_ARGUMENTS;
-	}
-
-	/* Register other than r0 - r14 uses r0 for access */
-	if (num > 14)
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).dirty =
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).valid;
-	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).dirty =
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).valid;
-
-	return ERROR_OK;
-}
-
-static int cortex_a8_store_core_reg_u32(struct target *target, int num,
-		armv4_5_mode_t mode, uint32_t value)
-{
-	int retval;
-//	uint32_t reg;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-#ifdef ARMV7_GDB_HACKS
-	/* If the LR register is being modified, make sure it will put us
-	 * in "thumb" mode, or an INVSTATE exception will occur. This is a
-	 * hack to deal with the fact that gdb will sometimes "forge"
-	 * return addresses, and doesn't set the LSB correctly (i.e., when
-	 * printing expressions containing function calls, it sets LR=0.) */
-
-	if (num == 14)
-		value |= 0x01;
-#endif
-
-	if ((num <= ARM_CPSR))
-	{
-		retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("JTAG failure %i", retval);
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, num).dirty =
-				ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, num).valid;
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-		LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
-	}
-	else
-	{
-		return ERROR_INVALID_ARGUMENTS;
-	}
-
-	return ERROR_OK;
-}
-#endif
-
-
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value);
-
-static int cortex_a8_read_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode)
-{
-	uint32_t value;
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
-	uint32_t cpsr = 0;
-	unsigned cookie = num;
-
-	/* avoid some needless mode changes
-	 * FIXME move some of these to shared ARM code...
-	 */
-	if (mode != armv4_5->core_mode) {
-		if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
-				&& (mode == ARMV4_5_MODE_USR))
-			mode = ARMV4_5_MODE_ANY;
-		else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
-			mode = ARMV4_5_MODE_ANY;
-
-		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
-		}
-	}
-
-	if (num == 16) {
-		switch (mode) {
-		case ARMV4_5_MODE_USR:
-		case ARMV4_5_MODE_SYS:
-		case ARMV4_5_MODE_ANY:
-			/* CPSR */
-			break;
-		default:
-			/* SPSR */
-			cookie++;
-			break;
-		}
-	}
-
-	cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
-	retval = jtag_execute_queue();
-	if (retval == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
-		r->valid = 1;
-		r->dirty = 0;
-		buf_set_u32(r->value, 0, 32, value);
-	}
-
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
-	return retval;
-}
-
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
-{
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
-	uint32_t cpsr = 0;
-	unsigned cookie = num;
-
-	/* avoid some needless mode changes
-	 * FIXME move some of these to shared ARM code...
-	 */
-	if (mode != armv4_5->core_mode) {
-		if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
-				&& (mode == ARMV4_5_MODE_USR))
-			mode = ARMV4_5_MODE_ANY;
-		else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
-			mode = ARMV4_5_MODE_ANY;
-
-		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
-		}
-	}
-
-
-	if (num == 16) {
-		switch (mode) {
-		case ARMV4_5_MODE_USR:
-		case ARMV4_5_MODE_SYS:
-		case ARMV4_5_MODE_ANY:
-			/* CPSR */
-			break;
-		default:
-			/* SPSR */
-			cookie++;
-			break;
-		}
-	}
-
-	cortex_a8_dap_write_coreregister_u32(target, value, cookie);
-	if ((retval = jtag_execute_queue()) == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
-		buf_set_u32(r->value, 0, 32, value);
-		r->valid = 1;
-		r->dirty = 0;
-	}
-
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
-	return retval;
-}
-
-
 /*
  * Cortex-A8 Breakpoint and watchpoint fuctions
  */
@@ -1219,7 +1166,8 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *
 	return ERROR_OK;
 }
 
-int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int cortex_a8_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
@@ -1272,6 +1220,21 @@ static int cortex_a8_assert_reset(struct target *target)
 
 	LOG_DEBUG(" ");
 
+	/* FIXME when halt is requested, make it work somehow... */
+
+	/* Issue some kind of warm reset. */
+	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+		target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+	} else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+		/* REVISIT handle "pulls" cases, if there's
+		 * hardware that needs them to work.
+		 */
+		jtag_add_reset(0, 1);
+	} else {
+		LOG_ERROR("%s: how to reset?", target_name(target));
+		return ERROR_FAIL;
+	}
+
 	/* registers are now invalid */
 	register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
@@ -1282,14 +1245,22 @@ static int cortex_a8_assert_reset(struct target *target)
 
 static int cortex_a8_deassert_reset(struct target *target)
 {
+	int retval;
 
 	LOG_DEBUG(" ");
 
-	if (target->reset_halt)
-	{
-		int retval;
-		if ((retval = target_halt(target)) != ERROR_OK)
-			return retval;
+	/* be certain SRST is off */
+	jtag_add_reset(0, 0);
+
+	retval = cortex_a8_poll(target);
+
+	if (target->reset_halt) {
+		if (target->state != TARGET_HALTED) {
+			LOG_WARNING("%s: ran after reset and before halt ...",
+					target_name(target));
+			if ((retval = target_halt(target)) != ERROR_OK)
+				return retval;
+		}
 	}
 
 	return ERROR_OK;
@@ -1330,7 +1301,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 	return retval;
 }
 
-int cortex_a8_write_memory(struct target *target, uint32_t address,
+static int cortex_a8_write_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -1353,25 +1324,57 @@ int cortex_a8_write_memory(struct target *target, uint32_t address,
 		}
 	}
 
+	/* REVISIT this op is generic ARMv7-A/R stuff */
 	if (retval == ERROR_OK && target->state == TARGET_HALTED)
 	{
-		/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+		struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+
+		retval = dpm->prepare(dpm);
+		if (retval != ERROR_OK)
+			return retval;
+
+		/* The Cache handling will NOT work with MMU active, the
+		 * wrong addresses will be invalidated!
+		 *
+		 * For both ICache and DCache, walk all cache lines in the
+		 * address range. Cortex-A8 has fixed 64 byte line length.
+		 *
+		 * REVISIT per ARMv7, these may trigger watchpoints ...
+		 */
+
 		/* invalidate I-Cache */
 		if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 		{
-			/* Invalidate ICache single entry with MVA, repeat this for all cache
-			   lines in the address range, Cortex-A8 has fixed 64 byte line length */
-			/* Invalidate Cache single entry with MVA to PoU */
-			for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
-				armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+			/* ICIMVAU - Invalidate Cache single entry
+			 * with MVA to PoU
+			 *	MCR p15, 0, r0, c7, c5, 1
+			 */
+			for (uint32_t cacheline = address;
+					cacheline < address + size * count;
+					cacheline += 64) {
+				retval = dpm->instr_write_data_r0(dpm,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
+					cacheline);
+			}
 		}
+
 		/* invalidate D-Cache */
 		if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 		{
-			/* Invalidate Cache single entry with MVA to PoC */
-			for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
-				armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+			/* DCIMVAC - Invalidate data Cache line
+			 * with MVA to PoC
+			 *	MCR p15, 0, r0, c7, c6, 1
+			 */
+			for (uint32_t cacheline = address;
+					cacheline < address + size * count;
+					cacheline += 64) {
+				retval = dpm->instr_write_data_r0(dpm,
+					ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
+					cacheline);
+			}
 		}
+
+		/* (void) */ dpm->finish(dpm);
 	}
 
 	return retval;
@@ -1458,7 +1461,8 @@ static int cortex_a8_examine_first(struct target *target)
 	int retval = ERROR_OK;
 	uint32_t didr, ctypr, ttypr, cpuid;
 
-	LOG_DEBUG("TODO");
+	/* stop assuming this is an OMAP! */
+	LOG_DEBUG("TODO - autoconfigure");
 
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1471,28 +1475,28 @@ static int cortex_a8_examine_first(struct target *target)
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CPUID");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "TTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "DIDR");
 		return retval;
 	}
 
@@ -1501,6 +1505,9 @@ static int cortex_a8_examine_first(struct target *target)
 	LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
 	LOG_DEBUG("didr = 0x%08" PRIx32, didr);
 
+	armv7a->armv4_5_common.core_type = ARM_MODE_MON;
+	cortex_a8_dpm_setup(cortex_a8, didr);
+
 	/* Setup Breakpoint Register Pairs */
 	cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
 	cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
@@ -1519,20 +1526,7 @@ static int cortex_a8_examine_first(struct target *target)
 		cortex_a8->brp_list[i].BRPn = i;
 	}
 
-	/* Setup Watchpoint Register Pairs */
-	cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
-	cortex_a8->wrp_num_available = cortex_a8->wrp_num;
-	cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
-	for (i = 0; i < cortex_a8->wrp_num; i++)
-	{
-		cortex_a8->wrp_list[i].used = 0;
-		cortex_a8->wrp_list[i].type = 0;
-		cortex_a8->wrp_list[i].value = 0;
-		cortex_a8->wrp_list[i].control = 0;
-		cortex_a8->wrp_list[i].WRPn = i;
-	}
-	LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
-			cortex_a8->brp_num , cortex_a8->wrp_num);
+	LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
 
 	target_set_examined(target);
 	return ERROR_OK;
@@ -1557,26 +1551,14 @@ static int cortex_a8_examine(struct target *target)
  *	Cortex-A8 target creation and initialization
  */
 
-static void cortex_a8_build_reg_cache(struct target *target)
-{
-	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	armv4_5->core_type = ARM_MODE_MON;
-
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
-}
-
-
 static int cortex_a8_init_target(struct command_context *cmd_ctx,
 		struct target *target)
 {
-	cortex_a8_build_reg_cache(target);
+	/* examine_first() does a bunch of this */
 	return ERROR_OK;
 }
 
-int cortex_a8_init_arch_info(struct target *target,
+static int cortex_a8_init_arch_info(struct target *target,
 		struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
 {
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1590,7 +1572,7 @@ int cortex_a8_init_arch_info(struct target *target,
 	/* prepare JTAG information for the new target */
 	cortex_a8->jtag_info.tap = tap;
 	cortex_a8->jtag_info.scann_size = 4;
-LOG_DEBUG(" ");
+
 	swjdp->dp_select_value = -1;
 	swjdp->ap_csw_value = -1;
 	swjdp->ap_tar_value = -1;
@@ -1602,7 +1584,6 @@ LOG_DEBUG(" ");
 
 	cortex_a8->fast_reg_read = 0;
 
-
 	/* register arch-specific functions */
 	armv7a->examine_debug_reason = NULL;
 
@@ -1618,17 +1599,12 @@ LOG_DEBUG(" ");
 //	armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
 	armv7a->armv4_5_mmu.has_tiny_pages = 1;
 	armv7a->armv4_5_mmu.mmu_enabled = 0;
-	armv7a->read_cp15 = cortex_a8_read_cp15;
-	armv7a->write_cp15 = cortex_a8_write_cp15;
 
 
 //	arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
-	armv4_5->read_core_reg = cortex_a8_read_core_reg;
-	armv4_5->write_core_reg = cortex_a8_write_core_reg;
-
 	/* REVISIT v7a setup should be in a v7a-specific routine */
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@@ -1664,29 +1640,36 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 	return ERROR_OK;
 }
 
-
-static int cortex_a8_register_commands(struct command_context *cmd_ctx)
-{
-	struct command *cortex_a8_cmd;
-	int retval = ERROR_OK;
-
-	armv4_5_register_commands(cmd_ctx);
-	armv7a_register_commands(cmd_ctx);
-
-	cortex_a8_cmd =	register_command(cmd_ctx, NULL, "cortex_a8",
-			NULL, COMMAND_ANY,
-			"cortex_a8 specific commands");
-
-	register_command(cmd_ctx, cortex_a8_cmd, "cache_info",
-			cortex_a8_handle_cache_info_command, COMMAND_EXEC,
-			"display information about target caches");
-
-	register_command(cmd_ctx, cortex_a8_cmd, "dbginit",
-			cortex_a8_handle_dbginit_command, COMMAND_EXEC,
-			"Initialize core debug");
-
-	return retval;
-}
+static const struct command_registration cortex_a8_exec_command_handlers[] = {
+	{
+		.name = "cache_info",
+		.handler = cortex_a8_handle_cache_info_command,
+		.mode = COMMAND_EXEC,
+		.help = "display information about target caches",
+	},
+	{
+		.name = "dbginit",
+		.handler = cortex_a8_handle_dbginit_command,
+		.mode = COMMAND_EXEC,
+		.help = "Initialize core debug",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration cortex_a8_command_handlers[] = {
+	{
+		.chain = arm_command_handlers,
+	},
+	{
+		.chain = armv7a_command_handlers,
+	},
+	{
+		.name = "cortex_a8",
+		.mode = COMMAND_ANY,
+		.help = "Cortex-A8 command group",
+		.chain = cortex_a8_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
 
 struct target_type cortexa8_target = {
 	.name = "cortex_a8",
@@ -1704,7 +1687,8 @@ struct target_type cortexa8_target = {
 	.deassert_reset = cortex_a8_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	/* REVISIT allow exporting VFP3 registers ... */
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
@@ -1720,10 +1704,8 @@ struct target_type cortexa8_target = {
 	.add_watchpoint = NULL,
 	.remove_watchpoint = NULL,
 
-	.register_commands = cortex_a8_register_commands,
+	.commands = cortex_a8_command_handlers,
 	.target_create = cortex_a8_target_create,
 	.init_target = cortex_a8_init_target,
 	.examine = cortex_a8_examine,
-	.mrc = cortex_a8_mrc,
-	.mcr = cortex_a8_mcr,
 };