X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=8402081dfc947a2b20caa2e18b7ad6c0e407a38e;hp=f92531152be3c8627cc27f871f178bff74ea28c7;hb=e0cb27df6bc595650ca6ce205803d3aa3218e262;hpb=ac927559c3ce5406adac34b9d4ca4ecb37a48181

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index f92531152b..8402081dfc 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -33,23 +33,22 @@
 #include "config.h"
 #endif
 
+#include "breakpoints.h"
 #include "cortex_a8.h"
-#include "armv7a.h"
-#include "armv4_5.h"
-
+#include "register.h"
 #include "target_request.h"
 #include "target_type.h"
 
-static int cortex_a8_poll(target_t *target);
-static int cortex_a8_debug_entry(target_t *target);
-static int cortex_a8_restore_context(target_t *target);
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint, uint8_t matchmode);
-static int cortex_a8_unset_breakpoint(struct target_s *target,
+static int cortex_a8_unset_breakpoint(struct target *target,
 		struct breakpoint *breakpoint);
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 		uint32_t *value, int regnum);
-static int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 		uint32_t value, int regnum);
 /*
  * FIXME do topology discovery using the ROM; don't
@@ -62,7 +61,7 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target,
 /*
  * Cortex-A8 Basic debug access, very low level assumes state is saved
  */
-static int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
@@ -90,15 +89,25 @@ static int cortex_a8_init_debug_access(target_t *target)
 	return retval;
 }
 
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+/* To reduce needless round-trips, pass in a pointer to the current
+ * DSCR value.  Initialize it to zero if you just need to know the
+ * value on return from this function; or (1 << DSCR_INSTR_COMP) if
+ * you happen to know that no instruction is pending.
+ */
+static int cortex_a8_exec_opcode(struct target *target,
+		uint32_t opcode, uint32_t *dscr_p)
 {
 	uint32_t dscr;
 	int retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+	dscr = dscr_p ? *dscr_p : 0;
+
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
-	do
+
+	/* Wait for InstrCompl bit to be set */
+	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -108,7 +117,6 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 			return retval;
 		}
 	}
-	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
 
@@ -124,6 +132,9 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 	}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
+	if (dscr_p)
+		*dscr_p = dscr;
+
 	return retval;
 }
 
@@ -131,7 +142,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 Read core register with very few exec_opcode, fast but needs work_area.
 This can cause problems with MMU active.
 **************************************************************************/
-static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
 		uint32_t * regfile)
 {
 	int retval = ERROR_OK;
@@ -140,7 +151,7 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
 
 	cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
 	cortex_a8_dap_write_coreregister_u32(target, address, 0);
-	cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0));
+	cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
 	dap_ap_select(swjdp, swjdp_memoryap);
 	mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
 	dap_ap_select(swjdp, swjdp_debugap);
@@ -148,16 +159,21 @@ static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
 	return retval;
 }
 
-static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
 		uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
 	int retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
+	uint32_t dscr = 0;
+
+	/* MRC(...) to read coprocessor register into r0 */
+	cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2),
+			&dscr);
 
-	cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
 	/* Move R0 to DTRTX */
-	cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+	cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+			&dscr);
 
 	/* Read DCCTX */
 	retval = mem_ap_read_atomic_u32(swjdp,
@@ -166,7 +182,7 @@ static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
 	return retval;
 }
 
-static int cortex_a8_write_cp(target_t *target, uint32_t value,
+static int cortex_a8_write_cp(struct target *target, uint32_t value,
 	uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
 	int retval;
@@ -183,31 +199,36 @@ static int cortex_a8_write_cp(target_t *target, uint32_t value,
 	{
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 
+	/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
+
 	/* Move DTRRX to r0 */
-	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr);
 
-	cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2));
-	return retval;
+	/* MCR(...) to write r0 to coprocessor */
+	return cortex_a8_exec_opcode(target,
+			ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2),
+			&dscr);
 }
 
-static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
 		uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
 	return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
 }
 
-static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
 		uint32_t CRn, uint32_t CRm, uint32_t value)
 {
 	return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
 }
 
-static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
 	if (cpnum!=15)
 	{
@@ -217,7 +238,7 @@ static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2
 	return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
 }
 
-static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
 	if (cpnum!=15)
 	{
@@ -229,49 +250,60 @@ static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2
 
 
 
-static int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 		uint32_t *value, int regnum)
 {
 	int retval = ERROR_OK;
 	uint8_t reg = regnum&0xFF;
-	uint32_t dscr;
+	uint32_t dscr = 0;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
-	if (reg > 16)
+	if (reg > 17)
 		return retval;
 
 	if (reg < 15)
 	{
-		/* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
+		/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
+				&dscr);
 	}
 	else if (reg == 15)
 	{
-		cortex_a8_exec_opcode(target, 0xE1A0000F);
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+		/* "MOV r0, r15"; then move r0 to DCCTX */
+		cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
-	else if (reg == 16)
+	else
 	{
-		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+		/* "MRS r0, CPSR" or "MRS r0, SPSR"
+		 * then move r0 to DCCTX
+		 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+		cortex_a8_exec_opcode(target,
+				ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 
-	/* Read DTRRTX */
-	do
+	/* Wait for DTRRXfull then read DTRRTX */
+	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
 	retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRTX, value);
+	LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 
 	return retval;
 }
 
-static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+		uint32_t value, int regnum)
 {
 	int retval = ERROR_OK;
 	uint8_t Rd = regnum&0xFF;
@@ -288,39 +320,55 @@ static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value
 	{
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
 	}
 
-	if (Rd > 16)
+	if (Rd > 17)
 		return retval;
 
-	/* Write to DCCRX */
+	/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
+	LOG_DEBUG("write DCC 0x%08" PRIx32, value);
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
 
 	if (Rd < 15)
 	{
-		/* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
+		/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+				&dscr);
 	}
 	else if (Rd == 15)
 	{
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-		cortex_a8_exec_opcode(target, 0xE1A0F000);
+		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+		 * then "mov r15, r0"
+		 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+		cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
 	}
-	else if (Rd == 16)
+	else
 	{
-		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
-		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
-		/* Execute a PrefetchFlush instruction through the ITR. */
-		cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+		/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+		 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+		 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+				&dscr);
+
+		/* "Prefetch flush" after modifying execution status in CPSR */
+		if (Rd == 16)
+			cortex_a8_exec_opcode(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+					&dscr);
 	}
 
 	return retval;
 }
 
 /* Write to memory mapped registers directly with no cache or mmu handling */
-static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
 {
 	int retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -331,11 +379,204 @@ static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t add
 	return retval;
 }
 
+/*
+ * Cortex-A8 implementation of Debug Programmer's Model
+ *
+ * NOTE the invariant:  these routines return with DSCR_INSTR_COMP set,
+ * so there's no need to poll for it before executing an instruction.
+ *
+ * NOTE that in several of these cases the "stall" mode might be useful.
+ * It'd let us queue a few operations together... prepare/finish might
+ * be the places to enable/disable that mode.
+ */
+
+static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+{
+	return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+}
+
+static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+{
+	LOG_DEBUG("write DCC 0x%08" PRIx32, data);
+	return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
+			a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+}
+
+static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+		uint32_t *dscr_p)
+{
+	struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	int retval;
+
+	if (dscr_p)
+		dscr = *dscr_p;
+
+	/* Wait for DTRRXfull */
+	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
+		retval = mem_ap_read_atomic_u32(swjdp,
+				a8->armv7a_common.debug_base + CPUDBG_DSCR,
+				&dscr);
+	}
+
+	retval = mem_ap_read_atomic_u32(swjdp,
+			a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+	LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+
+	if (dscr_p)
+		*dscr_p = dscr;
+
+	return retval;
+}
+
+static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+	uint32_t dscr;
+	int retval;
+
+	/* set up invariant:  INSTR_COMP is set after ever DPM operation */
+	do {
+		retval = mem_ap_read_atomic_u32(swjdp,
+				a8->armv7a_common.debug_base + CPUDBG_DSCR,
+				&dscr);
+	} while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
+
+	/* this "should never happen" ... */
+	if (dscr & (1 << DSCR_DTR_RX_FULL)) {
+		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+		/* Clear DCCRX */
+		retval = cortex_a8_exec_opcode(
+				a8->armv7a_common.armv4_5_common.target,
+				ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+				&dscr);
+	}
+
+	return retval;
+}
+
+static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+{
+	/* REVISIT what could be done here? */
+	return ERROR_OK;
+}
+
+static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	int retval;
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+
+	retval = cortex_a8_write_dcc(a8, data);
+
+	return cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+}
+
+static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	int retval;
+
+	retval = cortex_a8_write_dcc(a8, data);
+
+	/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+			&dscr);
+
+	/* then the opcode, taking data from R0 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	return retval;
+}
+
+static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+{
+	struct target *target = dpm->arm->target;
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+
+	/* "Prefetch flush" after modifying execution status in CPSR */
+	return cortex_a8_exec_opcode(target,
+			ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+			&dscr);
+}
+
+static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t *data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	int retval;
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+
+	/* the opcode, writing data to DCC */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+
+static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+		uint32_t opcode, uint32_t *data)
+{
+	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	int retval;
+
+	/* the opcode, writing data to R0 */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			opcode,
+			&dscr);
+
+	/* write R0 to DCC */
+	retval = cortex_a8_exec_opcode(
+			a8->armv7a_common.armv4_5_common.target,
+			ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+			&dscr);
+
+	return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+{
+	struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+
+	dpm->arm = &a8->armv7a_common.armv4_5_common;
+	dpm->didr = didr;
+
+	dpm->prepare = cortex_a8_dpm_prepare;
+	dpm->finish = cortex_a8_dpm_finish;
+
+	dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
+	dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
+	dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+
+	dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
+	dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+
+	return arm_dpm_setup(dpm);
+}
+
+
 /*
  * Cortex-A8 Run control
  */
 
-static int cortex_a8_poll(target_t *target)
+static int cortex_a8_poll(struct target *target)
 {
 	int retval = ERROR_OK;
 	uint32_t dscr;
@@ -400,7 +641,7 @@ static int cortex_a8_poll(target_t *target)
 	return retval;
 }
 
-static int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
 {
 	int retval = ERROR_OK;
 	uint32_t dscr;
@@ -438,11 +679,11 @@ out:
 	return retval;
 }
 
-static int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 //	struct breakpoint *breakpoint = NULL;
@@ -481,8 +722,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
 	resume_pc = buf_get_u32(
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+			armv4_5->core_cache->reg_list[15].value,
 			0, 32);
 	if (!current)
 		resume_pc = address;
@@ -490,28 +730,30 @@ static int cortex_a8_resume(struct target_s *target, int current,
 	/* Make sure that the Armv7 gdb thumb fixups does not
 	 * kill the return address
 	 */
-	if (armv7a->core_state == ARMV7A_STATE_ARM)
+	switch (armv4_5->core_state)
 	{
+	case ARMV4_5_STATE_ARM:
 		resume_pc &= 0xFFFFFFFC;
-	}
-	/* When the return address is loaded into PC
-	 * bit 0 must be 1 to stay in Thumb state
-	 */
-	if (armv7a->core_state == ARMV7A_STATE_THUMB)
-	{
+		break;
+	case ARMV4_5_STATE_THUMB:
+	case ARM_STATE_THUMB_EE:
+		/* When the return address is loaded into PC
+		 * bit 0 must be 1 to stay in Thumb state
+		 */
 		resume_pc |= 0x1;
+		break;
+	case ARMV4_5_STATE_JAZELLE:
+		LOG_ERROR("How do I resume into Jazelle state??");
+		return ERROR_FAIL;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).value,
+	buf_set_u32(armv4_5->core_cache->reg_list[15].value,
 			0, 32, resume_pc);
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).dirty = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-			armv4_5->core_mode, 15).valid = 1;
+	armv4_5->core_cache->reg_list[15].dirty = 1;
+	armv4_5->core_cache->reg_list[15].valid = 1;
 
 	cortex_a8_restore_context(target);
-//	arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+
 #if 0
 	/* the front-end may request us not to handle breakpoints */
 	if (handle_breakpoints)
@@ -539,7 +781,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
 	target->state = TARGET_RUNNING;
 
 	/* registers are now invalid */
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(armv4_5->core_cache);
 
 	if (!debug_execution)
 	{
@@ -559,7 +801,7 @@ static int cortex_a8_resume(struct target_s *target, int current,
 	return ERROR_OK;
 }
 
-static int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
 {
 	int i;
 	uint32_t regfile[16], pc, cpsr, dscr;
@@ -567,14 +809,21 @@ static int cortex_a8_debug_entry(target_t *target)
 	struct working_area *regfile_working_area = NULL;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
+	struct reg *reg;
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
 	/* Enable the ITR execution once we are in debug mode */
 	mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
+
+	/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+	 * imprecise data aborts get discarded by issuing a Data
+	 * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
+	 */
+
 	dscr |= (1 << DSCR_EXT_INT_EN);
 	retval = mem_ap_write_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
@@ -582,22 +831,28 @@ static int cortex_a8_debug_entry(target_t *target)
 	/* Examine debug reason */
 	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
 	{
-		case 0:
-		case 4:
+		case 0:		/* DRCR[0] write */
+		case 4:		/* EDBGRQ */
 			target->debug_reason = DBG_REASON_DBGRQ;
 			break;
-		case 1:
-		case 3:
+		case 1:		/* HW breakpoint */
+		case 3:		/* SW BKPT */
+		case 5:		/* vector catch */
 			target->debug_reason = DBG_REASON_BREAKPOINT;
 			break;
-		case 10:
+		case 10:	/* precise watchpoint */
 			target->debug_reason = DBG_REASON_WATCHPOINT;
+			/* REVISIT could collect WFAR later, to see just
+			 * which instruction triggered the watchpoint.
+			 */
 			break;
 		default:
 			target->debug_reason = DBG_REASON_UNDEFINED;
 			break;
 	}
 
+	/* REVISIT fast_reg_read is never set ... */
+
 	/* Examine target state and mode */
 	if (cortex_a8->fast_reg_read)
 		target_alloc_working_area(target, 64, &regfile_working_area);
@@ -605,9 +860,7 @@ static int cortex_a8_debug_entry(target_t *target)
 	/* First load register acessible through core debug port*/
 	if (!regfile_working_area)
 	{
-		for (i = 0; i <= 15; i++)
-			cortex_a8_dap_read_coreregister_u32(target,
-					&regfile[i], i);
+		retval = arm_dpm_read_current_registers(&armv7a->dpm);
 	}
 	else
 	{
@@ -616,53 +869,41 @@ static int cortex_a8_debug_entry(target_t *target)
 				regfile_working_area->address, regfile);
 		dap_ap_select(swjdp, swjdp_memoryap);
 		target_free_working_area(target, regfile_working_area);
-	}
 
-	cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
-	pc = regfile[15];
-	dap_ap_select(swjdp, swjdp_debugap);
-	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
+		/* read Current PSR */
+		cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+		pc = regfile[15];
+		dap_ap_select(swjdp, swjdp_debugap);
+		LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-	armv4_5->core_mode = cpsr & 0x1F;
-	armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
+		arm_set_cpsr(armv4_5, cpsr);
 
-	for (i = 0; i <= ARM_PC; i++)
-	{
-		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i).value,
-				0, 32, regfile[i]);
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, i).valid = 1;
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, i).dirty = 0;
-	}
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 16).value,
-			0, 32, cpsr);
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
-
-	/* Fixup PC Resume Address */
-	if (armv7a->core_state == ARMV7A_STATE_THUMB)
-	{
-		// T bit set for Thumb or ThumbEE state
-		regfile[ARM_PC] -= 4;
-	}
-	else
-	{
-		// ARM state
-		regfile[ARM_PC] -= 8;
-	}
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, ARM_PC).value,
-			0, 32, regfile[ARM_PC]);
+		/* update cache */
+		for (i = 0; i <= ARM_PC; i++)
+		{
+			reg = arm_reg_current(armv4_5, i);
+
+			buf_set_u32(reg->value, 0, 32, regfile[i]);
+			reg->valid = 1;
+			reg->dirty = 0;
+		}
+
+		/* Fixup PC Resume Address */
+		if (cpsr & (1 << 5))
+		{
+			// T bit set for Thumb or ThumbEE state
+			regfile[ARM_PC] -= 4;
+		}
+		else
+		{
+			// ARM state
+			regfile[ARM_PC] -= 8;
+		}
 
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).valid;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
-		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).valid;
+		reg = armv4_5->core_cache->reg_list + 15;
+		buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+		reg->dirty = reg->valid;
+	}
 
 #if 0
 /* TODO, Move this */
@@ -688,7 +929,7 @@ static int cortex_a8_debug_entry(target_t *target)
 
 }
 
-static void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -720,13 +961,14 @@ static void cortex_a8_post_debug_entry(target_t *target)
 
 }
 
-static int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+static int cortex_a8_step(struct target *target, int current, uint32_t address,
 		int handle_breakpoints)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct breakpoint *breakpoint = NULL;
 	struct breakpoint stepbreakpoint;
+	struct reg *r;
 
 	int timeout = 100;
 
@@ -737,17 +979,14 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
 	}
 
 	/* current = 1: continue on current pc, otherwise continue at <address> */
+	r = armv4_5->core_cache->reg_list + 15;
 	if (!current)
 	{
-		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, ARM_PC).value,
-				0, 32, address);
+		buf_set_u32(r->value, 0, 32, address);
 	}
 	else
 	{
-		address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, ARM_PC).value,
-				0, 32);
+		address = buf_get_u32(r->value, 0, 32);
 	}
 
 	/* The front-end may request us not to handle breakpoints.
@@ -756,17 +995,15 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
 	 */
 	handle_breakpoints = 1;
 	if (handle_breakpoints) {
-		breakpoint = breakpoint_find(target,
-				buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, 15).value,
-			0, 32));
+		breakpoint = breakpoint_find(target, address);
 		if (breakpoint)
 			cortex_a8_unset_breakpoint(target, breakpoint);
 	}
 
 	/* Setup single step breakpoint */
 	stepbreakpoint.address = address;
-	stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
+	stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+			? 2 : 4;
 	stepbreakpoint.type = BKPT_HARD;
 	stepbreakpoint.set = 0;
 
@@ -799,30 +1036,16 @@ static int cortex_a8_step(struct target_s *target, int current, uint32_t address
 	return ERROR_OK;
 }
 
-static int cortex_a8_restore_context(target_t *target)
+static int cortex_a8_restore_context(struct target *target)
 {
-	int i;
-	uint32_t value;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
 
 	LOG_DEBUG(" ");
 
 	if (armv7a->pre_restore_context)
 		armv7a->pre_restore_context(target);
 
-	for (i = 15; i >= 0; i--)
-	{
-		if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, i).dirty)
-		{
-			value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-						armv4_5->core_mode, i).value,
-					0, 32);
-			/* TODO Check return values */
-			cortex_a8_dap_write_coreregister_u32(target, value, i);
-		}
-	}
+	arm_dpm_write_dirty_registers(&armv7a->dpm);
 
 	if (armv7a->post_restore_context)
 		armv7a->post_restore_context(target);
@@ -831,136 +1054,12 @@ static int cortex_a8_restore_context(target_t *target)
 }
 
 
-#if 0
-/*
- * Cortex-A8 Core register functions
- */
-static int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
-		armv4_5_mode_t mode, uint32_t * value)
-{
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	if ((num <= ARM_CPSR))
-	{
-		/* read a normal core register */
-		retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
-
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("JTAG failure %i", retval);
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-		LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
-	}
-	else
-	{
-		return ERROR_INVALID_ARGUMENTS;
-	}
-
-	/* Register other than r0 - r14 uses r0 for access */
-	if (num > 14)
-		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).dirty =
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 0).valid;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).dirty =
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5->core_mode, 15).valid;
-
-	return ERROR_OK;
-}
-
-static int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
-		armv4_5_mode_t mode, uint32_t value)
-{
-	int retval;
-//	uint32_t reg;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-#ifdef ARMV7_GDB_HACKS
-	/* If the LR register is being modified, make sure it will put us
-	 * in "thumb" mode, or an INVSTATE exception will occur. This is a
-	 * hack to deal with the fact that gdb will sometimes "forge"
-	 * return addresses, and doesn't set the LSB correctly (i.e., when
-	 * printing expressions containing function calls, it sets LR=0.) */
-
-	if (num == 14)
-		value |= 0x01;
-#endif
-
-	if ((num <= ARM_CPSR))
-	{
-		retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("JTAG failure %i", retval);
-			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, num).dirty =
-				ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-					armv4_5->core_mode, num).valid;
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-		LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
-	}
-	else
-	{
-		return ERROR_INVALID_ARGUMENTS;
-	}
-
-	return ERROR_OK;
-}
-#endif
-
-
-static int cortex_a8_read_core_reg(struct target_s *target, int num,
-		enum armv4_5_mode mode)
-{
-	uint32_t value;
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	cortex_a8_dap_read_coreregister_u32(target, &value, num);
-
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
-	}
-
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
-			mode, num).value, 0, 32, value);
-
-	return ERROR_OK;
-}
-
-int cortex_a8_write_core_reg(struct target_s *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
-{
-	int retval;
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	cortex_a8_dap_write_coreregister_u32(target, value, num);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
-	}
-
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-
-	return ERROR_OK;
-}
-
-
 /*
  * Cortex-A8 Breakpoint and watchpoint fuctions
  */
 
 /* Setup hardware Breakpoint Register Pair */
-static int cortex_a8_set_breakpoint(struct target_s *target,
+static int cortex_a8_set_breakpoint(struct target *target,
 		struct breakpoint *breakpoint, uint8_t matchmode)
 {
 	int retval;
@@ -984,7 +1083,7 @@ static int cortex_a8_set_breakpoint(struct target_s *target,
 		if (brp_i >= cortex_a8->brp_num)
 		{
 			LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
-			exit(-1);
+			return ERROR_FAIL;
 		}
 		breakpoint->set = brp_i + 1;
 		if (breakpoint->length == 2)
@@ -1035,7 +1134,7 @@ static int cortex_a8_set_breakpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int cortex_a8_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	int retval;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -1093,7 +1192,8 @@ static int cortex_a8_unset_breakpoint(struct target_s *target, struct breakpoint
 	return ERROR_OK;
 }
 
-int cortex_a8_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
@@ -1110,7 +1210,7 @@ int cortex_a8_add_breakpoint(struct target_s *target, struct breakpoint *breakpo
 	return ERROR_OK;
 }
 
-static int cortex_a8_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
+static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
@@ -1140,29 +1240,53 @@ static int cortex_a8_remove_breakpoint(struct target_s *target, struct breakpoin
  * Cortex-A8 Reset fuctions
  */
 
-static int cortex_a8_assert_reset(target_t *target)
+static int cortex_a8_assert_reset(struct target *target)
 {
+	struct armv7a_common *armv7a = target_to_armv7a(target);
 
 	LOG_DEBUG(" ");
 
+	/* FIXME when halt is requested, make it work somehow... */
+
+	/* Issue some kind of warm reset. */
+	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+		target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+	} else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+		/* REVISIT handle "pulls" cases, if there's
+		 * hardware that needs them to work.
+		 */
+		jtag_add_reset(0, 1);
+	} else {
+		LOG_ERROR("%s: how to reset?", target_name(target));
+		return ERROR_FAIL;
+	}
+
 	/* registers are now invalid */
-	armv4_5_invalidate_core_regs(target);
+	register_cache_invalidate(armv7a->armv4_5_common.core_cache);
 
 	target->state = TARGET_RESET;
 
 	return ERROR_OK;
 }
 
-static int cortex_a8_deassert_reset(target_t *target)
+static int cortex_a8_deassert_reset(struct target *target)
 {
+	int retval;
 
 	LOG_DEBUG(" ");
 
-	if (target->reset_halt)
-	{
-		int retval;
-		if ((retval = target_halt(target)) != ERROR_OK)
-			return retval;
+	/* be certain SRST is off */
+	jtag_add_reset(0, 0);
+
+	retval = cortex_a8_poll(target);
+
+	if (target->reset_halt) {
+		if (target->state != TARGET_HALTED) {
+			LOG_WARNING("%s: ran after reset and before halt ...",
+					target_name(target));
+			if ((retval = target_halt(target)) != ERROR_OK)
+				return retval;
+		}
 	}
 
 	return ERROR_OK;
@@ -1175,24 +1299,19 @@ static int cortex_a8_deassert_reset(target_t *target)
  * ap number for every access.
  */
 
-static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_read_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	int retval = ERROR_OK;
-
-	/* sanitize arguments */
-	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-		return ERROR_INVALID_ARGUMENTS;
+	int retval = ERROR_INVALID_ARGUMENTS;
 
 	/* cortex_a8 handles unaligned memory access */
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
 
-	switch (size)
-	{
+	if (count && buffer) {
+		switch (size) {
 		case 4:
 			retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
 			break;
@@ -1202,30 +1321,23 @@ static int cortex_a8_read_memory(struct target_s *target, uint32_t address,
 		case 1:
 			retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
+		}
 	}
 
 	return retval;
 }
 
-int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_write_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
-
-	int retval;
-
-	/* sanitize arguments */
-	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
-		return ERROR_INVALID_ARGUMENTS;
+	int retval = ERROR_INVALID_ARGUMENTS;
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
 
-	switch (size)
-	{
+	if (count && buffer) {
+		switch (size) {
 		case 4:
 			retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
 			break;
@@ -1235,12 +1347,10 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
 		case 1:
 			retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
+		}
 	}
 
-	if (target->state == TARGET_HALTED)
+	if (retval == ERROR_OK && target->state == TARGET_HALTED)
 	{
 		/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
 		/* invalidate I-Cache */
@@ -1264,7 +1374,7 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
 	return retval;
 }
 
-static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
 		uint32_t count, uint8_t *buffer)
 {
 	return cortex_a8_write_memory(target, address, 4, count, buffer);
@@ -1296,12 +1406,12 @@ static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_
 
 static int cortex_a8_handle_target_request(void *priv)
 {
-	target_t *target = priv;
-	if (!target->type->examined)
-		return ERROR_OK;
+	struct target *target = priv;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
+	if (!target_was_examined(target))
+		return ERROR_OK;
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
 
@@ -1336,7 +1446,7 @@ static int cortex_a8_handle_target_request(void *priv)
  * Cortex-A8 target information and configuration
  */
 
-static int cortex_a8_examine(struct target_s *target)
+static int cortex_a8_examine_first(struct target *target)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1388,6 +1498,8 @@ static int cortex_a8_examine(struct target_s *target)
 	LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
 	LOG_DEBUG("didr = 0x%08" PRIx32, didr);
 
+	cortex_a8_dpm_setup(cortex_a8, didr);
+
 	/* Setup Breakpoint Register Pairs */
 	cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
 	cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
@@ -1421,10 +1533,21 @@ static int cortex_a8_examine(struct target_s *target)
 	LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
 			cortex_a8->brp_num , cortex_a8->wrp_num);
 
-	/* Configure core debug access */
-	cortex_a8_init_debug_access(target);
+	target_set_examined(target);
+	return ERROR_OK;
+}
+
+static int cortex_a8_examine(struct target *target)
+{
+	int retval = ERROR_OK;
 
-	target->type->examined = 1;
+	/* don't re-probe hardware after each reset */
+	if (!target_was_examined(target))
+		retval = cortex_a8_examine_first(target);
+
+	/* Configure core debug access */
+	if (retval == ERROR_OK)
+		retval = cortex_a8_init_debug_access(target);
 
 	return retval;
 }
@@ -1433,43 +1556,28 @@ static int cortex_a8_examine(struct target_s *target)
  *	Cortex-A8 target creation and initialization
  */
 
-static void cortex_a8_build_reg_cache(target_t *target)
-{
-	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
-}
-
-
-static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
-		struct target_s *target)
+static int cortex_a8_init_target(struct command_context *cmd_ctx,
+		struct target *target)
 {
-	cortex_a8_build_reg_cache(target);
+	/* examine_first() does a bunch of this */
 	return ERROR_OK;
 }
 
-int cortex_a8_init_arch_info(target_t *target,
+static int cortex_a8_init_arch_info(struct target *target,
 		struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
 {
-	struct arm *armv4_5;
-	struct armv7a_common *armv7a;
-
-	armv7a = &cortex_a8->armv7a_common;
-	armv4_5 = &armv7a->armv4_5_common;
+	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 	/* Setup struct cortex_a8_common */
 	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
 	armv4_5->arch_info = armv7a;
 
-	armv4_5_init_arch_info(target, armv4_5);
-
 	/* prepare JTAG information for the new target */
 	cortex_a8->jtag_info.tap = tap;
 	cortex_a8->jtag_info.scann_size = 4;
-LOG_DEBUG(" ");
+
 	swjdp->dp_select_value = -1;
 	swjdp->ap_csw_value = -1;
 	swjdp->ap_tar_value = -1;
@@ -1503,21 +1611,16 @@ LOG_DEBUG(" ");
 
 //	arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
-	armv4_5->read_core_reg = cortex_a8_read_core_reg;
-	armv4_5->write_core_reg = cortex_a8_write_core_reg;
-//	armv4_5->full_context = arm7_9_full_context;
-
-//	armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
-//	armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-//	armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-//	armv4_5->write_core_reg = armv4_5_write_core_reg;
+	/* REVISIT v7a setup should be in a v7a-specific routine */
+	armv4_5_init_arch_info(target, armv4_5);
+	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 
 	return ERROR_OK;
 }
 
-static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
 
@@ -1528,46 +1631,53 @@ static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
 
 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
-	return armv4_5_handle_cache_info_command(cmd_ctx,
+	return armv4_5_handle_cache_info_command(CMD_CTX,
 			&armv7a->armv4_5_mmu.armv4_5_cache);
 }
 
 
 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 {
-	target_t *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(CMD_CTX);
 
 	cortex_a8_init_debug_access(target);
 
 	return ERROR_OK;
 }
 
-
-static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
-{
-	command_t *cortex_a8_cmd;
-	int retval = ERROR_OK;
-
-	armv4_5_register_commands(cmd_ctx);
-	armv7a_register_commands(cmd_ctx);
-
-	cortex_a8_cmd =	register_command(cmd_ctx, NULL, "cortex_a8",
-			NULL, COMMAND_ANY,
-			"cortex_a8 specific commands");
-
-	register_command(cmd_ctx, cortex_a8_cmd, "cache_info",
-			cortex_a8_handle_cache_info_command, COMMAND_EXEC,
-			"display information about target caches");
-
-	register_command(cmd_ctx, cortex_a8_cmd, "dbginit",
-			cortex_a8_handle_dbginit_command, COMMAND_EXEC,
-			"Initialize core debug");
-
-	return retval;
-}
+static const struct command_registration cortex_a8_exec_command_handlers[] = {
+	{
+		.name = "cache_info",
+		.handler = &cortex_a8_handle_cache_info_command,
+		.mode = COMMAND_EXEC,
+		.help = "display information about target caches",
+	},
+	{
+		.name = "dbginit",
+		.handler = &cortex_a8_handle_dbginit_command,
+		.mode = COMMAND_EXEC,
+		.help = "Initialize core debug",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration cortex_a8_command_handlers[] = {
+	{
+		.chain = arm_command_handlers,
+	},
+	{
+		.chain = armv7a_command_handlers,
+	},
+	{
+		.name = "cortex_a8",
+		.mode = COMMAND_ANY,
+		.help = "Cortex-A8 command group",
+		.chain = cortex_a8_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
 
 struct target_type cortexa8_target = {
 	.name = "cortex_a8",
@@ -1590,8 +1700,9 @@ struct target_type cortexa8_target = {
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
 	.bulk_write_memory = cortex_a8_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.checksum_memory = arm_checksum_memory,
+	.blank_check_memory = arm_blank_check_memory,
 
 	.run_algorithm = armv4_5_run_algorithm,
 
@@ -1600,7 +1711,7 @@ struct target_type cortexa8_target = {
 	.add_watchpoint = NULL,
 	.remove_watchpoint = NULL,
 
-	.register_commands = cortex_a8_register_commands,
+	.commands = cortex_a8_command_handlers,
 	.target_create = cortex_a8_target_create,
 	.init_target = cortex_a8_init_target,
 	.examine = cortex_a8_examine,