X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=71de3b799267e251a92711ea7482d63b02cea1a6;hp=168fe127ddb68b960bce21dcd50d9964be835397;hb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;hpb=a1777fc6493b4c1879ef133c565327212859d37c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 168fe127dd..71de3b7992 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -648,7 +648,7 @@ static int cortex_a8_debug_entry(struct target *target)
 	dap_ap_select(swjdp, swjdp_debugap);
 	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
-	armv4_5->core_mode = cpsr & 0x1F;
+	arm_set_cpsr(armv4_5, cpsr);
 
 	i = (cpsr >> 5) & 1;	/* T */
 	i |= (cpsr >> 23) & 1;	/* J << 1 */
@@ -674,11 +674,6 @@ static int cortex_a8_debug_entry(struct target *target)
 	}
 
 	/* update cache */
-	reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
-	buf_set_u32(reg->value, 0, 32, cpsr);
-	reg->valid = 1;
-	reg->dirty = 0;
-
 	for (i = 0; i <= ARM_PC; i++)
 	{
 		reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
@@ -877,9 +872,9 @@ static int cortex_a8_restore_context(struct target *target)
 
 		/* write dirty non-{R0,CPSR} registers sharing the same mode */
 		for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
-			struct armv4_5_core_reg *reg;
+			struct arm_reg *reg;
 
-			if (!r->dirty || i == ARMV4_5_CPSR)
+			if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
 				continue;
 			reg = r->arch_info;
 
@@ -915,7 +910,7 @@ static int cortex_a8_restore_context(struct target *target)
 	} while (flushed);
 
 	/* now flush CPSR if needed ... */
-	r = cache->reg_list + ARMV4_5_CPSR;
+	r = armv7a->armv4_5_common.cpsr;
 	if (flush_cpsr || r->dirty) {
 		value = buf_get_u32(r->value, 0, 32);
 		cortex_a8_dap_write_coreregister_u32(target, value, 16);
@@ -1018,16 +1013,16 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 #endif
 
 
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value);
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value);
 
-static int cortex_a8_read_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode)
+static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode)
 {
 	uint32_t value;
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
+	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
 
@@ -1042,10 +1037,10 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
+			cpsr_r = armv4_5->cpsr;
+			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+			cortex_a8_write_core_reg(target, cpsr_r,
+					16, ARMV4_5_MODE_ANY, mode);
 		}
 	}
 
@@ -1066,24 +1061,23 @@ static int cortex_a8_read_core_reg(struct target *target, int num,
 	cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
 	retval = jtag_execute_queue();
 	if (retval == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
 		r->valid = 1;
 		r->dirty = 0;
 		buf_set_u32(r->value, 0, 32, value);
 	}
 
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	if (cpsr_r)
+		cortex_a8_write_core_reg(target, cpsr_r,
+				16, ARMV4_5_MODE_ANY, cpsr);
 	return retval;
 }
 
-static int cortex_a8_write_core_reg(struct target *target, int num,
-		enum armv4_5_mode mode, uint32_t value)
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+		int num, enum armv4_5_mode mode, uint32_t value)
 {
 	int retval;
 	struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
-	struct reg_cache *cache = armv4_5->core_cache;
+	struct reg *cpsr_r = NULL;
 	uint32_t cpsr = 0;
 	unsigned cookie = num;
 
@@ -1098,10 +1092,10 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
 			mode = ARMV4_5_MODE_ANY;
 
 		if (mode != ARMV4_5_MODE_ANY) {
-			cpsr = buf_get_u32(cache ->reg_list[ARMV4_5_CPSR]
-					.value, 0, 32);
-			cortex_a8_write_core_reg(target, 16,
-					ARMV4_5_MODE_ANY, mode);
+			cpsr_r = armv4_5->cpsr;
+			cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+			cortex_a8_write_core_reg(target, cpsr_r,
+					16, ARMV4_5_MODE_ANY, mode);
 		}
 	}
 
@@ -1122,15 +1116,14 @@ static int cortex_a8_write_core_reg(struct target *target, int num,
 
 	cortex_a8_dap_write_coreregister_u32(target, value, cookie);
 	if ((retval = jtag_execute_queue()) == ERROR_OK) {
-		struct reg *r = &ARMV4_5_CORE_REG_MODE(cache, mode, num);
-
 		buf_set_u32(r->value, 0, 32, value);
 		r->valid = 1;
 		r->dirty = 0;
 	}
 
-	if (cpsr)
-		cortex_a8_write_core_reg(target, 16, ARMV4_5_MODE_ANY, cpsr);
+	if (cpsr_r)
+		cortex_a8_write_core_reg(target, cpsr_r,
+				16, ARMV4_5_MODE_ANY, cpsr);
 	return retval;
 }
 
@@ -1619,7 +1612,6 @@ static void cortex_a8_build_reg_cache(struct target *target)
 	armv4_5->core_type = ARM_MODE_MON;
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
-	armv4_5->core_cache = (*cache_p);
 }