X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=3ce861c4529c532870c4c0a200fcbc08232896b7;hp=dcf246fa52819c1a42d4496e742071553a0a94bd;hb=cfc4d5c6b7b6f8f82dc5bbf3ee661c179814666e;hpb=56b346447bb9799640ef328d4d867168be813119 diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index dcf246fa52..3ce861c452 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -40,74 +40,17 @@ #include "target_request.h" #include "target_type.h" -/* cli handling */ -int cortex_a8_register_commands(struct command_context_s *cmd_ctx); - -/* forward declarations */ -int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp); -int cortex_a8_init_target(struct command_context_s *cmd_ctx, - struct target_s *target); -int cortex_a8_examine(struct target_s *target); -int cortex_a8_poll(target_t *target); -int cortex_a8_halt(target_t *target); -int cortex_a8_resume(struct target_s *target, int current, uint32_t address, - int handle_breakpoints, int debug_execution); -int cortex_a8_step(struct target_s *target, int current, uint32_t address, - int handle_breakpoints); -int cortex_a8_debug_entry(target_t *target); -int cortex_a8_restore_context(target_t *target); -int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, - uint32_t count, uint8_t *buffer); -int cortex_a8_set_breakpoint(struct target_s *target, +static int cortex_a8_poll(target_t *target); +static int cortex_a8_debug_entry(target_t *target); +static int cortex_a8_restore_context(target_t *target); +static int cortex_a8_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint, uint8_t matchmode); -int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_unset_breakpoint(struct target_s *target, + breakpoint_t *breakpoint); +static int cortex_a8_dap_read_coreregister_u32(target_t *target, uint32_t *value, int regnum); -int cortex_a8_dap_write_coreregister_u32(target_t *target, +static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum); - -target_type_t cortexa8_target = -{ - .name = "cortex_a8", - - .poll = cortex_a8_poll, - .arch_state = armv7a_arch_state, - - .target_request_data = NULL, - - .halt = cortex_a8_halt, - .resume = cortex_a8_resume, - .step = cortex_a8_step, - - .assert_reset = NULL, - .deassert_reset = NULL, - .soft_reset_halt = NULL, - -// .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = cortex_a8_read_memory, - .write_memory = cortex_a8_write_memory, - .bulk_write_memory = cortex_a8_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = cortex_a8_add_breakpoint, - .remove_breakpoint = cortex_a8_remove_breakpoint, - .add_watchpoint = NULL, - .remove_watchpoint = NULL, - - .register_commands = cortex_a8_register_commands, - .target_create = cortex_a8_target_create, - .init_target = cortex_a8_init_target, - .examine = cortex_a8_examine, - .quit = NULL -}; - /* * FIXME do topology discovery using the ROM; don't * assume this is an OMAP3. @@ -119,78 +62,80 @@ target_type_t cortexa8_target = /* * Cortex-A8 Basic debug access, very low level assumes state is saved */ -int cortex_a8_init_debug_access(target_t *target) +static int cortex_a8_init_debug_access(target_t *target) { -#if 0 -# Unlocking the debug registers for modification -mww 0x54011FB0 0xC5ACCE55 4 - -# Clear Sticky Power Down status Bit to enable access to -# the registers in the Core Power Domain -mdw 0x54011314 -# Check that it is cleared -mdw 0x54011314 -# Now we can read Core Debug Registers at offset 0x080 -mdw 0x54011080 4 -# We can also read RAM. -mdw 0x80000000 32 - -mdw 0x5401d030 -mdw 0x54011FB8 - -# Set DBGEN line for hardware debug (OMAP35xx) -mww 0x5401d030 0x00002000 - -#Check AUTHSTATUS -mdw 0x54011FB8 - -# Instr enable -mww 0x54011088 0x2000 -mdw 0x54011080 4 -#endif - return ERROR_OK; + struct armv7a_common_s *armv7a = target_to_armv7a(target); + swjdp_common_t *swjdp = &armv7a->swjdp_info; + + int retval; + uint32_t dummy; + + LOG_DEBUG(" "); + + /* Unlocking the debug registers for modification */ + /* The debugport might be uninitialised so try twice */ + retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); + if (retval != ERROR_OK) + mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); + /* Clear Sticky Power Down status Bit in PRSR to enable access to + the registers in the Core Power Domain */ + retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); + /* Enabling of instruction execution in debug mode is done in debug_entry code */ + + /* Resync breakpoint registers */ + + /* Since this is likley called from init or reset, update targtet state information*/ + cortex_a8_poll(target); + + return retval; } int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) { uint32_t dscr; - int retvalue; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + int retval; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode); do { - retvalue = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); + return retval; + } } - while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */ + while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ - mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode); + mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); do { - retvalue = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register"); + return retval; + } } - while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */ + while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ - return retvalue; + return retval; } /************************************************************************** Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ -int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, +static int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, uint32_t * regfile) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; cortex_a8_dap_read_coreregister_u32(target, regfile, 0); @@ -203,13 +148,11 @@ int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address, return retval; } -int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, +static int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2)); @@ -218,55 +161,83 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP, /* Read DCCTX */ retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); + armv7a->debug_base + CPUDBG_DTRTX, value); return retval; } -int cortex_a8_write_cp(target_t *target, uint32_t value, +static int cortex_a8_write_cp(target_t *target, uint32_t value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) -/* TODO Fix this */ { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + uint32_t dscr; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; + LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); + + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + retval = mem_ap_write_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value); + armv7a->debug_base + CPUDBG_DTRRX, value); /* Move DTRRX to r0 */ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); - cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, 0, 0, 0, 5, 0)); + cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2)); return retval; } -int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2); } -int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2, +static int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2); } -int cortex_a8_dap_read_coreregister_u32(target_t *target, +static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +{ + if (cpnum!=15) + { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value); +} + +static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +{ + if (cpnum!=15) + { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value); +} + + + +static int cortex_a8_dap_read_coreregister_u32(target_t *target, uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + uint32_t dscr; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - if (reg > 16) return retval; @@ -286,30 +257,46 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0)); } - /* Read DCCTX */ + /* Read DTRRTX */ + do + { + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + } + while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */ + retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); -// retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value); + armv7a->debug_base + CPUDBG_DTRTX, value); return retval; } -int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum) +static int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + uint32_t dscr; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; + LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); + + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + if (Rd > 16) return retval; /* Write to DCCRX */ retval = mem_ap_write_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value); + armv7a->debug_base + CPUDBG_DTRRX, value); if (Rd < 15) { @@ -332,27 +319,35 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r return retval; } +/* Write to memory mapped registers directly with no cache or mmu handling */ +static int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value) +{ + int retval; + struct armv7a_common_s *armv7a = target_to_armv7a(target); + swjdp_common_t *swjdp = &armv7a->swjdp_info; + + retval = mem_ap_write_atomic_u32(swjdp, address, value); + + return retval; +} + /* * Cortex-A8 Run control */ -int cortex_a8_poll(target_t *target) +static int cortex_a8_poll(target_t *target) { int retval = ERROR_OK; uint32_t dscr; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; swjdp_common_t *swjdp = &armv7a->swjdp_info; - - enum target_state prev_target_state = target->state; - uint8_t saved_apsel = dap_ap_get_select(swjdp); + dap_ap_select(swjdp, swjdp_debugap); retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) { dap_ap_select(swjdp, saved_apsel); @@ -405,38 +400,53 @@ int cortex_a8_poll(target_t *target) return retval; } -int cortex_a8_halt(target_t *target) +static int cortex_a8_halt(target_t *target) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + uint32_t dscr; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; - uint8_t saved_apsel = dap_ap_get_select(swjdp); dap_ap_select(swjdp, swjdp_debugap); - /* Perhaps we should do a read-modify-write here */ + /* + * Tell the core to be halted by writing DRCR with 0x1 + * and then wait for the core to be halted. + */ + retval = mem_ap_write_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DRCR, 0x1); + + /* + * enter halting debug mode + */ + mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); retval = mem_ap_write_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1); + armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE)); + + if (retval != ERROR_OK) + goto out; + + do { + mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0); target->debug_reason = DBG_REASON_DBGRQ; - dap_ap_select(swjdp, saved_apsel); +out: + dap_ap_select(swjdp, saved_apsel); return retval; } -int cortex_a8_resume(struct target_s *target, int current, +static int cortex_a8_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; swjdp_common_t *swjdp = &armv7a->swjdp_info; // breakpoint_t *breakpoint = NULL; - uint32_t resume_pc; + uint32_t resume_pc, dscr; uint8_t saved_apsel = dap_ap_get_select(swjdp); dap_ap_select(swjdp, swjdp_debugap); @@ -480,10 +490,17 @@ int cortex_a8_resume(struct target_s *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - if (!(cortex_a8->cpudbg_dscr & (1 << 5))) + if (armv7a->core_state == ARMV7A_STATE_ARM) { resume_pc &= 0xFFFFFFFC; } + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + if (armv7a->core_state == ARMV7A_STATE_THUMB) + { + resume_pc |= 0x1; + } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).value, @@ -510,9 +527,13 @@ int cortex_a8_resume(struct target_s *target, int current, } #endif - /* Restart core */ - /* Perhaps we should do a read-modify-write here */ - mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2); + /* Restart core and wait for it to be started */ + mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2); + + do { + mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0); target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; @@ -538,24 +559,26 @@ int cortex_a8_resume(struct target_s *target, int current, return ERROR_OK; } -int cortex_a8_debug_entry(target_t *target) +static int cortex_a8_debug_entry(target_t *target) { int i; - uint32_t regfile[16], pc, cpsr; + uint32_t regfile[16], pc, cpsr, dscr; int retval = ERROR_OK; working_area_t *regfile_working_area = NULL; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; swjdp_common_t *swjdp = &armv7a->swjdp_info; - if (armv7a->pre_debug_entry) - armv7a->pre_debug_entry(target); - LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); + /* Enable the ITR execution once we are in debug mode */ + mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + dscr |= (1 << DSCR_EXT_INT_EN); + retval = mem_ap_write_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, dscr); + /* Examine debug reason */ switch ((cortex_a8->cpudbg_dscr >> 2)&0xF) { @@ -576,7 +599,6 @@ int cortex_a8_debug_entry(target_t *target) } /* Examine target state and mode */ - dap_ap_select(swjdp, swjdp_memoryap); if (cortex_a8->fast_reg_read) target_alloc_working_area(target, 64, ®file_working_area); @@ -589,6 +611,7 @@ int cortex_a8_debug_entry(target_t *target) } else { + dap_ap_select(swjdp, swjdp_memoryap); cortex_a8_read_regs_through_mem(target, regfile_working_area->address, regfile); dap_ap_select(swjdp, swjdp_memoryap); @@ -600,7 +623,8 @@ int cortex_a8_debug_entry(target_t *target) dap_ap_select(swjdp, swjdp_debugap); LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); - armv4_5->core_mode = cpsr & 0x3F; + armv4_5->core_mode = cpsr & 0x1F; + armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM; for (i = 0; i <= ARM_PC; i++) { @@ -619,8 +643,7 @@ int cortex_a8_debug_entry(target_t *target) ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; /* Fixup PC Resume Address */ - /* TODO Her we should use arch->core_state */ - if (cortex_a8->cpudbg_dscr & (1 << 5)) + if (armv7a->core_state == ARMV7A_STATE_THUMB) { // T bit set for Thumb or ThumbEE state regfile[ARM_PC] -= 4; @@ -665,12 +688,10 @@ int cortex_a8_debug_entry(target_t *target) } -void cortex_a8_post_debug_entry(target_t *target) +static void cortex_a8_post_debug_entry(target_t *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; // cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0); /* examine cp15 control reg */ @@ -699,13 +720,11 @@ void cortex_a8_post_debug_entry(target_t *target) } -int cortex_a8_step(struct target_s *target, int current, uint32_t address, +static int cortex_a8_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; breakpoint_t *breakpoint = NULL; breakpoint_t stepbreakpoint; @@ -747,7 +766,7 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; - stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4; + stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -780,14 +799,12 @@ int cortex_a8_step(struct target_s *target, int current, uint32_t address, return ERROR_OK; } -int cortex_a8_restore_context(target_t *target) +static int cortex_a8_restore_context(target_t *target) { int i; uint32_t value; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); + struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common; LOG_DEBUG(" "); @@ -814,16 +831,15 @@ int cortex_a8_restore_context(target_t *target) } +#if 0 /* * Cortex-A8 Core register functions */ - -int cortex_a8_load_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_load_core_reg_u32(struct target_s *target, int num, armv4_5_mode_t mode, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if ((num <= ARM_CPSR)) { @@ -856,14 +872,12 @@ int cortex_a8_load_core_reg_u32(struct target_s *target, int num, return ERROR_OK; } -int cortex_a8_store_core_reg_u32(struct target_s *target, int num, +static int cortex_a8_store_core_reg_u32(struct target_s *target, int num, armv4_5_mode_t mode, uint32_t value) { int retval; // uint32_t reg; - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -897,14 +911,16 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num, return ERROR_OK; } +#endif -int cortex_a8_read_core_reg(struct target_s *target, int num, +static int cortex_a8_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { uint32_t value; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + cortex_a8_dap_read_coreregister_u32(target, &value, num); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -924,7 +940,7 @@ int cortex_a8_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); cortex_a8_dap_write_coreregister_u32(target, value, num); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -944,19 +960,15 @@ int cortex_a8_write_core_reg(struct target_s *target, int num, */ /* Setup hardware Breakpoint Register Pair */ -int cortex_a8_set_breakpoint(struct target_s *target, +static int cortex_a8_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint, uint8_t matchmode) { int retval; int brp_i=0; uint32_t control; uint8_t byte_addr_select = 0x0F; - - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; cortex_a8_brp_t * brp_list = cortex_a8->brp_list; if (breakpoint->set) @@ -985,10 +997,10 @@ int cortex_a8_set_breakpoint(struct target_s *target, brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].control = control; - target_write_u32(target, OMAP3530_DEBUG_BASE + cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); - target_write_u32(target, OMAP3530_DEBUG_BASE + cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].control); LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, @@ -1023,13 +1035,11 @@ int cortex_a8_set_breakpoint(struct target_s *target, return ERROR_OK; } -int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; cortex_a8_brp_t * brp_list = cortex_a8->brp_list; if (!breakpoint->set) @@ -1051,10 +1061,10 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; - target_write_u32(target, OMAP3530_DEBUG_BASE + cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].control); - target_write_u32(target, OMAP3530_DEBUG_BASE + cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); } @@ -1085,10 +1095,7 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { @@ -1103,12 +1110,9 @@ int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); #if 0 /* It is perfectly possible to remove brakpoints while the taget is running */ @@ -1136,6 +1140,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin * Cortex-A8 Reset fuctions */ +static int cortex_a8_assert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + /* registers are now invalid */ + armv4_5_invalidate_core_regs(target); + + target->state = TARGET_RESET; + + return ERROR_OK; +} + +static int cortex_a8_deassert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + } + + return ERROR_OK; +} /* * Cortex-A8 Memory access @@ -1144,12 +1175,10 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin * ap number for every access. */ -int cortex_a8_read_memory(struct target_s *target, uint32_t address, +static int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; int retval = ERROR_OK; @@ -1184,9 +1213,7 @@ int cortex_a8_read_memory(struct target_s *target, uint32_t address, int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; int retval; @@ -1213,17 +1240,38 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, exit(-1); } + if (target->state == TARGET_HALTED) + { + /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ + /* invalidate I-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + { + /* Invalidate ICache single entry with MVA, repeat this for all cache + lines in the address range, Cortex-A8 has fixed 64 byte line length */ + /* Invalidate Cache single entry with MVA to PoU */ + for (uint32_t cacheline=address; cachelinewrite_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ + } + /* invalidate D-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) + { + /* Invalidate Cache single entry with MVA to PoC */ + for (uint32_t cacheline=address; cachelinewrite_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + } + } + return retval; } -int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, +static int cortex_a8_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } -int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) { #if 0 u16 dcrdr; @@ -1246,16 +1294,14 @@ int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) } -int cortex_a8_handle_target_request(void *priv) +static int cortex_a8_handle_target_request(void *priv) { target_t *target = priv; if (!target->type->examined) return ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); swjdp_common_t *swjdp = &armv7a->swjdp_info; - if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1290,49 +1336,48 @@ int cortex_a8_handle_target_request(void *priv) * Cortex-A8 target information and configuration */ -int cortex_a8_examine(struct target_s *target) +static int cortex_a8_examine(struct target_s *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; - cortex_a8_common_t *cortex_a8 = armv7a->arch_info; + struct cortex_a8_common_s *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common_s *armv7a = &cortex_a8->armv7a_common; swjdp_common_t *swjdp = &armv7a->swjdp_info; - - int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; LOG_DEBUG("TODO"); + /* Here we shall insert a proper ROM Table scan */ + armv7a->debug_base = OMAP3530_DEBUG_BASE; + /* We do one extra read to ensure DAP is configured, * we call ahbap_debugport_init(swjdp) instead */ ahbap_debugport_init(swjdp); - mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid); + mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if ((retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid)) != ERROR_OK) + armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) { LOG_DEBUG("Examine failed"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) + armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) { LOG_DEBUG("Examine failed"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) + armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) { LOG_DEBUG("Examine failed"); return retval; } if ((retval = mem_ap_read_atomic_u32(swjdp, - OMAP3530_DEBUG_BASE + CPUDBG_DIDR, &didr)) != ERROR_OK) + armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK) { LOG_DEBUG("Examine failed"); return retval; @@ -1376,6 +1421,9 @@ int cortex_a8_examine(struct target_s *target) LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs", cortex_a8->brp_num , cortex_a8->wrp_num); + /* Configure core debug access */ + cortex_a8_init_debug_access(target); + target->type->examined = 1; return retval; @@ -1385,18 +1433,17 @@ int cortex_a8_examine(struct target_s *target) * Cortex-A8 target creation and initialization */ -void cortex_a8_build_reg_cache(target_t *target) +static void cortex_a8_build_reg_cache(target_t *target) { reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); } -int cortex_a8_init_target(struct command_context_s *cmd_ctx, +static int cortex_a8_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { cortex_a8_build_reg_cache(target); @@ -1415,8 +1462,6 @@ int cortex_a8_init_arch_info(target_t *target, /* Setup cortex_a8_common_t */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; - cortex_a8->arch_info = NULL; - armv7a->arch_info = cortex_a8; armv4_5->arch_info = armv7a; armv4_5_init_arch_info(target, armv4_5); @@ -1440,7 +1485,6 @@ LOG_DEBUG(" "); /* register arch-specific functions */ armv7a->examine_debug_reason = NULL; - armv7a->pre_debug_entry = NULL; armv7a->post_debug_entry = cortex_a8_post_debug_entry; armv7a->pre_restore_context = NULL; @@ -1473,7 +1517,7 @@ LOG_DEBUG(" "); return ERROR_OK; } -int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) { cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t)); @@ -1482,19 +1526,27 @@ int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } -static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(cortex_a8_handle_cache_info_command) { target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; - armv7a_common_t *armv7a = armv4_5->arch_info; + struct armv7a_common_s *armv7a = target_to_armv7a(target); return armv4_5_handle_cache_info_command(cmd_ctx, &armv7a->armv4_5_mmu.armv4_5_cache); } -int cortex_a8_register_commands(struct command_context_s *cmd_ctx) +COMMAND_HANDLER(cortex_a8_handle_dbginit_command) +{ + target_t *target = get_current_target(cmd_ctx); + + cortex_a8_init_debug_access(target); + + return ERROR_OK; +} + + +static int cortex_a8_register_commands(struct command_context_s *cmd_ctx) { command_t *cortex_a8_cmd; int retval = ERROR_OK; @@ -1510,5 +1562,48 @@ int cortex_a8_register_commands(struct command_context_s *cmd_ctx) cortex_a8_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); + register_command(cmd_ctx, cortex_a8_cmd, "dbginit", + cortex_a8_handle_dbginit_command, COMMAND_EXEC, + "Initialize core debug"); + return retval; } + +target_type_t cortexa8_target = { + .name = "cortex_a8", + + .poll = cortex_a8_poll, + .arch_state = armv7a_arch_state, + + .target_request_data = NULL, + + .halt = cortex_a8_halt, + .resume = cortex_a8_resume, + .step = cortex_a8_step, + + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, + .soft_reset_halt = NULL, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = cortex_a8_read_memory, + .write_memory = cortex_a8_write_memory, + .bulk_write_memory = cortex_a8_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = cortex_a8_add_breakpoint, + .remove_breakpoint = cortex_a8_remove_breakpoint, + .add_watchpoint = NULL, + .remove_watchpoint = NULL, + + .register_commands = cortex_a8_register_commands, + .target_create = cortex_a8_target_create, + .init_target = cortex_a8_init_target, + .examine = cortex_a8_examine, + .mrc = cortex_a8_mrc, + .mcr = cortex_a8_mcr, +};