X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=c9401af7dea6f5587d3d109b14c2f8b374cc0059;hp=f81f0693fb6ff46556685a8946cfc874155b2649;hb=0c2f8b6eb8f4b379aa0c78caba73ec1ebaae8414;hpb=a7844aa4e83481a66fd5df8f33956da586d2f880 diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c old mode 100644 new mode 100755 index f81f0693fb..c9401af7de --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -14,6 +14,9 @@ * Copyright (C) 2010 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) ST-Ericsson SA 2011 * + * michel.jaouen@stericsson.com : smp minimum support * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -50,6 +53,10 @@ static int cortex_a8_debug_entry(struct target *target); static int cortex_a8_restore_context(struct target *target, bool bpwp); static int cortex_a8_set_breakpoint(struct target *target, struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_set_context_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_set_hybrid_breakpoint(struct target *target, + struct breakpoint *breakpoint); static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); static int cortex_a8_dap_read_coreregister_u32(struct target *target, @@ -59,12 +66,6 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, static int cortex_a8_mmu(struct target *target, int *enabled); static int cortex_a8_virt2phys(struct target *target, uint32_t virt, uint32_t *phys); -static int cortex_a8_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache); -static int cortex_a8_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache); -static int cortex_a8_get_ttb(struct target *target, uint32_t *result); - /* * FIXME do topology discovery using the ROM; don't @@ -75,6 +76,99 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result); #define swjdp_memoryap 0 #define swjdp_debugap 1 +/* restore cp15_control_reg at resume */ +static int cortex_a8_restore_cp15_control_reg(struct target* target) +{ + int retval = ERROR_OK; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); + + if (cortex_a8->cp15_control_reg !=cortex_a8->cp15_control_reg_curr) + { + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; + //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); + retval = armv7a->armv4_5_common.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg); + } + return retval; +} + +/* check address before cortex_a8_apb read write access with mmu on + * remove apb predictible data abort */ +static int cortex_a8_check_address(struct target *target, uint32_t address) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + uint32_t os_border = armv7a->armv7a_mmu.os_border; + if ((address < os_border) && + (armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)){ + LOG_ERROR("%x access in userspace and target in supervisor",address); + return ERROR_FAIL; + } + if ((address >= os_border) && + ( cortex_a8->curr_mode != ARM_MODE_SVC)){ + dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); + cortex_a8->curr_mode = ARM_MODE_SVC; + LOG_INFO("%x access in kernel space and target not in supervisor", + address); + return ERROR_OK; + } + if ((address < os_border) && + (cortex_a8->curr_mode == ARM_MODE_SVC)){ + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + cortex_a8->curr_mode = ARM_MODE_ANY; + } + return ERROR_OK; +} +/* modify cp15_control_reg in order to enable or disable mmu for : + * - virt2phys address conversion + * - read or write memory in phys or virt address */ +static int cortex_a8_mmu_modify(struct target *target, int enable) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); + int retval = ERROR_OK; + if (enable) + { + /* if mmu enabled at target stop and mmu not enable */ + if (!(cortex_a8->cp15_control_reg & 0x1U)) + { + LOG_ERROR("trying to enable mmu on target stopped with mmu disable"); + return ERROR_FAIL; + } + if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) + { + cortex_a8->cp15_control_reg_curr |= 0x1U; + retval = armv7a->armv4_5_common.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg_curr); + } + } + else + { + if (cortex_a8->cp15_control_reg_curr & 0x4U) + { + /* data cache is active */ + cortex_a8->cp15_control_reg_curr &= ~0x4U; + /* flush data cache armv7 function to be called */ + if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) + armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); + } + if ( (cortex_a8->cp15_control_reg_curr & 0x1U)) + { + cortex_a8->cp15_control_reg_curr &= ~0x1U; + retval = armv7a->armv4_5_common.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg_curr); + } + } + return retval; +} + /* * Cortex-A8 Basic debug access, very low level assumes state is saved */ @@ -320,6 +414,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); + if (retval != ERROR_OK) return retval; } @@ -670,7 +765,54 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) return retval; } +static struct target *get_cortex_a8(struct target *target, int32_t coreid) +{ +struct target_list *head; +struct target *curr; + + head = target->head; + while(head != (struct target_list*)NULL) + { + curr = head->target; + if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) + { + return curr; + } + head = head->next; + } + return target; +} +static int cortex_a8_halt(struct target *target); + +static int cortex_a8_halt_smp(struct target *target) +{ + int retval = 0; + struct target_list *head; + struct target *curr; + head = target->head; + while(head != (struct target_list*)NULL) + { + curr = head->target; + if ((curr != target) && (curr->state!= TARGET_HALTED)) + { + retval += cortex_a8_halt(curr); + } + head = head->next; + } + return retval; +} +static int update_halt_gdb(struct target *target) +{ + int retval = 0; + if (target->gdb_service->core[0]==-1) + { + target->gdb_service->target = target; + target->gdb_service->core[0] = target->coreid; + retval += cortex_a8_halt_smp(target); + } + return retval; +} /* * Cortex-A8 Run control @@ -684,7 +826,20 @@ static int cortex_a8_poll(struct target *target) struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; enum target_state prev_target_state = target->state; - + // toggle to another core is done by gdb as follow + // maint packet J core_id + // continue + // the next polling trigger an halt event sent to gdb + if ((target->state == TARGET_HALTED) && (target->smp) && + (target->gdb_service) && + (target->gdb_service->target==NULL) ) + { + target->gdb_service->target = + get_cortex_a8(target, target->gdb_service->core[1]); + target_call_event_callbacks(target, + TARGET_EVENT_HALTED); + return retval; + } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) @@ -706,7 +861,12 @@ static int cortex_a8_poll(struct target *target) retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - + if (target->smp) + { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } target_call_event_callbacks(target, TARGET_EVENT_HALTED); } @@ -717,6 +877,12 @@ static int cortex_a8_poll(struct target *target) retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; + if (target->smp) + { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); @@ -788,16 +954,13 @@ static int cortex_a8_halt(struct target *target) return ERROR_OK; } -static int cortex_a8_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) +static int cortex_a8_internal_restore(struct target *target, int current, + uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; int retval; - -// struct breakpoint *breakpoint = NULL; - uint32_t resume_pc, dscr; + uint32_t resume_pc; if (!debug_execution) target_free_all_working_areas(target); @@ -826,7 +989,9 @@ static int cortex_a8_resume(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32); if (!current) - resume_pc = address; + resume_pc = *address; + else + *address = resume_pc; /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address @@ -851,10 +1016,21 @@ static int cortex_a8_resume(struct target *target, int current, buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc); armv4_5->pc->dirty = 1; armv4_5->pc->valid = 1; - + /* restore dpm_mode at system halt */ + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + /* called it now before restoring context because it uses cpu + * register r0 for restoring cp15 control register */ + retval = cortex_a8_restore_cp15_control_reg(target); + if (retval != ERROR_OK) + return retval; retval = cortex_a8_restore_context(target, handle_breakpoints); if (retval != ERROR_OK) return retval; + target->debug_reason = DBG_REASON_NOTHALTED; + target->state = TARGET_RUNNING; + + /* registers are now invalid */ + register_cache_invalidate(armv4_5->core_cache); #if 0 /* the front-end may request us not to handle breakpoints */ @@ -871,8 +1047,17 @@ static int cortex_a8_resume(struct target *target, int current, } #endif + return retval; +} - /* +static int cortex_a8_internal_restart(struct target *target) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + struct adiv5_dap *swjdp = armv4_5->dap; + int retval; + uint32_t dscr; +/* * Restart core and wait for it to be started. Clear ITRen and sticky * exception flags: see ARMv7 ARM, C5.9. * @@ -894,7 +1079,8 @@ static int cortex_a8_resume(struct target *target, int current, return retval; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS); + armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | + DRCR_CLEAR_EXCEPTIONS); if (retval != ERROR_OK) return retval; @@ -920,17 +1106,66 @@ static int cortex_a8_resume(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(armv4_5->core_cache); + return ERROR_OK; +} + +static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints) +{ + int retval = 0; + struct target_list *head; + struct target *curr; + uint32_t address; + head = target->head; + while(head != (struct target_list*)NULL) + { + curr = head->target; + if ((curr != target) && (curr->state != TARGET_RUNNING)) + { + /* resume current address , not in step mode */ + retval += cortex_a8_internal_restore(curr, 1, &address, + handle_breakpoints, 0); + retval += cortex_a8_internal_restart(curr); + } + head = head->next; + + } + return retval; +} + +static int cortex_a8_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + int retval = 0; + /* dummy resume for smp toggle in order to reduce gdb impact */ + if ((target->smp) && (target->gdb_service->core[1]!=-1)) + { + /* simulate a start and halt of target */ + target->gdb_service->target = NULL; + target->gdb_service->core[0] = target->gdb_service->core[1]; + /* fake resume at next poll we play the target core[1], see poll*/ + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + return 0; + } + cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution); + if (target->smp) + { target->gdb_service->core[0] = -1; + retval = cortex_a8_restore_smp(target, handle_breakpoints); + if (retval != ERROR_OK) + return retval; + } + cortex_a8_internal_restart(target); + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc); + LOG_DEBUG("target resumed at 0x%" PRIx32, address); } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc); + LOG_DEBUG("target debug resumed at 0x%" PRIx32, address); } return ERROR_OK; @@ -1007,6 +1242,7 @@ static int cortex_a8_debug_entry(struct target *target) /* read Current PSR */ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); + /* store current cpsr */ if (retval != ERROR_OK) return retval; @@ -1080,32 +1316,21 @@ static int cortex_a8_post_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; - if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1) + if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) { - uint32_t cache_type_reg; - - /* MRC p15,0,,c0,c0,1 ; Read CP15 Cache Type Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 0, 0, /* CRn, CRm */ - &cache_type_reg); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg); - - /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */ - armv4_5_identify_cache(cache_type_reg, - &armv7a->armv4_5_mmu.armv4_5_cache); + armv7a_identify_cache(target); } - armv7a->armv4_5_mmu.mmu_enabled = + armv7a->armv7a_mmu.mmu_enabled = (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; - armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = + armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; - armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled = + armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; - + cortex_a8->curr_mode = armv7a->armv4_5_common.core_mode; + return ERROR_OK; } @@ -1286,6 +1511,141 @@ static int cortex_a8_set_breakpoint(struct target *target, return ERROR_OK; } +static int cortex_a8_set_context_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode) +{ + int retval = ERROR_FAIL; + int brp_i=0; + uint32_t control; + uint8_t byte_addr_select = 0x0F; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + + if (breakpoint->set) + { + LOG_WARNING("breakpoint already set"); + return retval ; + } + /*check available context BRPs*/ + while ((brp_list[brp_i].used || (brp_list[brp_i].type!=BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) + brp_i++ ; + + if (brp_i >= cortex_a8->brp_num) + { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; + } + + breakpoint->set = brp_i + 1; + control = ((matchmode & 0x7) << 20) + | (byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_i].used = 1; + brp_list[brp_i].value = (breakpoint->asid); + brp_list[brp_i].control = control; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if(retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if(retval != ERROR_OK) + return retval; + LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, + brp_list[brp_i].value); + return ERROR_OK; + +} + +static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint) +{ + int retval = ERROR_FAIL; + int brp_1=0; //holds the contextID pair + int brp_2=0; // holds the IVA pair + uint32_t control_CTX, control_IVA; + uint8_t CTX_byte_addr_select = 0x0F; + uint8_t IVA_byte_addr_select = 0x0F; + uint8_t CTX_machmode = 0x03; + uint8_t IVA_machmode = 0x01; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + + + + if (breakpoint->set) + { + LOG_WARNING("breakpoint already set"); + return retval ; + } + /*check available context BRPs*/ + while ((brp_list[brp_1].used || (brp_list[brp_1].type!=BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) + brp_1++ ; + + printf("brp(CTX) found num: %d \n",brp_1); + if (brp_1 >= cortex_a8->brp_num) + { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; + } + + while ((brp_list[brp_2].used || (brp_list[brp_2].type!=BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) + brp_2++ ; + + printf("brp(IVA) found num: %d \n",brp_2); + if (brp_2 >= cortex_a8->brp_num) + { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; + } + + breakpoint->set = brp_1 + 1; + breakpoint->linked_BRP= brp_2; + control_CTX = ((CTX_machmode & 0x7) << 20) + | (brp_2 << 16) + | (0 << 14) + | (CTX_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_1].used = 1; + brp_list[brp_1].value = (breakpoint->asid); + brp_list[brp_1].control = control_CTX; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].control); + if( retval != ERROR_OK ) + return retval; + + control_IVA = ((IVA_machmode & 0x7) << 20) + | (brp_1 << 16) + | (IVA_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_2].used = 1; + brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); + brp_list[brp_2].control = control_IVA; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].control); + if (retval != ERROR_OK ) + return retval; + + return ERROR_OK; +} + + static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; @@ -1301,27 +1661,81 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * if (breakpoint->type == BKPT_HARD) { - int brp_i = breakpoint->set - 1; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) + if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { - LOG_DEBUG("Invalid BRP number in breakpoint"); + int brp_i = breakpoint->set - 1; + int brp_j = breakpoint->linked_BRP; + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) + { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].used = 0; + brp_list[brp_i].value = 0; + brp_list[brp_i].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if (retval != ERROR_OK) + return retval; + if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) + { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j, + brp_list[brp_j].control, brp_list[brp_j].value); + brp_list[brp_j].used = 0; + brp_list[brp_j].value = 0; + brp_list[brp_j].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn, + brp_list[brp_j].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn, + brp_list[brp_j].value); + if (retval != ERROR_OK) + return retval; + breakpoint->linked_BRP = 0; + breakpoint->set = 0; return ERROR_OK; + } - LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); - brp_list[brp_i].used = 0; - brp_list[brp_i].value = 0; - brp_list[brp_i].control = 0; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, - brp_list[brp_i].control); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, - brp_list[brp_i].value); - if (retval != ERROR_OK) - return retval; + else + { + int brp_i = breakpoint->set - 1; + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) + { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].used = 0; + brp_list[brp_i].value = 0; + brp_list[brp_i].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if (retval != ERROR_OK) + return retval; + breakpoint->set = 0; + return ERROR_OK; + } } else { @@ -1365,6 +1779,41 @@ static int cortex_a8_add_breakpoint(struct target *target, return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ } +static int cortex_a8_add_context_breakpoint(struct target *target, + struct breakpoint *breakpoint) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) + { + LOG_INFO("no hardware breakpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (breakpoint->type == BKPT_HARD) + cortex_a8->brp_num_available--; + + return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ +} + +static int cortex_a8_add_hybrid_breakpoint(struct target *target, + struct breakpoint *breakpoint) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) + { + LOG_INFO("no hardware breakpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (breakpoint->type == BKPT_HARD) + cortex_a8->brp_num_available--; + + return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ +} + + static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); @@ -1449,140 +1898,232 @@ static int cortex_a8_deassert_reset(struct target *target) return ERROR_OK; } -/* - * Cortex-A8 Memory access - * - * This is same Cortex M3 but we must also use the correct - * ap number for every access. - */ -static int cortex_a8_read_phys_memory(struct target *target, +static int cortex_a8_write_apb_ab_memory(struct target *target, uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { - struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; - int retval = ERROR_INVALID_ARGUMENTS; - uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count); - - if (count && buffer) { + /* write memory through APB-AP */ - if ( apsel == swjdp_memoryap ) { + int retval = ERROR_COMMAND_SYNTAX_ERROR; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + int total_bytes = count * size; + int start_byte, nbytes_to_write, i; + struct reg *reg; + union _data { + uint8_t uc_a[4]; + uint32_t ui; + } data; - /* read memory through AHB-AP */ - - switch (size) { - case 4: - retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, - buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, - buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, - buffer, count, address); - break; - } + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } - } else { + reg = arm_reg_current(armv4_5, 0); + reg->dirty = 1; + reg = arm_reg_current(armv4_5, 1); + reg->dirty = 1; - /* read memory through APB-AP */ + retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); + if (retval != ERROR_OK) + return retval; - uint32_t saved_r0, saved_r1; - int nbytes = count * size; - uint32_t data; - int enabled = 0; + start_byte = address & 0x3; - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } + while (total_bytes > 0) { - retval = cortex_a8_mmu(target, &enabled); + nbytes_to_write = 4 - start_byte; + if (total_bytes < nbytes_to_write) + nbytes_to_write = total_bytes; + + if ( nbytes_to_write != 4 ) { + + /* execute instruction LDR r1, [r0] */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_LDR(1, 0), NULL); if (retval != ERROR_OK) return retval; - if (enabled) - { - LOG_WARNING("Reading physical memory through APB with MMU enabled is not yet implemented"); - return ERROR_TARGET_FAILURE; - } - - /* save registers r0 and r1, we are going to corrupt them */ - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0); + retval = cortex_a8_dap_read_coreregister_u32(target, &data.ui, 1); if (retval != ERROR_OK) return retval; + } + + for (i = 0; i < nbytes_to_write; ++i) + data.uc_a[i + start_byte] = *buffer++; - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1); - if (retval != ERROR_OK) - return retval; + retval = cortex_a8_dap_write_coreregister_u32(target, data.ui, 1); + if (retval != ERROR_OK) + return retval; - retval = cortex_a8_dap_write_coreregister_u32(target, address, 0); - if (retval != ERROR_OK) + /* execute instruction STRW r1, [r0], 1 (0xe4801004) */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0) , NULL); + if (retval != ERROR_OK) return retval; - while (nbytes > 0) { + total_bytes -= nbytes_to_write; + start_byte = 0; + } - /* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRB_IP(1, 0) , NULL); - if (retval != ERROR_OK) - return retval; + return retval; +} - retval = cortex_a8_dap_read_coreregister_u32(target, &data, 1); - if (retval != ERROR_OK) - return retval; - *buffer++ = data; - --nbytes; +static int cortex_a8_read_apb_ab_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ - } + /* read memory through APB-AP */ - /* restore corrupted registers r0 and r1 */ - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0); - if (retval != ERROR_OK) - return retval; + int retval = ERROR_COMMAND_SYNTAX_ERROR; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *armv4_5 = &armv7a->armv4_5_common; + int total_bytes = count * size; + int start_byte, nbytes_to_read, i; + struct reg *reg; + union _data { + uint8_t uc_a[4]; + uint32_t ui; + } data; - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1); - if (retval != ERROR_OK) - return retval; + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } - } + reg = arm_reg_current(armv4_5, 0); + reg->dirty = 1; + reg = arm_reg_current(armv4_5, 1); + reg->dirty = 1; + + retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); + if (retval != ERROR_OK) + return retval; + + start_byte = address & 0x3; + + while (total_bytes > 0) { + + /* execute instruction LDRW r1, [r0], 4 (0xe4901004) */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRW_IP(1, 0), NULL); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a8_dap_read_coreregister_u32(target, &data.ui, 1); + if (retval != ERROR_OK) + return retval; + + nbytes_to_read = 4 - start_byte; + if (total_bytes < nbytes_to_read) + nbytes_to_read = total_bytes; + + for (i = 0; i < nbytes_to_read; ++i) + *buffer++ = data.uc_a[i + start_byte]; + + total_bytes -= nbytes_to_read; + start_byte = 0; } return retval; } + + +/* + * Cortex-A8 Memory access + * + * This is same Cortex M3 but we must also use the correct + * ap number for every access. + */ + +static int cortex_a8_read_phys_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + int retval = ERROR_COMMAND_SYNTAX_ERROR; + uint8_t apsel = swjdp->apsel; + LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", + address, size, count); + + if (count && buffer) { + + if ( apsel == swjdp_memoryap ) { + + /* read memory through AHB-AP */ + + switch (size) { + case 4: + retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, + buffer, 4 * count, address); + break; + case 2: + retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, + buffer, 2 * count, address); + break; + case 1: + retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, + buffer, count, address); + break; + } + } else { + + /* read memory through APB-AP */ + /* disable mmu */ + retval = cortex_a8_mmu_modify(target, 0); + if (retval != ERROR_OK) return retval; + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); + } + } + return retval; +} + static int cortex_a8_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - int enabled = 0; - uint32_t virt, phys; - int retval; + int enabled = 0; + uint32_t virt, phys; + int retval; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ + LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + size, count); + if (apsel == swjdp_memoryap) { + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; - LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count); - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if(enabled) - { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys); - address = phys; - } + if(enabled) + { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; - return cortex_a8_read_phys_memory(target, address, size, count, buffer); + LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", + virt, phys); + address = phys; + } + retval = cortex_a8_read_phys_memory(target, address, size, count, buffer); + } else { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) return retval; + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); + } + return retval; } static int cortex_a8_write_phys_memory(struct target *target, @@ -1591,10 +2132,11 @@ static int cortex_a8_write_phys_memory(struct target *target, { struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; - int retval = ERROR_INVALID_ARGUMENTS; + int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count); + LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, + size, count); if (count && buffer) { @@ -1620,69 +2162,10 @@ static int cortex_a8_write_phys_memory(struct target *target, } else { /* write memory through APB-AP */ - - uint32_t saved_r0, saved_r1; - int nbytes = count * size; - uint32_t data; - int enabled = 0; - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if (enabled) - { - LOG_WARNING("Writing physical memory through APB with MMU enabled is not yet implemented"); - return ERROR_TARGET_FAILURE; - } - - /* save registers r0 and r1, we are going to corrupt them */ - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, address, 0); + retval = cortex_a8_mmu_modify(target, 0); if (retval != ERROR_OK) return retval; - - while (nbytes > 0) { - - data = *buffer++; - - retval = cortex_a8_dap_write_coreregister_u32(target, data, 1); - if (retval != ERROR_OK) - return retval; - - /* execute instruction STRB r1, [r0], 1 (0xe4c01001) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_STRB_IP(1, 0) , NULL); - if (retval != ERROR_OK) - return retval; - - --nbytes; - } - - /* restore corrupted registers r0 and r1 */ - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1); - if (retval != ERROR_OK) - return retval; - - /* we can return here without invalidating D/I-cache because */ - /* access through APB maintains cache coherency */ - return retval; + return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } } @@ -1706,7 +2189,7 @@ static int cortex_a8_write_phys_memory(struct target *target, */ /* invalidate I-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { /* ICIMVAU - Invalidate Cache single entry * with MVA to PoU @@ -1724,7 +2207,7 @@ static int cortex_a8_write_phys_memory(struct target *target, } /* invalidate D-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) + if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { /* DCIMVAC - Invalidate data Cache line * with MVA to PoC @@ -1750,27 +2233,44 @@ static int cortex_a8_write_phys_memory(struct target *target, static int cortex_a8_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { - int enabled = 0; - uint32_t virt, phys; - int retval; + int enabled = 0; + uint32_t virt, phys; + int retval; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + uint8_t apsel = swjdp->apsel; + /* cortex_a8 handles unaligned memory access */ + LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + size, count); + if (apsel == swjdp_memoryap) { - LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; + LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; - if(enabled) - { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys); - address = phys; - } + if(enabled) + { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys); + address = phys; + } - return cortex_a8_write_phys_memory(target, address, size, - count, buffer); + retval = cortex_a8_write_phys_memory(target, address, size, + count, buffer); + } + else { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) return retval; + retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); + } + return retval; } static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, @@ -1952,14 +2452,17 @@ static int cortex_a8_init_arch_info(struct target *target, struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct arm *armv4_5 = &armv7a->armv4_5_common; struct adiv5_dap *dap = &armv7a->dap; armv7a->armv4_5_common.dap = dap; /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; - armv4_5->arch_info = armv7a; + /* tap has no dap initialized */ + if (!tap->dap) + { + armv7a->armv4_5_common.dap = dap; + /* Setup struct cortex_a8_common */ /* prepare JTAG information for the new target */ cortex_a8->jtag_info.tap = tap; @@ -1967,38 +2470,31 @@ static int cortex_a8_init_arch_info(struct target *target, /* Leave (only) generic DAP stuff for debugport_init() */ dap->jtag_info = &cortex_a8->jtag_info; - dap->memaccess_tck = 80; /* Number of bits for tar autoincrement, impl. dep. at least 10 */ dap->tar_autoincr_block = (1 << 10); + dap->memaccess_tck = 80; + tap->dap = dap; + } + else + armv7a->armv4_5_common.dap = tap->dap; cortex_a8->fast_reg_read = 0; - /* Set default value */ - cortex_a8->current_address_mode = ARM_MODE_ANY; - /* register arch-specific functions */ armv7a->examine_debug_reason = NULL; armv7a->post_debug_entry = cortex_a8_post_debug_entry; armv7a->pre_restore_context = NULL; - armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1; - armv7a->armv4_5_mmu.get_ttb = cortex_a8_get_ttb; - armv7a->armv4_5_mmu.read_memory = cortex_a8_read_phys_memory; - armv7a->armv4_5_mmu.write_memory = cortex_a8_write_phys_memory; - armv7a->armv4_5_mmu.disable_mmu_caches = cortex_a8_disable_mmu_caches; - armv7a->armv4_5_mmu.enable_mmu_caches = cortex_a8_enable_mmu_caches; - armv7a->armv4_5_mmu.has_tiny_pages = 1; - armv7a->armv4_5_mmu.mmu_enabled = 0; + armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory; + // arm7_9->handle_target_request = cortex_a8_handle_target_request; /* REVISIT v7a setup should be in a v7a-specific routine */ - arm_init_arch_info(target, armv4_5); - armv7a->common_magic = ARMV7_COMMON_MAGIC; - + armv7a_init_arch_info(target, armv7a); target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target); return ERROR_OK; @@ -2011,133 +2507,6 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) return cortex_a8_init_arch_info(target, cortex_a8, target->tap); } -static int cortex_a8_get_ttb(struct target *target, uint32_t *result) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t ttb = 0, retval = ERROR_OK; - - /* current_address_mode is set inside cortex_a8_virt2phys() - where we can determine if address belongs to user or kernel */ - if(cortex_a8->current_address_mode == ARM_MODE_SVC) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - else if(cortex_a8->current_address_mode == ARM_MODE_USR) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - /* we don't know whose address is: user or kernel - we assume that if we are in kernel mode then - address belongs to kernel else if in user mode - - to user */ - else if(armv7a->armv4_5_common.core_mode == ARM_MODE_SVC) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - /* finally we don't know whose ttb to use: user or kernel */ - else - LOG_ERROR("Don't know how to get ttb for current mode!!!"); - - ttb &= 0xffffc000; - - *result = ttb; - - return ERROR_OK; -} - -static int cortex_a8_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t cp15_control; - int retval; - - /* read cp15 control register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - &cp15_control); - if (retval != ERROR_OK) - return retval; - - - if (mmu) - cp15_control &= ~0x1U; - - if (d_u_cache) - cp15_control &= ~0x4U; - - if (i_cache) - cp15_control &= ~0x1000U; - - retval = armv7a->armv4_5_common.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - cp15_control); - return retval; -} - -static int cortex_a8_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t cp15_control; - int retval; - - /* read cp15 control register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - &cp15_control); - if (retval != ERROR_OK) - return retval; - - if (mmu) - cp15_control |= 0x1U; - - if (d_u_cache) - cp15_control |= 0x4U; - - if (i_cache) - cp15_control |= 0x1000U; - - retval = armv7a->armv4_5_common.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - cp15_control); - return retval; -} static int cortex_a8_mmu(struct target *target, int *enabled) @@ -2147,36 +2516,35 @@ static int cortex_a8_mmu(struct target *target, int *enabled) return ERROR_TARGET_INVALID; } - *enabled = target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled; + *enabled = target_to_cortex_a8(target)->armv7a_common.armv7a_mmu.mmu_enabled; return ERROR_OK; } static int cortex_a8_virt2phys(struct target *target, uint32_t virt, uint32_t *phys) { - uint32_t cb; - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - // struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - - /* We assume that virtual address is separated - between user and kernel in Linux style: - 0x00000000-0xbfffffff - User space - 0xc0000000-0xffffffff - Kernel space */ - if( virt < 0xc0000000 ) /* Linux user space */ - cortex_a8->current_address_mode = ARM_MODE_USR; - else /* Linux kernel */ - cortex_a8->current_address_mode = ARM_MODE_SVC; - uint32_t ret; - int retval = armv4_5_mmu_translate_va(target, - &armv7a->armv4_5_mmu, virt, &cb, &ret); - if (retval != ERROR_OK) - return retval; - /* Reset the flag. We don't want someone else to use it by error */ - cortex_a8->current_address_mode = ARM_MODE_ANY; - - *phys = ret; - return ERROR_OK; + struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + uint8_t apsel = swjdp->apsel; + if (apsel == swjdp_memoryap) + { + uint32_t ret; + retval = armv7a_mmu_translate_va(target, + virt, &ret); + if (retval != ERROR_OK) + goto done; + *phys = ret; + } + else + { /* use this method if swjdp_memoryap not selected */ + /* mmu must be enable in order to get a correct translation */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) goto done; + retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1); + } +done: + return retval; } COMMAND_HANDLER(cortex_a8_handle_cache_info_command) @@ -2184,8 +2552,8 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command) struct target *target = get_current_target(CMD_CTX); struct armv7a_common *armv7a = target_to_armv7a(target); - return armv4_5_handle_cache_info_command(CMD_CTX, - &armv7a->armv4_5_mmu.armv4_5_cache); + return armv7a_handle_cache_info_command(CMD_CTX, + &armv7a->armv7a_mmu.armv7a_cache); } @@ -2200,6 +2568,68 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command) return cortex_a8_init_debug_access(target); } +COMMAND_HANDLER(cortex_a8_handle_smp_off_command) +{ + struct target *target = get_current_target(CMD_CTX); + /* check target is an smp target */ + struct target_list *head; + struct target *curr; + head = target->head; + target->smp = 0; + if (head != (struct target_list*)NULL) + { + while (head != (struct target_list*)NULL) + { + curr = head->target; + curr->smp = 0; + head = head->next; + } + /* fixes the target display to the debugger */ + target->gdb_service->target = target; + } + return ERROR_OK; +} + +COMMAND_HANDLER(cortex_a8_handle_smp_on_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct target_list *head; + struct target *curr; + head = target->head; + if (head != (struct target_list*)NULL) + { target->smp=1; + while (head != (struct target_list*)NULL) + { + curr = head->target; + curr->smp = 1; + head = head->next; + } + } + return ERROR_OK; +} + +COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command) +{ + struct target *target = get_current_target(CMD_CTX); + int retval = ERROR_OK; + struct target_list *head; + head = target->head; + if (head != (struct target_list*)NULL) + { + if (CMD_ARGC == 1) + { + int coreid = 0; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); + if (ERROR_OK != retval) + return retval; + target->gdb_service->core[1]=coreid; + + } + command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] + , target->gdb_service->core[1]); + } + return ERROR_OK; +} static const struct command_registration cortex_a8_exec_command_handlers[] = { { @@ -2207,13 +2637,37 @@ static const struct command_registration cortex_a8_exec_command_handlers[] = { .handler = cortex_a8_handle_cache_info_command, .mode = COMMAND_EXEC, .help = "display information about target caches", + .usage = "", }, { .name = "dbginit", .handler = cortex_a8_handle_dbginit_command, .mode = COMMAND_EXEC, .help = "Initialize core debug", + .usage = "", + }, + { .name ="smp_off", + .handler = cortex_a8_handle_smp_off_command, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "", + }, + { + .name ="smp_on", + .handler = cortex_a8_handle_smp_on_command, + .mode = COMMAND_EXEC, + .help = "Restart smp handling", + .usage = "", + }, + { + .name ="smp_gdb", + .handler = cortex_a8_handle_smp_gdb_command, + .mode = COMMAND_EXEC, + .help = "display/fix current core played to gdb", + .usage = "", }, + + COMMAND_REGISTRATION_DONE }; static const struct command_registration cortex_a8_command_handlers[] = { @@ -2227,6 +2681,7 @@ static const struct command_registration cortex_a8_command_handlers[] = { .name = "cortex_a8", .mode = COMMAND_ANY, .help = "Cortex-A8 command group", + .usage = "", .chain = cortex_a8_exec_command_handlers, }, COMMAND_REGISTRATION_DONE @@ -2261,6 +2716,8 @@ struct target_type cortexa8_target = { .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = cortex_a8_add_breakpoint, + .add_context_breakpoint = cortex_a8_add_context_breakpoint, + .add_hybrid_breakpoint = cortex_a8_add_hybrid_breakpoint, .remove_breakpoint = cortex_a8_remove_breakpoint, .add_watchpoint = NULL, .remove_watchpoint = NULL, @@ -2274,5 +2731,4 @@ struct target_type cortexa8_target = { .write_phys_memory = cortex_a8_write_phys_memory, .mmu = cortex_a8_mmu, .virt2phys = cortex_a8_virt2phys, - };