X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=8773ea1607a1019a6c778bc5e14088e2e4008259;hp=3ed2481ba957c01ff0541fb02d27cc6757165bba;hb=16065e06adac25953a63bceb0fe5bf4f2c75d6ce;hpb=e99a43a27605c174c7114478e493671875124215

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 3ed2481ba9..8773ea1607 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -425,22 +425,35 @@ static int cortex_a_instr_write_data_dcc(struct arm_dpm *dpm,
 			&dscr);
 }
 
-static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
-	uint32_t opcode, uint32_t data)
+static int cortex_a_instr_write_data_rt_dcc(struct arm_dpm *dpm,
+	uint8_t rt, uint32_t data)
 {
 	struct cortex_a_common *a = dpm_to_a(dpm);
 	uint32_t dscr = DSCR_INSTR_COMP;
 	int retval;
 
+	if (rt > 15)
+		return ERROR_TARGET_INVALID;
+
 	retval = cortex_a_write_dcc(a, data);
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
-	retval = cortex_a_exec_opcode(
+	/* DCCRX to Rt, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+	return cortex_a_exec_opcode(
 			a->armv7a_common.arm.target,
-			ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+			ARMV4_5_MRC(14, 0, rt, 0, 5, 0),
 			&dscr);
+}
+
+static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
+	uint32_t opcode, uint32_t data)
+{
+	struct cortex_a_common *a = dpm_to_a(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -482,31 +495,43 @@ static int cortex_a_instr_read_data_dcc(struct arm_dpm *dpm,
 	return cortex_a_read_dcc(a, data, &dscr);
 }
 
-
-static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
-	uint32_t opcode, uint32_t *data)
+static int cortex_a_instr_read_data_rt_dcc(struct arm_dpm *dpm,
+	uint8_t rt, uint32_t *data)
 {
 	struct cortex_a_common *a = dpm_to_a(dpm);
 	uint32_t dscr = DSCR_INSTR_COMP;
 	int retval;
 
-	/* the opcode, writing data to R0 */
+	if (rt > 15)
+		return ERROR_TARGET_INVALID;
+
 	retval = cortex_a_exec_opcode(
 			a->armv7a_common.arm.target,
-			opcode,
+			ARMV4_5_MCR(14, 0, rt, 0, 5, 0),
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* write R0 to DCC */
+	return cortex_a_read_dcc(a, data, &dscr);
+}
+
+static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
+	uint32_t opcode, uint32_t *data)
+{
+	struct cortex_a_common *a = dpm_to_a(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	/* the opcode, writing data to R0 */
 	retval = cortex_a_exec_opcode(
 			a->armv7a_common.arm.target,
-			ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+			opcode,
 			&dscr);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return cortex_a_read_dcc(a, data, &dscr);
+	/* write R0 to DCC */
+	return cortex_a_instr_read_data_rt_dcc(dpm, 0, data);
 }
 
 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,