X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a.c;h=3923b3d10d0ecec9ceaf9a26ca64e4840c692d26;hp=c04804f85397039f118e6e8b8affd054c7dea5aa;hb=9b6de72c2ba149ac6f3e11d6d0dd3030bf7b19f9;hpb=2615bf4398f393ee1e387128064093dcd44749c8 diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index c04804f853..3923b3d10d 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -14,6 +14,9 @@ * Copyright (C) 2010 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) ST-Ericsson SA 2011 * + * michel.jaouen@stericsson.com : smp minimum support * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -33,6 +36,7 @@ * Cortex-A9(tm) TRM, ARM DDI 0407F * * * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -49,22 +53,20 @@ static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); static int cortex_a8_restore_context(struct target *target, bool bpwp); static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode); + struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_set_context_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode); +static int cortex_a8_set_hybrid_breakpoint(struct target *target, + struct breakpoint *breakpoint); static int cortex_a8_unset_breakpoint(struct target *target, - struct breakpoint *breakpoint); + struct breakpoint *breakpoint); static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum); + uint32_t *value, int regnum); static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum); + uint32_t value, int regnum); static int cortex_a8_mmu(struct target *target, int *enabled); static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys); -static int cortex_a8_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache); -static int cortex_a8_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache); -static int cortex_a8_get_ttb(struct target *target, uint32_t *result); - + uint32_t virt, uint32_t *phys); /* * FIXME do topology discovery using the ROM; don't @@ -75,38 +77,121 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result); #define swjdp_memoryap 0 #define swjdp_debugap 1 +/* restore cp15_control_reg at resume */ +static int cortex_a8_restore_cp15_control_reg(struct target *target) +{ + int retval = ERROR_OK; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); + + if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) { + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; + /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */ + retval = armv7a->arm.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg); + } + return retval; +} + +/* check address before cortex_a8_apb read write access with mmu on + * remove apb predictible data abort */ +static int cortex_a8_check_address(struct target *target, uint32_t address) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + uint32_t os_border = armv7a->armv7a_mmu.os_border; + if ((address < os_border) && + (armv7a->arm.core_mode == ARM_MODE_SVC)) { + LOG_ERROR("%x access in userspace and target in supervisor", address); + return ERROR_FAIL; + } + if ((address >= os_border) && + (cortex_a8->curr_mode != ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); + cortex_a8->curr_mode = ARM_MODE_SVC; + LOG_INFO("%x access in kernel space and target not in supervisor", + address); + return ERROR_OK; + } + if ((address < os_border) && + (cortex_a8->curr_mode == ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + cortex_a8->curr_mode = ARM_MODE_ANY; + } + return ERROR_OK; +} +/* modify cp15_control_reg in order to enable or disable mmu for : + * - virt2phys address conversion + * - read or write memory in phys or virt address */ +static int cortex_a8_mmu_modify(struct target *target, int enable) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = target_to_armv7a(target); + int retval = ERROR_OK; + if (enable) { + /* if mmu enabled at target stop and mmu not enable */ + if (!(cortex_a8->cp15_control_reg & 0x1U)) { + LOG_ERROR("trying to enable mmu on target stopped with mmu disable"); + return ERROR_FAIL; + } + if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) { + cortex_a8->cp15_control_reg_curr |= 0x1U; + retval = armv7a->arm.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg_curr); + } + } else { + if (cortex_a8->cp15_control_reg_curr & 0x4U) { + /* data cache is active */ + cortex_a8->cp15_control_reg_curr &= ~0x4U; + /* flush data cache armv7 function to be called */ + if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) + armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); + } + if ((cortex_a8->cp15_control_reg_curr & 0x1U)) { + cortex_a8->cp15_control_reg_curr &= ~0x1U; + retval = armv7a->arm.mcr(target, 15, + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ + cortex_a8->cp15_control_reg_curr); + } + } + return retval; +} + /* * Cortex-A8 Basic debug access, very low level assumes state is saved */ static int cortex_a8_init_debug_access(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval; uint32_t dummy; LOG_DEBUG(" "); - /* Unlocking the debug registers for modification */ - /* The debugport might be uninitialised so try twice */ + /* Unlocking the debug registers for modification + * The debugport might be uninitialised so try twice */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* try again */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval == ERROR_OK) - { - LOG_USER("Locking debug access failed on first, but succeeded on second try."); - } + LOG_USER( + "Locking debug access failed on first, but succeeded on second try."); } if (retval != ERROR_OK) return retval; /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_PRSR, &dummy); + armv7a->debug_base + CPUDBG_PRSR, &dummy); if (retval != ERROR_OK) return retval; @@ -124,12 +209,12 @@ static int cortex_a8_init_debug_access(struct target *target) * happen to know that no instruction is pending. */ static int cortex_a8_exec_opcode(struct target *target, - uint32_t opcode, uint32_t *dscr_p) + uint32_t opcode, uint32_t *dscr_p) { uint32_t dscr; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; dscr = dscr_p ? *dscr_p : 0; @@ -137,44 +222,37 @@ static int cortex_a8_exec_opcode(struct target *target, /* Wait for InstrCompl bit to be set */ long long then = timeval_ms(); - while ((dscr & DSCR_INSTR_COMP) == 0) - { + while ((dscr & DSCR_INSTR_COMP) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } } retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_ITR, opcode); + armv7a->debug_base + CPUDBG_ITR, opcode); if (retval != ERROR_OK) return retval; then = timeval_ms(); - do - { + do { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register"); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } - } - while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ + } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ if (dscr_p) *dscr_p = dscr; @@ -187,11 +265,11 @@ Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address, - uint32_t * regfile) + uint32_t *regfile) { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0); if (retval != ERROR_OK) @@ -210,28 +288,25 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre } static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum) + uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; uint32_t dscr = 0; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; if (reg > 17) return retval; - if (reg < 15) - { + if (reg < 15) { /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0), &dscr); if (retval != ERROR_OK) return retval; - } - else if (reg == 15) - { + } else if (reg == 15) { /* "MOV r0, r15"; then move r0 to DCCTX */ retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr); if (retval != ERROR_OK) @@ -241,9 +316,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* "MRS r0, CPSR" or "MRS r0, SPSR" * then move r0 to DCCTX */ @@ -259,14 +332,12 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, /* Wait for DTRRXfull then read DTRRTX */ long long then = timeval_ms(); - while ((dscr & DSCR_DTR_TX_FULL) == 0) - { + while ((dscr & DSCR_DTR_TX_FULL) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } @@ -280,23 +351,22 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, } static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum) + uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); /* Check that DCCRX is not full */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (dscr & DSCR_DTR_RX_FULL) - { + if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), @@ -315,16 +385,14 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, if (retval != ERROR_OK) return retval; - if (Rd < 15) - { + if (Rd < 15) { /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); + if (retval != ERROR_OK) return retval; - } - else if (Rd == 15) - { + } else if (Rd == 15) { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "mov r15, r0" */ @@ -335,9 +403,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ @@ -351,8 +417,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, return retval; /* "Prefetch flush" after modifying execution status in CPSR */ - if (Rd == 16) - { + if (Rd == 16) { retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4), &dscr); @@ -365,11 +430,13 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, } /* Write to memory mapped registers directly with no cache or mmu handling */ -static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value) +static int cortex_a8_dap_write_memap_register_u32(struct target *target, + uint32_t address, + uint32_t value) { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value); @@ -395,14 +462,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm) static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); - return mem_ap_sel_write_u32(&a8->armv7a_common.dap, swjdp_debugap, - a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); + return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, + swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, - uint32_t *dscr_p) + uint32_t *dscr_p) { - struct adiv5_dap *swjdp = &a8->armv7a_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr = DSCR_INSTR_COMP; int retval; @@ -417,8 +484,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for read dcc"); return ERROR_FAIL; } @@ -428,7 +494,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); if (retval != ERROR_OK) return retval; - //LOG_DEBUG("read DCC 0x%08" PRIx32, *data); + /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */ if (dscr_p) *dscr_p = dscr; @@ -439,14 +505,13 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - struct adiv5_dap *swjdp = &a8->armv7a_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr; int retval; /* set up invariant: INSTR_COMP is set after ever DPM operation */ long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); @@ -454,8 +519,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) return retval; if ((dscr & DSCR_INSTR_COMP) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for dpm prepare"); return ERROR_FAIL; } @@ -466,7 +530,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -483,7 +547,7 @@ static int cortex_a8_dpm_finish(struct arm_dpm *dpm) } static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -494,13 +558,13 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, return retval; return cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); } static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -512,7 +576,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -520,7 +584,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* then the opcode, taking data from R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); @@ -539,7 +603,7 @@ static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm) } static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -547,7 +611,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, /* the opcode, writing data to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -558,7 +622,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -566,7 +630,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* the opcode, writing data to R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -574,7 +638,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* write R0 to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -584,7 +648,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, } static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, - uint32_t addr, uint32_t control) + uint32_t addr, uint32_t control) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t vr = a8->armv7a_common.debug_base; @@ -592,23 +656,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, int retval; switch (index_t) { - case 0 ... 15: /* breakpoints */ - vr += CPUDBG_BVR_BASE; - cr += CPUDBG_BCR_BASE; - break; - case 16 ... 31: /* watchpoints */ - vr += CPUDBG_WVR_BASE; - cr += CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: /* breakpoints */ + vr += CPUDBG_BVR_BASE; + cr += CPUDBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUDBG_WVR_BASE; + cr += CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } vr += 4 * index_t; cr += 4 * index_t; LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", - (unsigned) vr, (unsigned) cr); + (unsigned) vr, (unsigned) cr); retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target, vr, addr); @@ -625,15 +689,15 @@ static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) uint32_t cr; switch (index_t) { - case 0 ... 15: - cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; - break; - case 16 ... 31: - cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; + break; + case 16 ... 31: + cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } cr += 4 * index_t; @@ -648,7 +712,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) struct arm_dpm *dpm = &a8->armv7a_common.dpm; int retval; - dpm->arm = &a8->armv7a_common.armv4_5_common; + dpm->arm = &a8->armv7a_common.arm; dpm->didr = didr; dpm->prepare = cortex_a8_dpm_prepare; @@ -670,7 +734,47 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) return retval; } +static struct target *get_cortex_a8(struct target *target, int32_t coreid) +{ + struct target_list *head; + struct target *curr; + + head = target->head; + while (head != (struct target_list *)NULL) { + curr = head->target; + if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) + return curr; + head = head->next; + } + return target; +} +static int cortex_a8_halt(struct target *target); + +static int cortex_a8_halt_smp(struct target *target) +{ + int retval = 0; + struct target_list *head; + struct target *curr; + head = target->head; + while (head != (struct target_list *)NULL) { + curr = head->target; + if ((curr != target) && (curr->state != TARGET_HALTED)) + retval += cortex_a8_halt(curr); + head = head->next; + } + return retval; +} +static int update_halt_gdb(struct target *target) +{ + int retval = 0; + if (target->gdb_service->core[0] == -1) { + target->gdb_service->target = target; + target->gdb_service->core[0] = target->coreid; + retval += cortex_a8_halt_smp(target); + } + return retval; +} /* * Cortex-A8 Run control @@ -682,53 +786,64 @@ static int cortex_a8_poll(struct target *target) uint32_t dscr; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; enum target_state prev_target_state = target->state; - + /* toggle to another core is done by gdb as follow */ + /* maint packet J core_id */ + /* continue */ + /* the next polling trigger an halt event sent to gdb */ + if ((target->state == TARGET_HALTED) && (target->smp) && + (target->gdb_service) && + (target->gdb_service->target == NULL)) { + target->gdb_service->target = + get_cortex_a8(target, target->gdb_service->core[1]); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + return retval; + } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) - { return retval; - } cortex_a8->cpudbg_dscr = dscr; - if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) - { - if (prev_target_state != TARGET_HALTED) - { + if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) { + if (prev_target_state != TARGET_HALTED) { /* We have a halting debug event */ LOG_DEBUG("Target halted"); target->state = TARGET_HALTED; if ((prev_target_state == TARGET_RUNNING) - || (prev_target_state == TARGET_RESET)) - { + || (prev_target_state == TARGET_UNKNOWN) + || (prev_target_state == TARGET_RESET)) { retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - + if (target->smp) { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } target_call_event_callbacks(target, - TARGET_EVENT_HALTED); + TARGET_EVENT_HALTED); } - if (prev_target_state == TARGET_DEBUG_RUNNING) - { + if (prev_target_state == TARGET_DEBUG_RUNNING) { LOG_DEBUG(" "); retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; + if (target->smp) { + retval = update_halt_gdb(target); + if (retval != ERROR_OK) + return retval; + } target_call_event_callbacks(target, - TARGET_EVENT_DEBUG_HALTED); + TARGET_EVENT_DEBUG_HALTED); } } - } - else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) - { + } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) target->state = TARGET_RUNNING; - } - else - { + else { LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr); target->state = TARGET_UNKNOWN; } @@ -741,7 +856,7 @@ static int cortex_a8_halt(struct target *target) int retval = ERROR_OK; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; /* * Tell the core to be halted by writing DRCR with 0x1 @@ -756,28 +871,24 @@ static int cortex_a8_halt(struct target *target) * enter halting debug mode */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); + armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_HALTED) != 0) - { break; - } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for halt"); return ERROR_FAIL; } @@ -788,23 +899,19 @@ static int cortex_a8_halt(struct target *target) return ERROR_OK; } -static int cortex_a8_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) +static int cortex_a8_internal_restore(struct target *target, int current, + uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct arm *arm = &armv7a->arm; int retval; - -// struct breakpoint *breakpoint = NULL; - uint32_t resume_pc, dscr; + uint32_t resume_pc; if (!debug_execution) target_free_all_working_areas(target); #if 0 - if (debug_execution) - { + if (debug_execution) { /* Disable interrupts */ /* We disable interrupts in the PRIMASK register instead of * masking with C_MASKINTS, @@ -817,52 +924,64 @@ static int cortex_a8_resume(struct target *target, int current, /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, + 32) | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } #endif /* current = 1: continue on current pc, otherwise continue at
*/ - resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + resume_pc = buf_get_u32(arm->pc->value, 0, 32); if (!current) - resume_pc = address; + resume_pc = *address; + else + *address = resume_pc; /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - switch (armv4_5->core_state) - { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; + switch (arm->core_state) { + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); - buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; - + buf_set_u32(arm->pc->value, 0, 32, resume_pc); + arm->pc->dirty = 1; + arm->pc->valid = 1; + /* restore dpm_mode at system halt */ + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + /* called it now before restoring context because it uses cpu + * register r0 for restoring cp15 control register */ + retval = cortex_a8_restore_cp15_control_reg(target); + if (retval != ERROR_OK) + return retval; retval = cortex_a8_restore_context(target, handle_breakpoints); if (retval != ERROR_OK) return retval; + target->debug_reason = DBG_REASON_NOTHALTED; + target->state = TARGET_RUNNING; + + /* registers are now invalid */ + register_cache_invalidate(arm->core_cache); #if 0 /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); @@ -871,10 +990,19 @@ static int cortex_a8_resume(struct target *target, int current, } #endif + return retval; +} +static int cortex_a8_internal_restart(struct target *target) +{ + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = arm->dap; + int retval; + uint32_t dscr; /* - * Restart core and wait for it to be started. Clear ITRen and sticky - * exception flags: see ARMv7 ARM, C5.9. + * * Restart core and wait for it to be started. Clear ITRen and sticky + * * exception flags: see ARMv7 ARM, C5.9. * * REVISIT: for single stepping, we probably want to * disable IRQs by default, with optional override... @@ -889,26 +1017,25 @@ static int cortex_a8_resume(struct target *target, int current, LOG_ERROR("DSCR InstrCompl must be set before leaving debug!"); retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); + armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); if (retval != ERROR_OK) return retval; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS); + armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | + DRCR_CLEAR_EXCEPTIONS); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_RESTARTED) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for resume"); return ERROR_FAIL; } @@ -918,19 +1045,62 @@ static int cortex_a8_resume(struct target *target, int current, target->state = TARGET_RUNNING; /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); - if (!debug_execution) - { - target->state = TARGET_RUNNING; + return ERROR_OK; +} + +static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints) +{ + int retval = 0; + struct target_list *head; + struct target *curr; + uint32_t address; + head = target->head; + while (head != (struct target_list *)NULL) { + curr = head->target; + if ((curr != target) && (curr->state != TARGET_RUNNING)) { + /* resume current address , not in step mode */ + retval += cortex_a8_internal_restore(curr, 1, &address, + handle_breakpoints, 0); + retval += cortex_a8_internal_restart(curr); + } + head = head->next; + + } + return retval; +} + +static int cortex_a8_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + int retval = 0; + /* dummy resume for smp toggle in order to reduce gdb impact */ + if ((target->smp) && (target->gdb_service->core[1] != -1)) { + /* simulate a start and halt of target */ + target->gdb_service->target = NULL; + target->gdb_service->core[0] = target->gdb_service->core[1]; + /* fake resume at next poll we play the target core[1], see poll*/ target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc); + return 0; } - else - { + cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution); + if (target->smp) { + target->gdb_service->core[0] = -1; + retval = cortex_a8_restore_smp(target, handle_breakpoints); + if (retval != ERROR_OK) + return retval; + } + cortex_a8_internal_restart(target); + + if (!debug_execution) { + target->state = TARGET_RUNNING; + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + LOG_DEBUG("target resumed at 0x%" PRIx32, address); + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc); + LOG_DEBUG("target debug resumed at 0x%" PRIx32, address); } return ERROR_OK; @@ -944,15 +1114,15 @@ static int cortex_a8_debug_entry(struct target *target) struct working_area *regfile_working_area = NULL; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = armv7a->arm.dap; struct reg *reg; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); /* REVISIT surely we should not re-read DSCR !! */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -991,33 +1161,28 @@ static int cortex_a8_debug_entry(struct target *target) /* First load register acessible through core debug port*/ if (!regfile_working_area) - { retval = arm_dpm_read_current_registers(&armv7a->dpm); - } - else - { + else { retval = cortex_a8_read_regs_through_mem(target, regfile_working_area->address, regfile); target_free_working_area(target, regfile_working_area); if (retval != ERROR_OK) - { return retval; - } /* read Current PSR */ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); + /* store current cpsr */ if (retval != ERROR_OK) return retval; LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); - arm_set_cpsr(armv4_5, cpsr); + arm_set_cpsr(arm, cpsr); /* update cache */ - for (i = 0; i <= ARM_PC; i++) - { - reg = arm_reg_current(armv4_5, i); + for (i = 0; i <= ARM_PC; i++) { + reg = arm_reg_current(arm, i); buf_set_u32(reg->value, 0, 32, regfile[i]); reg->valid = 1; @@ -1025,18 +1190,15 @@ static int cortex_a8_debug_entry(struct target *target) } /* Fixup PC Resume Address */ - if (cpsr & (1 << 5)) - { - // T bit set for Thumb or ThumbEE state + if (cpsr & (1 << 5)) { + /* T bit set for Thumb or ThumbEE state */ regfile[ARM_PC] -= 4; - } - else - { - // ARM state + } else { + /* ARM state */ regfile[ARM_PC] -= 8; } - reg = armv4_5->pc; + reg = arm->pc; buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]); reg->dirty = reg->valid; } @@ -1055,9 +1217,8 @@ static int cortex_a8_debug_entry(struct target *target) #endif /* Are we in an exception handler */ -// armv4_5->exception_number = 0; - if (armv7a->post_debug_entry) - { +/* armv4_5->exception_number = 0; */ + if (armv7a->post_debug_entry) { retval = armv7a->post_debug_entry(target); if (retval != ERROR_OK) return retval; @@ -1073,68 +1234,50 @@ static int cortex_a8_post_debug_entry(struct target *target) int retval; /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, + retval = armv7a->arm.mrc(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ &cortex_a8->cp15_control_reg); if (retval != ERROR_OK) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; - if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1) - { - uint32_t cache_type_reg; - - /* MRC p15,0,,c0,c0,1 ; Read CP15 Cache Type Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 0, 0, /* CRn, CRm */ - &cache_type_reg); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg); - - /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */ - armv4_5_identify_cache(cache_type_reg, - &armv7a->armv4_5_mmu.armv4_5_cache); - } + if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) + armv7a_identify_cache(target); - armv7a->armv4_5_mmu.mmu_enabled = - (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; - armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = - (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; - armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled = - (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; + armv7a->armv7a_mmu.mmu_enabled = + (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; + armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = + (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; + armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = + (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; + cortex_a8->curr_mode = armv7a->arm.core_mode; return ERROR_OK; } static int cortex_a8_step(struct target *target, int current, uint32_t address, - int handle_breakpoints) + int handle_breakpoints) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; struct breakpoint *breakpoint = NULL; struct breakpoint stepbreakpoint; struct reg *r; int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* current = 1: continue on current pc, otherwise continue at
*/ - r = armv4_5->pc; + r = arm->pc; if (!current) - { buf_set_u32(r->value, 0, 32, address); - } else - { address = buf_get_u32(r->value, 0, 32); - } /* The front-end may request us not to handle breakpoints. * But since Cortex-A8 uses breakpoint for single step, @@ -1149,8 +1292,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; - stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB) - ? 2 : 4; + stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB) + ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -1164,13 +1307,11 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, return retval; long long then = timeval_ms(); - while (target->state != TARGET_HALTED) - { + while (target->state != TARGET_HALTED) { retval = cortex_a8_poll(target); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for target halt"); return ERROR_FAIL; } @@ -1201,46 +1342,40 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp) return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp); } - /* * Cortex-A8 Breakpoint and watchpoint functions */ /* Setup hardware Breakpoint Register Pair */ static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode) + struct breakpoint *breakpoint, uint8_t matchmode) { int retval; - int brp_i=0; + int brp_i = 0; uint32_t control; uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num)) - brp_i++ ; - if (brp_i >= cortex_a8->brp_num) - { + brp_i++; + if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = brp_i + 1; if (breakpoint->length == 2) - { byte_addr_select = (3 << (breakpoint->address & 0x02)); - } control = ((matchmode & 0x7) << 20) - | (byte_addr_select << 5) - | (3 << 1) | 1; + | (byte_addr_select << 5) + | (3 << 1) | 1; brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].control = control; @@ -1255,142 +1390,335 @@ static int cortex_a8_set_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); - } - else if (breakpoint->type == BKPT_SOFT) - { + brp_list[brp_i].control, + brp_list[brp_i].value); + } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; if (breakpoint->length == 2) - { buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); - } else - { buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11)); - } - retval = target->type->read_memory(target, + retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; - retval = target->type->write_memory(target, + retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code); if (retval != ERROR_OK) return retval; - breakpoint->set = 0x11; /* Any nice value but 0 */ + breakpoint->set = 0x11; /* Any nice value but 0 */ } return ERROR_OK; } -static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) +static int cortex_a8_set_context_breakpoint(struct target *target, + struct breakpoint *breakpoint, uint8_t matchmode) { - int retval; + int retval = ERROR_FAIL; + int brp_i = 0; + uint32_t control; + uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (!breakpoint->set) - { - LOG_WARNING("breakpoint not set"); - return ERROR_OK; + if (breakpoint->set) { + LOG_WARNING("breakpoint already set"); + return retval; } + /*check available context BRPs*/ + while ((brp_list[brp_i].used || + (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) + brp_i++; - if (breakpoint->type == BKPT_HARD) - { - int brp_i = breakpoint->set - 1; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) - { - LOG_DEBUG("Invalid BRP number in breakpoint"); - return ERROR_OK; - } - LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); - brp_list[brp_i].used = 0; - brp_list[brp_i].value = 0; - brp_list[brp_i].control = 0; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, - brp_list[brp_i].control); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, - brp_list[brp_i].value); - if (retval != ERROR_OK) - return retval; - } - else - { - /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { - retval = target->type->write_memory(target, - breakpoint->address & 0xFFFFFFFE, - 4, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) - return retval; - } - else - { - retval = target->type->write_memory(target, - breakpoint->address & 0xFFFFFFFE, - 2, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) - return retval; - } + if (brp_i >= cortex_a8->brp_num) { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; } - breakpoint->set = 0; + breakpoint->set = brp_i + 1; + control = ((matchmode & 0x7) << 20) + | (byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_i].used = 1; + brp_list[brp_i].value = (breakpoint->asid); + brp_list[brp_i].control = control; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, + brp_list[brp_i].value); return ERROR_OK; + } -static int cortex_a8_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) +static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint) { + int retval = ERROR_FAIL; + int brp_1 = 0; /* holds the contextID pair */ + int brp_2 = 0; /* holds the IVA pair */ + uint32_t control_CTX, control_IVA; + uint8_t CTX_byte_addr_select = 0x0F; + uint8_t IVA_byte_addr_select = 0x0F; + uint8_t CTX_machmode = 0x03; + uint8_t IVA_machmode = 0x01; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { - LOG_INFO("no hardware breakpoint available"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (breakpoint->set) { + LOG_WARNING("breakpoint already set"); + return retval; + } + /*check available context BRPs*/ + while ((brp_list[brp_1].used || + (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) + brp_1++; + + printf("brp(CTX) found num: %d\n", brp_1); + if (brp_1 >= cortex_a8->brp_num) { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; } - if (breakpoint->type == BKPT_HARD) - cortex_a8->brp_num_available--; + while ((brp_list[brp_2].used || + (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) + brp_2++; - return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ -} + printf("brp(IVA) found num: %d\n", brp_2); + if (brp_2 >= cortex_a8->brp_num) { + LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); + return ERROR_FAIL; + } -static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) -{ + breakpoint->set = brp_1 + 1; + breakpoint->linked_BRP = brp_2; + control_CTX = ((CTX_machmode & 0x7) << 20) + | (brp_2 << 16) + | (0 << 14) + | (CTX_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_1].used = 1; + brp_list[brp_1].value = (breakpoint->asid); + brp_list[brp_1].control = control_CTX; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].control); + if (retval != ERROR_OK) + return retval; + + control_IVA = ((IVA_machmode & 0x7) << 20) + | (brp_1 << 16) + | (IVA_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_2].used = 1; + brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); + brp_list[brp_2].control = control_IVA; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].control); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; +} + +static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) +{ + int retval; + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; + + if (!breakpoint->set) { + LOG_WARNING("breakpoint not set"); + return ERROR_OK; + } + + if (breakpoint->type == BKPT_HARD) { + if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { + int brp_i = breakpoint->set - 1; + int brp_j = breakpoint->linked_BRP; + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].used = 0; + brp_list[brp_i].value = 0; + brp_list[brp_i].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if (retval != ERROR_OK) + return retval; + if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j, + brp_list[brp_j].control, brp_list[brp_j].value); + brp_list[brp_j].used = 0; + brp_list[brp_j].value = 0; + brp_list[brp_j].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_j].BRPn, + brp_list[brp_j].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_j].BRPn, + brp_list[brp_j].value); + if (retval != ERROR_OK) + return retval; + breakpoint->linked_BRP = 0; + breakpoint->set = 0; + return ERROR_OK; + + } else { + int brp_i = breakpoint->set - 1; + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { + LOG_DEBUG("Invalid BRP number in breakpoint"); + return ERROR_OK; + } + LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, + brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].used = 0; + brp_list[brp_i].value = 0; + brp_list[brp_i].control = 0; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + brp_list[brp_i].value); + if (retval != ERROR_OK) + return retval; + breakpoint->set = 0; + return ERROR_OK; + } + } else { + /* restore original instruction (kept in target endianness) */ + if (breakpoint->length == 4) { + retval = target_write_memory(target, + breakpoint->address & 0xFFFFFFFE, + 4, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) + return retval; + } else { + retval = target_write_memory(target, + breakpoint->address & 0xFFFFFFFE, + 2, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) + return retval; + } + } + breakpoint->set = 0; + + return ERROR_OK; +} + +static int cortex_a8_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { + LOG_INFO("no hardware breakpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (breakpoint->type == BKPT_HARD) + cortex_a8->brp_num_available--; + + return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ +} + +static int cortex_a8_add_context_breakpoint(struct target *target, + struct breakpoint *breakpoint) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { + LOG_INFO("no hardware breakpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (breakpoint->type == BKPT_HARD) + cortex_a8->brp_num_available--; + + return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ +} + +static int cortex_a8_add_hybrid_breakpoint(struct target *target, + struct breakpoint *breakpoint) +{ + struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); + + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { + LOG_INFO("no hardware breakpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + if (breakpoint->type == BKPT_HARD) + cortex_a8->brp_num_available--; + + return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ +} + + +static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) +{ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); #if 0 /* It is perfectly possible to remove breakpoints while the target is running */ - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } #endif - if (breakpoint->set) - { + if (breakpoint->set) { cortex_a8_unset_breakpoint(target, breakpoint); if (breakpoint->type == BKPT_HARD) - cortex_a8->brp_num_available++ ; + cortex_a8->brp_num_available++; } return ERROR_OK; } - - /* * Cortex-A8 Reset functions */ @@ -1404,9 +1732,9 @@ static int cortex_a8_assert_reset(struct target *target) /* FIXME when halt is requested, make it work somehow... */ /* Issue some kind of warm reset. */ - if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - } else if (jtag_get_reset_config() & RESET_HAS_SRST) { + else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ @@ -1417,7 +1745,7 @@ static int cortex_a8_assert_reset(struct target *target) } /* registers are now invalid */ - register_cache_invalidate(armv7a->armv4_5_common.core_cache); + register_cache_invalidate(armv7a->arm.core_cache); target->state = TARGET_RESET; @@ -1440,8 +1768,9 @@ static int cortex_a8_deassert_reset(struct target *target) if (target->reset_halt) { if (target->state != TARGET_HALTED) { LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - if ((retval = target_halt(target)) != ERROR_OK) + target_name(target)); + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } } @@ -1449,6 +1778,138 @@ static int cortex_a8_deassert_reset(struct target *target) return ERROR_OK; } +static int cortex_a8_write_apb_ab_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) +{ + /* write memory through APB-AP */ + + int retval = ERROR_COMMAND_SYNTAX_ERROR; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *arm = &armv7a->arm; + int total_bytes = count * size; + int start_byte, nbytes_to_write, i; + struct reg *reg; + union _data { + uint8_t uc_a[4]; + uint32_t ui; + } data; + + if (target->state != TARGET_HALTED) { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + reg = arm_reg_current(arm, 0); + reg->dirty = 1; + reg = arm_reg_current(arm, 1); + reg->dirty = 1; + + retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); + if (retval != ERROR_OK) + return retval; + + start_byte = address & 0x3; + + while (total_bytes > 0) { + + nbytes_to_write = 4 - start_byte; + if (total_bytes < nbytes_to_write) + nbytes_to_write = total_bytes; + + if (nbytes_to_write != 4) { + + /* execute instruction LDR r1, [r0] */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_LDR(1, 0), NULL); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a8_dap_read_coreregister_u32(target, &data.ui, 1); + if (retval != ERROR_OK) + return retval; + } + + for (i = 0; i < nbytes_to_write; ++i) + data.uc_a[i + start_byte] = *buffer++; + + retval = cortex_a8_dap_write_coreregister_u32(target, data.ui, 1); + if (retval != ERROR_OK) + return retval; + + /* execute instruction STRW r1, [r0], 1 (0xe4801004) */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0), NULL); + if (retval != ERROR_OK) + return retval; + + total_bytes -= nbytes_to_write; + start_byte = 0; + } + + return retval; +} + + +static int cortex_a8_read_apb_ab_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ + + /* read memory through APB-AP */ + + int retval = ERROR_COMMAND_SYNTAX_ERROR; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct arm *arm = &armv7a->arm; + int total_bytes = count * size; + int start_byte, nbytes_to_read, i; + struct reg *reg; + union _data { + uint8_t uc_a[4]; + uint32_t ui; + } data; + + if (target->state != TARGET_HALTED) { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + reg = arm_reg_current(arm, 0); + reg->dirty = 1; + reg = arm_reg_current(arm, 1); + reg->dirty = 1; + + retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); + if (retval != ERROR_OK) + return retval; + + start_byte = address & 0x3; + + while (total_bytes > 0) { + + /* execute instruction LDRW r1, [r0], 4 (0xe4901004) */ + retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRW_IP(1, 0), NULL); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a8_dap_read_coreregister_u32(target, &data.ui, 1); + if (retval != ERROR_OK) + return retval; + + nbytes_to_read = 4 - start_byte; + if (total_bytes < nbytes_to_read) + nbytes_to_read = total_bytes; + + for (i = 0; i < nbytes_to_read; ++i) + *buffer++ = data.uc_a[i + start_byte]; + + total_bytes -= nbytes_to_read; + start_byte = 0; + } + + return retval; +} + + + /* * Cortex-A8 Memory access * @@ -1457,240 +1918,139 @@ static int cortex_a8_deassert_reset(struct target *target) */ static int cortex_a8_read_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; - int retval = ERROR_INVALID_ARGUMENTS; + struct adiv5_dap *swjdp = armv7a->arm.dap; + int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - - LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count); + LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", + address, size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* read memory through AHB-AP */ switch (size) { case 4: retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, - buffer, 4 * count, address); + buffer, 4 * count, address); break; case 2: retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, - buffer, 2 * count, address); + buffer, 2 * count, address); break; case 1: retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, - buffer, count, address); + buffer, count, address); break; } - } else { - /* read memory through APB-AP */ - - uint32_t saved_r0, saved_r1; - int nbytes = count * size; - uint32_t data; - int enabled = 0; - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if (enabled) - { - LOG_WARNING("Reading physical memory through APB with MMU enabled is not yet implemented"); - return ERROR_TARGET_FAILURE; - } - - /* save registers r0 and r1, we are going to corrupt them */ - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, address, 0); - if (retval != ERROR_OK) - return retval; - - while (nbytes > 0) { - - /* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_LDRB_IP(1, 0) , NULL); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_read_coreregister_u32(target, &data, 1); - if (retval != ERROR_OK) - return retval; - - *buffer++ = data; - --nbytes; - - } - - /* restore corrupted registers r0 and r1 */ - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0); + /* read memory through APB-AP + * disable mmu */ + retval = cortex_a8_mmu_modify(target, 0); if (retval != ERROR_OK) return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1); - if (retval != ERROR_OK) - return retval; - + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } } - return retval; } static int cortex_a8_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { - int enabled = 0; - uint32_t virt, phys; - int retval; + int enabled = 0; + uint32_t virt, phys; + int retval; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct adiv5_dap *swjdp = armv7a->arm.dap; + uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ + LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + size, count); + if (apsel == swjdp_memoryap) { + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; - LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count); - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if(enabled) - { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys); - address = phys; - } + if (enabled) { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; - return cortex_a8_read_phys_memory(target, address, size, count, buffer); + LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", + virt, phys); + address = phys; + } + retval = cortex_a8_read_phys_memory(target, address, size, count, buffer); + } else { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) + return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); + } + return retval; } static int cortex_a8_write_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; - int retval = ERROR_INVALID_ARGUMENTS; + struct adiv5_dap *swjdp = armv7a->arm.dap; + int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; - LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count); + LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, + size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* write memory through AHB-AP */ switch (size) { case 4: retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap, - buffer, 4 * count, address); + buffer, 4 * count, address); break; case 2: retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap, - buffer, 2 * count, address); + buffer, 2 * count, address); break; case 1: retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap, - buffer, count, address); + buffer, count, address); break; } } else { /* write memory through APB-AP */ - - uint32_t saved_r0, saved_r1; - int nbytes = count * size; - uint32_t data; - int enabled = 0; - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; - - if (enabled) - { - LOG_WARNING("Writing physical memory through APB with MMU enabled is not yet implemented"); - return ERROR_TARGET_FAILURE; - } - - /* save registers r0 and r1, we are going to corrupt them */ - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r0, 0); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_read_coreregister_u32(target, &saved_r1, 1); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, address, 0); - if (retval != ERROR_OK) - return retval; - - while (nbytes > 0) { - - data = *buffer++; - - retval = cortex_a8_dap_write_coreregister_u32(target, data, 1); - if (retval != ERROR_OK) - return retval; - - /* execute instruction STRB r1, [r0], 1 (0xe4c01001) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_STRB_IP(1, 0) , NULL); - if (retval != ERROR_OK) - return retval; - - --nbytes; - } - - /* restore corrupted registers r0 and r1 */ - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r0, 0); - if (retval != ERROR_OK) - return retval; - - retval = cortex_a8_dap_write_coreregister_u32(target, saved_r1, 1); + retval = cortex_a8_mmu_modify(target, 0); if (retval != ERROR_OK) return retval; - - /* we can return here without invalidating D/I-cache because */ - /* access through APB maintains cache coherency */ - return retval; + return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } } /* REVISIT this op is generic ARMv7-A/R stuff */ - if (retval == ERROR_OK && target->state == TARGET_HALTED) - { - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + if (retval == ERROR_OK && target->state == TARGET_HALTED) { + struct arm_dpm *dpm = armv7a->arm.dpm; retval = dpm->prepare(dpm); if (retval != ERROR_OK) @@ -1706,15 +2066,14 @@ static int cortex_a8_write_phys_memory(struct target *target, */ /* invalidate I-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { /* ICIMVAU - Invalidate Cache single entry * with MVA to PoU * MCR p15, 0, r0, c7, c5, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), cacheline); @@ -1724,15 +2083,14 @@ static int cortex_a8_write_phys_memory(struct target *target, } /* invalidate D-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { /* DCIMVAC - Invalidate data Cache line * with MVA to PoC * MCR p15, 0, r0, c7, c6, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), cacheline); @@ -1748,65 +2106,62 @@ static int cortex_a8_write_phys_memory(struct target *target, } static int cortex_a8_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { - int enabled = 0; - uint32_t virt, phys; - int retval; + int enabled = 0; + uint32_t virt, phys; + int retval; + struct armv7a_common *armv7a = target_to_armv7a(target); + struct adiv5_dap *swjdp = armv7a->arm.dap; + uint8_t apsel = swjdp->apsel; + /* cortex_a8 handles unaligned memory access */ + LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, + size, count); + if (apsel == swjdp_memoryap) { - LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); - retval = cortex_a8_mmu(target, &enabled); - if (retval != ERROR_OK) - return retval; + LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, + count); + retval = cortex_a8_mmu(target, &enabled); + if (retval != ERROR_OK) + return retval; - if(enabled) - { - virt = address; - retval = cortex_a8_virt2phys(target, virt, &phys); - if (retval != ERROR_OK) - return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys); - address = phys; - } + if (enabled) { + virt = address; + retval = cortex_a8_virt2phys(target, virt, &phys); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", + virt, + phys); + address = phys; + } - return cortex_a8_write_phys_memory(target, address, size, - count, buffer); + retval = cortex_a8_write_phys_memory(target, address, size, + count, buffer); + } else { + retval = cortex_a8_check_address(target, address); + if (retval != ERROR_OK) + return retval; + /* enable mmu */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); + } + return retval; } static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } -static int cortex_a8_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) -{ -#if 0 - u16 dcrdr; - - mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); - *ctrl = (uint8_t)dcrdr; - *value = (uint8_t)(dcrdr >> 8); - - LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl); - - /* write ack back to software dcc register - * signify we have read data */ - if (dcrdr & (1 << 0)) - { - dcrdr = 0; - mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); - } -#endif - return ERROR_OK; -} - - static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval; if (!target_was_examined(target)) @@ -1814,35 +2169,21 @@ static int cortex_a8_handle_target_request(void *priv) if (!target->dbg_msg_enabled) return ERROR_OK; - if (target->state == TARGET_RUNNING) - { - uint8_t data = 0; - uint8_t ctrl = 0; - - retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); - if (retval != ERROR_OK) - return retval; + if (target->state == TARGET_RUNNING) { + uint32_t request; + uint32_t dscr; + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DSCR, &dscr); /* check if we have data */ - if (ctrl & (1 << 0)) - { - uint32_t request; - - /* we assume target is quick enough */ - request = data; - retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); - if (retval != ERROR_OK) - return retval; - request |= (data << 8); - retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); - if (retval != ERROR_OK) - return retval; - request |= (data << 16); - retval = cortex_a8_dcc_read(swjdp, &data, &ctrl); - if (retval != ERROR_OK) - return retval; - request |= (data << 24); - target_request(target, request); + while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DTRTX, &request); + if (retval == ERROR_OK) { + target_request(target, request); + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + } } } @@ -1857,11 +2198,10 @@ static int cortex_a8_examine_first(struct target *target) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = &armv7a->dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; - uint32_t dbgbase; /* We do one extra read to ensure DAP is configured, * we call ahbap_debugport_init(swjdp) instead @@ -1870,68 +2210,50 @@ static int cortex_a8_examine_first(struct target *target) if (retval != ERROR_OK) return retval; - if (!target->dbgbase_set) - { + if (!target->dbgbase_set) { + uint32_t dbgbase; /* Get ROM Table base */ uint32_t apid; retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid); if (retval != ERROR_OK) return retval; + /* Lookup 0x15 -- Processor DAP */ + retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, + &armv7a->debug_base); + if (retval != ERROR_OK) + return retval; } else - { - dbgbase = target->dbgbase; - } - - /* Lookup 0x15 -- Processor DAP */ - retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15, - &armv7a->debug_base); - if (retval != ERROR_OK) - return retval; - -#if 0 - /* - * FIXME: assuming omap4430 - * - * APB DBGBASE reads 0x80040000, but this points to an empty ROM table. - * 0x80000000 is cpu0 coresight region - */ - if (target->coreid > 3) { - LOG_ERROR("cortex_a8 supports up to 4 cores"); - return ERROR_INVALID_ARGUMENTS; - } - armv7a->debug_base = 0x80000000 | - ((target->coreid & 0x3) << CORTEX_A8_PADDRDBG_CPU_SHIFT); -#endif + armv7a->debug_base = target->dbgbase; retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if (retval != ERROR_OK) return retval; - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CPUID, &cpuid); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CPUID"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CTYPR, &ctypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_TTYPR, &ttypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "TTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DIDR, &didr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "DIDR"); return retval; } @@ -1941,7 +2263,7 @@ static int cortex_a8_examine_first(struct target *target) LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr); LOG_DEBUG("didr = 0x%08" PRIx32, didr); - armv7a->armv4_5_common.core_type = ARM_MODE_MON; + armv7a->arm.core_type = ARM_MODE_MON; retval = cortex_a8_dpm_setup(cortex_a8, didr); if (retval != ERROR_OK) return retval; @@ -1951,9 +2273,8 @@ static int cortex_a8_examine_first(struct target *target) cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1; cortex_a8->brp_num_available = cortex_a8->brp_num; cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp)); -// cortex_a8->brb_enabled = ????; - for (i = 0; i < cortex_a8->brp_num; i++) - { +/* cortex_a8->brb_enabled = ????; */ + for (i = 0; i < cortex_a8->brp_num; i++) { cortex_a8->brp_list[i].used = 0; if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context)) cortex_a8->brp_list[i].type = BRP_NORMAL; @@ -1990,63 +2311,57 @@ static int cortex_a8_examine(struct target *target) */ static int cortex_a8_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { /* examine_first() does a bunch of this */ return ERROR_OK; } static int cortex_a8_init_arch_info(struct target *target, - struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct arm *armv4_5 = &armv7a->armv4_5_common; struct adiv5_dap *dap = &armv7a->dap; - armv7a->armv4_5_common.dap = dap; + armv7a->arm.dap = dap; /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; - armv4_5->arch_info = armv7a; - - /* prepare JTAG information for the new target */ - cortex_a8->jtag_info.tap = tap; - cortex_a8->jtag_info.scann_size = 4; - - /* Leave (only) generic DAP stuff for debugport_init() */ - dap->jtag_info = &cortex_a8->jtag_info; - dap->memaccess_tck = 80; - - /* Number of bits for tar autoincrement, impl. dep. at least 10 */ - dap->tar_autoincr_block = (1 << 10); + /* tap has no dap initialized */ + if (!tap->dap) { + armv7a->arm.dap = dap; + /* Setup struct cortex_a8_common */ + + /* prepare JTAG information for the new target */ + cortex_a8->jtag_info.tap = tap; + cortex_a8->jtag_info.scann_size = 4; + + /* Leave (only) generic DAP stuff for debugport_init() */ + dap->jtag_info = &cortex_a8->jtag_info; + + /* Number of bits for tar autoincrement, impl. dep. at least 10 */ + dap->tar_autoincr_block = (1 << 10); + dap->memaccess_tck = 80; + tap->dap = dap; + } else + armv7a->arm.dap = tap->dap; cortex_a8->fast_reg_read = 0; - /* Set default value */ - cortex_a8->current_address_mode = ARM_MODE_ANY; - /* register arch-specific functions */ armv7a->examine_debug_reason = NULL; armv7a->post_debug_entry = cortex_a8_post_debug_entry; armv7a->pre_restore_context = NULL; - armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1; - armv7a->armv4_5_mmu.get_ttb = cortex_a8_get_ttb; - armv7a->armv4_5_mmu.read_memory = cortex_a8_read_phys_memory; - armv7a->armv4_5_mmu.write_memory = cortex_a8_write_phys_memory; - armv7a->armv4_5_mmu.disable_mmu_caches = cortex_a8_disable_mmu_caches; - armv7a->armv4_5_mmu.enable_mmu_caches = cortex_a8_enable_mmu_caches; - armv7a->armv4_5_mmu.has_tiny_pages = 1; - armv7a->armv4_5_mmu.mmu_enabled = 0; + armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory; -// arm7_9->handle_target_request = cortex_a8_handle_target_request; - /* REVISIT v7a setup should be in a v7a-specific routine */ - arm_init_arch_info(target, armv4_5); - armv7a->common_magic = ARMV7_COMMON_MAGIC; +/* arm7_9->handle_target_request = cortex_a8_handle_target_request; */ + /* REVISIT v7a setup should be in a v7a-specific routine */ + armv7a_init_arch_info(target, armv7a); target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target); return ERROR_OK; @@ -2059,133 +2374,6 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp) return cortex_a8_init_arch_info(target, cortex_a8, target->tap); } -static int cortex_a8_get_ttb(struct target *target, uint32_t *result) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t ttb = 0, retval = ERROR_OK; - - /* current_address_mode is set inside cortex_a8_virt2phys() - where we can determine if address belongs to user or kernel */ - if(cortex_a8->current_address_mode == ARM_MODE_SVC) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - else if(cortex_a8->current_address_mode == ARM_MODE_USR) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - /* we don't know whose address is: user or kernel - we assume that if we are in kernel mode then - address belongs to kernel else if in user mode - - to user */ - else if(armv7a->armv4_5_common.core_mode == ARM_MODE_SVC) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 1, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR) - { - /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 2, 0, /* CRn, CRm */ - &ttb); - if (retval != ERROR_OK) - return retval; - } - /* finally we don't know whose ttb to use: user or kernel */ - else - LOG_ERROR("Don't know how to get ttb for current mode!!!"); - - ttb &= 0xffffc000; - - *result = ttb; - - return ERROR_OK; -} - -static int cortex_a8_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t cp15_control; - int retval; - - /* read cp15 control register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - &cp15_control); - if (retval != ERROR_OK) - return retval; - - - if (mmu) - cp15_control &= ~0x1U; - - if (d_u_cache) - cp15_control &= ~0x4U; - - if (i_cache) - cp15_control &= ~0x1000U; - - retval = armv7a->armv4_5_common.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - cp15_control); - return retval; -} - -static int cortex_a8_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) -{ - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - uint32_t cp15_control; - int retval; - - /* read cp15 control register */ - retval = armv7a->armv4_5_common.mrc(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - &cp15_control); - if (retval != ERROR_OK) - return retval; - - if (mmu) - cp15_control |= 0x1U; - - if (d_u_cache) - cp15_control |= 0x4U; - - if (i_cache) - cp15_control |= 0x1000U; - - retval = armv7a->armv4_5_common.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ - cp15_control); - return retval; -} static int cortex_a8_mmu(struct target *target, int *enabled) @@ -2195,36 +2383,33 @@ static int cortex_a8_mmu(struct target *target, int *enabled) return ERROR_TARGET_INVALID; } - *enabled = target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled; + *enabled = target_to_cortex_a8(target)->armv7a_common.armv7a_mmu.mmu_enabled; return ERROR_OK; } static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys) + uint32_t virt, uint32_t *phys) { - uint32_t cb; - struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - // struct armv7a_common *armv7a = &cortex_a8->armv7a_common; + int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - - /* We assume that virtual address is separated - between user and kernel in Linux style: - 0x00000000-0xbfffffff - User space - 0xc0000000-0xffffffff - Kernel space */ - if( virt < 0xc0000000 ) /* Linux user space */ - cortex_a8->current_address_mode = ARM_MODE_USR; - else /* Linux kernel */ - cortex_a8->current_address_mode = ARM_MODE_SVC; - uint32_t ret; - int retval = armv4_5_mmu_translate_va(target, - &armv7a->armv4_5_mmu, virt, &cb, &ret); - if (retval != ERROR_OK) - return retval; - /* Reset the flag. We don't want someone else to use it by error */ - cortex_a8->current_address_mode = ARM_MODE_ANY; - - *phys = ret; - return ERROR_OK; + struct adiv5_dap *swjdp = armv7a->arm.dap; + uint8_t apsel = swjdp->apsel; + if (apsel == swjdp_memoryap) { + uint32_t ret; + retval = armv7a_mmu_translate_va(target, + virt, &ret); + if (retval != ERROR_OK) + goto done; + *phys = ret; + } else {/* use this method if swjdp_memoryap not selected + * mmu must be enable in order to get a correct translation */ + retval = cortex_a8_mmu_modify(target, 1); + if (retval != ERROR_OK) + goto done; + retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1); + } +done: + return retval; } COMMAND_HANDLER(cortex_a8_handle_cache_info_command) @@ -2232,22 +2417,78 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command) struct target *target = get_current_target(CMD_CTX); struct armv7a_common *armv7a = target_to_armv7a(target); - return armv4_5_handle_cache_info_command(CMD_CTX, - &armv7a->armv4_5_mmu.armv4_5_cache); + return armv7a_handle_cache_info_command(CMD_CTX, + &armv7a->armv7a_mmu.armv7a_cache); } COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { struct target *target = get_current_target(CMD_CTX); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("target not examined yet"); return ERROR_FAIL; } return cortex_a8_init_debug_access(target); } +COMMAND_HANDLER(cortex_a8_handle_smp_off_command) +{ + struct target *target = get_current_target(CMD_CTX); + /* check target is an smp target */ + struct target_list *head; + struct target *curr; + head = target->head; + target->smp = 0; + if (head != (struct target_list *)NULL) { + while (head != (struct target_list *)NULL) { + curr = head->target; + curr->smp = 0; + head = head->next; + } + /* fixes the target display to the debugger */ + target->gdb_service->target = target; + } + return ERROR_OK; +} + +COMMAND_HANDLER(cortex_a8_handle_smp_on_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct target_list *head; + struct target *curr; + head = target->head; + if (head != (struct target_list *)NULL) { + target->smp = 1; + while (head != (struct target_list *)NULL) { + curr = head->target; + curr->smp = 1; + head = head->next; + } + } + return ERROR_OK; +} + +COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command) +{ + struct target *target = get_current_target(CMD_CTX); + int retval = ERROR_OK; + struct target_list *head; + head = target->head; + if (head != (struct target_list *)NULL) { + if (CMD_ARGC == 1) { + int coreid = 0; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); + if (ERROR_OK != retval) + return retval; + target->gdb_service->core[1] = coreid; + + } + command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] + , target->gdb_service->core[1]); + } + return ERROR_OK; +} static const struct command_registration cortex_a8_exec_command_handlers[] = { { @@ -2255,13 +2496,36 @@ static const struct command_registration cortex_a8_exec_command_handlers[] = { .handler = cortex_a8_handle_cache_info_command, .mode = COMMAND_EXEC, .help = "display information about target caches", + .usage = "", }, { .name = "dbginit", .handler = cortex_a8_handle_dbginit_command, .mode = COMMAND_EXEC, .help = "Initialize core debug", + .usage = "", + }, + { .name = "smp_off", + .handler = cortex_a8_handle_smp_off_command, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "",}, + { + .name = "smp_on", + .handler = cortex_a8_handle_smp_on_command, + .mode = COMMAND_EXEC, + .help = "Restart smp handling", + .usage = "", }, + { + .name = "smp_gdb", + .handler = cortex_a8_handle_smp_gdb_command, + .mode = COMMAND_EXEC, + .help = "display/fix current core played to gdb", + .usage = "", + }, + + COMMAND_REGISTRATION_DONE }; static const struct command_registration cortex_a8_command_handlers[] = { @@ -2275,6 +2539,7 @@ static const struct command_registration cortex_a8_command_handlers[] = { .name = "cortex_a8", .mode = COMMAND_ANY, .help = "Cortex-A8 command group", + .usage = "", .chain = cortex_a8_exec_command_handlers, }, COMMAND_REGISTRATION_DONE @@ -2309,6 +2574,8 @@ struct target_type cortexa8_target = { .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = cortex_a8_add_breakpoint, + .add_context_breakpoint = cortex_a8_add_context_breakpoint, + .add_hybrid_breakpoint = cortex_a8_add_hybrid_breakpoint, .remove_breakpoint = cortex_a8_remove_breakpoint, .add_watchpoint = NULL, .remove_watchpoint = NULL, @@ -2322,5 +2589,4 @@ struct target_type cortexa8_target = { .write_phys_memory = cortex_a8_write_phys_memory, .mmu = cortex_a8_mmu, .virt2phys = cortex_a8_virt2phys, - };