X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv8_opcodes.h;h=3fda29668a27dac00376d34d08198db0249f4dfa;hp=94694bc8b161980bae7c4ab277f1c89f64261128;hb=c734202dc89bb3ee05a204140b3c890451e79686;hpb=5d00fd9d1dc504335dd71e474a3d61dec7696c40 diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h index 94694bc8b1..3fda29668a 100644 --- a/src/target/armv8_opcodes.h +++ b/src/target/armv8_opcodes.h @@ -42,6 +42,10 @@ #define SYSTEM_ELR_EL2 0b1110001000000001 #define SYSTEM_ELR_EL3 0b1111001000000001 +#define SYSTEM_SCTLR_EL1 0b1100000010000000 +#define SYSTEM_SCTLR_EL2 0b1110000010000000 +#define SYSTEM_SCTLR_EL3 0b1111000010000000 + #define SYSTEM_FPCR 0b1101101000100000 #define SYSTEM_FPSR 0b1101101000100001 #define SYSTEM_DAIF 0b1101101000010001 @@ -155,6 +159,22 @@ #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt)) #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F)) +#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd) +#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd) +#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd) + +#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd) +#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd) +#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd) + +#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd) +#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd) + +#define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt)) +#define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt)) +#define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt)) +#define ARMV8_MSR_FPSR(Rt) (0xd51b4420 | (Rt)) + #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt) enum armv8_opcode { @@ -176,6 +196,12 @@ enum armv8_opcode { ARMV8_OPC_DCCIVAC, ARMV8_OPC_ICIVAU, ARMV8_OPC_HLT, + ARMV8_OPC_STRB_IP, + ARMV8_OPC_STRH_IP, + ARMV8_OPC_STRW_IP, + ARMV8_OPC_LDRB_IP, + ARMV8_OPC_LDRH_IP, + ARMV8_OPC_LDRW_IP, ARMV8_OPC_NUM, };