X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.h;h=ec90b7150d0d8a16ab31724970156fb6922f5912;hp=d7d24adbcaa0489e7514e5bc9dade865c97a8e4b;hb=2e779198535580515dfa9c8bfe1f3fe08abdb84b;hpb=938e01d0c3ff4fedf1629cc1c1928af1c90882e9 diff --git a/src/target/armv7m.h b/src/target/armv7m.h index d7d24adbca..ec90b7150d 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -5,6 +5,9 @@ * Copyright (C) 2006 by Magnus Lundin * * lundin@mlu.mine.nu * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -23,9 +26,7 @@ #ifndef ARMV7M_COMMON_H #define ARMV7M_COMMON_H -#include "register.h" -#include "target.h" -#include "arm_jtag.h" +#include "arm_adi_v5.h" /* define for enabling armv7 gdb workarounds */ #if 1 @@ -54,7 +55,7 @@ extern char* armv7m_exception_strings[]; extern char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ -enum +enum { ARMV7M_PC = 15, ARMV7M_xPSR = 16, @@ -75,20 +76,20 @@ typedef struct armv7m_common_s reg_cache_t *core_cache; enum armv7m_mode core_mode; int exception_number; - + swjdp_common_t swjdp_info; + + /* Direct processor core register read and writes */ - int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value); - int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value); + int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); + int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value); /* register cache to processor synchronization */ int (*read_core_reg)(struct target_s *target, int num); int (*write_core_reg)(struct target_s *target, int num); - - arm_jtag_t jtag_info; int (*examine_debug_reason)(target_t *target); void (*pre_debug_entry)(target_t *target); void (*post_debug_entry)(target_t *target); - + void (*pre_restore_context)(target_t *target); void (*post_restore_context)(target_t *target); @@ -98,13 +99,13 @@ typedef struct armv7m_common_s typedef struct armv7m_algorithm_s { int common_magic; - + enum armv7m_mode core_mode; } armv7m_algorithm_t; typedef struct armv7m_core_reg_s { - u32 num; + uint32_t num; enum armv7m_regtype type; enum armv7m_mode mode; target_t *target; @@ -117,49 +118,48 @@ extern int armv7m_mode_to_number(enum armv7m_mode mode); extern int armv7m_arch_state(struct target_s *target); extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); -extern int armv7m_invalidate_core_regs(target_t *target); extern int armv7m_register_commands(struct command_context_s *cmd_ctx); extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m); -extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); +extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); extern int armv7m_invalidate_core_regs(target_t *target); extern int armv7m_restore_context(target_t *target); -extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); -extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank); +extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum); +extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank); /* Thumb mode instructions */ - + /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction * Rd: destination register * SYSm: source special register */ -#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16)) +#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction * Rd: source register * SYSm: destination special register */ -#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16)) +#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) -/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK +/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction * Rd: source register - * IF: + * IF: */ #define I_FLAG 2 -#define F_FLAG 1 -#define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16)) -#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16)) +#define F_FLAG 1 +#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) +#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) /* Breakpoint (Thumb mode) v5 onwards * Im: immediate value used by debugger */ -#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16)) +#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16)) /* Store register (Thumb mode) * Rd: source register @@ -178,12 +178,12 @@ extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 c * List: for each bit in list: store register */ #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) - + /* Load register with PC relative addressing * Rd: register to load */ -#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) - +#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) + /* Move hi register (Thumb mode) * Rd: destination register * Rm: source register