X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.h;h=8e87c7795b9e608db755c8f3560e8393b648fd97;hp=909330bde0e5bcc3a0b72b09363a26a6e5c0b883;hb=f96d6054e65708e7abdceac673f1a18fec3204b6;hpb=b0d04ab6c6c2a04130a72124e79fede7655032e2 diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 909330bde0..8e87c7795b 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -26,9 +26,6 @@ #ifndef ARMV7M_COMMON_H #define ARMV7M_COMMON_H -#include "register.h" -#include "target.h" -#include "arm_jtag.h" #include "arm_adi_v5.h" /* define for enabling armv7 gdb workarounds */ @@ -44,7 +41,7 @@ enum armv7m_mode ARMV7M_MODE_ANY = -1 }; -extern char* armv7m_mode_strings[]; +extern char *armv7m_mode_strings[]; enum armv7m_regtype { @@ -53,22 +50,43 @@ enum armv7m_regtype ARMV7M_REGISTER_MEMMAP }; -extern char* armv7m_exception_strings[]; - -extern char *armv7m_exception_string(int number); +char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ -enum +enum { + /* for convenience, the first set of indices match + * the Cortex-M3 DCRSR selectors + */ + ARMV7M_R0, + ARMV7M_R1, + ARMV7M_R2, + ARMV7M_R3, + + ARMV7M_R4, + ARMV7M_R5, + ARMV7M_R6, + ARMV7M_R7, + + ARMV7M_R8, + ARMV7M_R9, + ARMV7M_R10, + ARMV7M_R11, + + ARMV7M_R12, + ARMV7M_R13, + ARMV7M_R14, ARMV7M_PC = 15, + ARMV7M_xPSR = 16, ARMV7M_MSP, ARMV7M_PSP, + + /* this next set of indices is arbitrary */ ARMV7M_PRIMASK, ARMV7M_BASEPRI, ARMV7M_FAULTMASK, ARMV7M_CONTROL, - ARMV7NUMCOREREGS }; #define ARMV7M_COMMON_MAGIC 0x2A452A45 @@ -79,91 +97,98 @@ typedef struct armv7m_common_s reg_cache_t *core_cache; enum armv7m_mode core_mode; int exception_number; - swjdp_common_t swjdp_info; + struct swjdp_common swjdp_info; - /* Direct processor core register read and writes */ - int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value); - int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value); + int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); + int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value); /* register cache to processor synchronization */ int (*read_core_reg)(struct target_s *target, int num); int (*write_core_reg)(struct target_s *target, int num); - + int (*examine_debug_reason)(target_t *target); - void (*pre_debug_entry)(target_t *target); void (*post_debug_entry)(target_t *target); - + void (*pre_restore_context)(target_t *target); void (*post_restore_context)(target_t *target); - - void *arch_info; } armv7m_common_t; +static inline struct armv7m_common_s * +target_to_armv7m(struct target_s *target) +{ + return target->arch_info; +} + typedef struct armv7m_algorithm_s { int common_magic; - + enum armv7m_mode core_mode; } armv7m_algorithm_t; typedef struct armv7m_core_reg_s { - u32 num; + uint32_t num; enum armv7m_regtype type; - enum armv7m_mode mode; target_t *target; armv7m_common_t *armv7m_common; } armv7m_core_reg_t; -extern reg_cache_t *armv7m_build_reg_cache(target_t *target); -extern enum armv7m_mode armv7m_number_to_mode(int number); -extern int armv7m_mode_to_number(enum armv7m_mode mode); +reg_cache_t *armv7m_build_reg_cache(target_t *target); +enum armv7m_mode armv7m_number_to_mode(int number); +int armv7m_mode_to_number(enum armv7m_mode mode); -extern int armv7m_arch_state(struct target_s *target); -extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); -extern int armv7m_invalidate_core_regs(target_t *target); +int armv7m_arch_state(struct target_s *target); +int armv7m_get_gdb_reg_list(target_t *target, + reg_t **reg_list[], int *reg_list_size); -extern int armv7m_register_commands(struct command_context_s *cmd_ctx); -extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m); +int armv7m_register_commands(struct command_context_s *cmd_ctx); +int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m); -extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info); +int armv7m_run_algorithm(struct target_s *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info); -extern int armv7m_invalidate_core_regs(target_t *target); +int armv7m_invalidate_core_regs(target_t *target); -extern int armv7m_restore_context(target_t *target); +int armv7m_restore_context(target_t *target); -extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum); -extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank); +int armv7m_checksum_memory(struct target_s *target, + uint32_t address, uint32_t count, uint32_t* checksum); +int armv7m_blank_check_memory(struct target_s *target, + uint32_t address, uint32_t count, uint32_t* blank); /* Thumb mode instructions */ - + /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction * Rd: destination register * SYSm: source special register */ -#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16)) +#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction * Rd: source register * SYSm: destination special register */ -#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16)) +#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) -/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK +/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction * Rd: source register - * IF: + * IF: */ #define I_FLAG 2 -#define F_FLAG 1 -#define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16)) -#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16)) +#define F_FLAG 1 +#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) +#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) /* Breakpoint (Thumb mode) v5 onwards * Im: immediate value used by debugger */ -#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16)) +#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16)) /* Store register (Thumb mode) * Rd: source register @@ -182,12 +207,12 @@ extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 c * List: for each bit in list: store register */ #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16)) - + /* Load register with PC relative addressing * Rd: register to load */ -#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) - +#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16)) + /* Move hi register (Thumb mode) * Rd: destination register * Rm: source register