X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=9fe705af7c92c600e5a1a7deda61fe912cd14466;hp=f8c8430622ee18d415e84fc171fbaae8de517327;hb=ff5deeeeaa4f394931e3c5ccfb4cfd33beda0743;hpb=d460a7cd6cc218bd4c3cc8a98ba32a4a81a62018 diff --git a/src/target/armv7m.c b/src/target/armv7m.c index f8c8430622..9fe705af7c 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -26,7 +26,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * - * ARMv7-M Architecture, Application Level Reference Manual * + * ARMv7-M Architecture, Application Level Reference Manual * * ARM DDI 0405C (September 2008) * * * ***************************************************************************/ @@ -34,16 +34,18 @@ #include "config.h" #endif +#include "breakpoints.h" #include "armv7m.h" - -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) +#include "algorithm.h" +#include "register.h" #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -char* armv7m_mode_strings[] = +/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */ +char *armv7m_mode_strings[] = { "Thread", "Thread (User)", "Handler", }; @@ -56,26 +58,17 @@ static char *armv7m_exception_strings[] = "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; -uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -reg_t armv7m_gdb_dummy_fp_reg = -{ - "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 -}; - -uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0}; - -reg_t armv7m_gdb_dummy_fps_reg = -{ - "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 -}; - #ifdef ARMV7_GDB_HACKS uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; -reg_t armv7m_gdb_dummy_cpsr_reg = +struct reg armv7m_gdb_dummy_cpsr_reg = { - "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy cpsr register", + .value = armv7m_gdb_dummy_cpsr_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, }; #endif @@ -83,52 +76,55 @@ reg_t armv7m_gdb_dummy_cpsr_reg = * These registers are not memory-mapped. The ARMv7-M profile includes * memory mapped registers too, such as for the NVIC (interrupt controller) * and SysTick (timer) modules; those can mostly be treated as peripherals. + * + * The ARMv6-M profile is almost identical in this respect, except that it + * doesn't include basepri or faultmask registers. */ static const struct { unsigned id; char *name; + unsigned bits; } armv7m_regs[] = { - { ARMV7M_R0, "r0" }, - { ARMV7M_R1, "r1" }, - { ARMV7M_R2, "r2" }, - { ARMV7M_R3, "r3" }, - - { ARMV7M_R4, "r4" }, - { ARMV7M_R5, "r5" }, - { ARMV7M_R6, "r6" }, - { ARMV7M_R7, "r7" }, - - { ARMV7M_R8, "r8" }, - { ARMV7M_R9, "r9" }, - { ARMV7M_R10, "r10" }, - { ARMV7M_R11, "r11" }, - - { ARMV7M_R12, "r12" }, - { ARMV7M_R13, "sp" }, - { ARMV7M_R14, "lr" }, - { ARMV7M_PC, "pc" }, - - { ARMV7M_xPSR, "xPSR" }, - { ARMV7M_MSP, "msp" }, - { ARMV7M_PSP, "psp" }, - - { ARMV7M_PRIMASK, "primask" }, - { ARMV7M_BASEPRI, "basepri" }, - { ARMV7M_FAULTMASK, "faultmask" }, - { ARMV7M_CONTROL, "control" }, + { ARMV7M_R0, "r0", 32 }, + { ARMV7M_R1, "r1", 32 }, + { ARMV7M_R2, "r2", 32 }, + { ARMV7M_R3, "r3", 32 }, + + { ARMV7M_R4, "r4", 32 }, + { ARMV7M_R5, "r5", 32 }, + { ARMV7M_R6, "r6", 32 }, + { ARMV7M_R7, "r7", 32 }, + + { ARMV7M_R8, "r8", 32 }, + { ARMV7M_R9, "r9", 32 }, + { ARMV7M_R10, "r10", 32 }, + { ARMV7M_R11, "r11", 32 }, + + { ARMV7M_R12, "r12", 32 }, + { ARMV7M_R13, "sp", 32 }, + { ARMV7M_R14, "lr", 32 }, + { ARMV7M_PC, "pc", 32 }, + + { ARMV7M_xPSR, "xPSR", 32 }, + { ARMV7M_MSP, "msp", 32 }, + { ARMV7M_PSP, "psp", 32 }, + + { ARMV7M_PRIMASK, "primask", 1 }, + { ARMV7M_BASEPRI, "basepri", 8 }, + { ARMV7M_FAULTMASK, "faultmask", 1 }, + { ARMV7M_CONTROL, "control", 2 }, }; #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) -int armv7m_core_reg_arch_type = -1; -int armv7m_dummy_core_reg_arch_type = -1; - -int armv7m_restore_context(target_t *target) +/** + * Restores target context using the cache of core registers set up + * by armv7m_build_reg_cache(), calling optional core-specific hooks. + */ +int armv7m_restore_context(struct target *target) { int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); LOG_DEBUG(" "); @@ -150,6 +146,14 @@ int armv7m_restore_context(target_t *target) } /* Core state functions */ + +/** + * Maps ISR number (from xPSR) to name. + * Note that while names and meanings for the first sixteen are standardized + * (with zero not a true exception), external interrupts are only numbered. + * They are assigned by vendors, which generally assign different numbers to + * peripherals (such as UART0 or a USB peripheral controller). + */ char *armv7m_exception_string(int number) { static char enamebuf[32]; @@ -162,27 +166,27 @@ char *armv7m_exception_string(int number) return enamebuf; } -int armv7m_get_core_reg(reg_t *reg) +static int armv7m_get_core_reg(struct reg *reg) { int retval; - armv7m_core_reg_t *armv7m_reg = reg->arch_info; - target_t *target = armv7m_reg->target; - armv7m_common_t *armv7m_target = target->arch_info; + struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct target *target = armv7m_reg->target; + struct armv7m_common *armv7m = target_to_armv7m(target); if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } - retval = armv7m_target->read_core_reg(target, armv7m_reg->num); + retval = armv7m->read_core_reg(target, armv7m_reg->num); return retval; } -int armv7m_set_core_reg(reg_t *reg, uint8_t *buf) +static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) { - armv7m_core_reg_t *armv7m_reg = reg->arch_info; - target_t *target = armv7m_reg->target; + struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct target *target = armv7m_reg->target; uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -197,16 +201,14 @@ int armv7m_set_core_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int armv7m_read_core_reg(struct target_s *target, int num) +static int armv7m_read_core_reg(struct target *target, unsigned num) { uint32_t reg_value; int retval; - armv7m_core_reg_t * armv7m_core_reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_core_reg * armv7m_core_reg; + struct armv7m_common *armv7m = target_to_armv7m(target); - if ((num < 0) || (num >= ARMV7M_NUM_REGS)) + if (num >= ARMV7M_NUM_REGS) return ERROR_INVALID_ARGUMENTS; armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; @@ -218,16 +220,14 @@ int armv7m_read_core_reg(struct target_s *target, int num) return retval; } -int armv7m_write_core_reg(struct target_s *target, int num) +static int armv7m_write_core_reg(struct target *target, unsigned num) { int retval; uint32_t reg_value; - armv7m_core_reg_t *armv7m_core_reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_core_reg *armv7m_core_reg; + struct armv7m_common *armv7m = target_to_armv7m(target); - if ((num < 0) || (num >= ARMV7M_NUM_REGS)) + if (num >= ARMV7M_NUM_REGS) return ERROR_INVALID_ARGUMENTS; reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); @@ -246,29 +246,19 @@ int armv7m_write_core_reg(struct target_s *target, int num) return ERROR_OK; } -int armv7m_invalidate_core_regs(target_t *target) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - int i; - - for (i = 0; i < armv7m->core_cache->num_regs; i++) - { - armv7m->core_cache->reg_list[i].valid = 0; - armv7m->core_cache->reg_list[i].dirty = 0; - } - - return ERROR_OK; -} - -int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) +/** + * Returns generic ARM userspace registers to GDB. + * GDB doesn't quite understand that most ARMs don't have floating point + * hardware, so this also fakes a set of long-obsolete FPA registers that + * are not used in EABI based software stacks. + */ +int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); int i; *reg_list_size = 26; - *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); /* * GDB register packet format for ARM: @@ -283,11 +273,8 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ } for (i = 16; i < 24; i++) - { - (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg; - } - - (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg; + (*reg_list)[i] = &arm_gdb_dummy_fp_reg; + (*reg_list)[24] = &arm_gdb_dummy_fps_reg; #ifdef ARMV7_GDB_HACKS /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */ @@ -304,7 +291,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ } /* run to exit point. return error if exit point was not reached. */ -static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m) +static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m) { uint32_t pc; int retval; @@ -338,14 +325,17 @@ static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, in return ERROR_OK; } -int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +/** Runs a Thumb algorithm in the target. */ +int armv7m_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - armv7m_algorithm_t *armv7m_algorithm_info = arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct armv7m_algorithm *armv7m_algorithm_info = arch_info; enum armv7m_mode core_mode = armv7m->core_mode; int retval = ERROR_OK; - int i; uint32_t context[ARMV7M_NUM_REGS]; if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) @@ -362,34 +352,34 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* refresh core register cache */ /* Not needed if core register cache is always consistent with target process state */ - for (i = 0; i < ARMV7M_NUM_REGS; i++) + for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) + for (int i = 0; i < num_mem_params; i++) { if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) return retval; } - for (i = 0; i < num_reg_params; i++) + for (int i = 0; i < num_reg_params; i++) { - reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); // uint32_t regvalue; if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } // regvalue = buf_get_u32(reg_params[i].value, 0, 32); @@ -405,6 +395,11 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } + /* REVISIT speed things up (3% or so in one case) by requiring + * algorithms to include a BKPT instruction at each exit point. + * This eliminates overheads of adding/removing a breakpoint. + */ + /* ARMV7M always runs in Thumb state */ if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK) { @@ -422,7 +417,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } /* Read memory values to mem_params[] */ - for (i = 0; i < num_mem_params; i++) + for (int i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) @@ -432,29 +427,29 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } /* Copy core register values to reg_params[] */ - for (i = 0; i < num_reg_params; i++) + for (int i = 0; i < num_reg_params; i++) { if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); } } - for (i = ARMV7M_NUM_REGS; i >= 0; i--) + for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { uint32_t regvalue; regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); @@ -474,10 +469,10 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ return retval; } -int armv7m_arch_state(struct target_s *target) +/** Logs summary of ARMv7-M state for a halted target. */ +int armv7m_arch_state(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; + struct armv7m_common *armv7m = target_to_armv7m(target); uint32_t ctrl, sp; ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); @@ -485,8 +480,7 @@ int armv7m_arch_state(struct target_s *target) LOG_USER("target halted due to %s, current mode: %s %s\n" "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32, - Jim_Nvp_value2name_simple(nvp_target_debug_reason, - target->debug_reason)->name, + debug_reason_name(target), armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), @@ -496,29 +490,25 @@ int armv7m_arch_state(struct target_s *target) return ERROR_OK; } +static const struct reg_arch_type armv7m_reg_type = { + .get = armv7m_get_core_reg, + .set = armv7m_set_core_reg, +}; -reg_cache_t *armv7m_build_reg_cache(target_t *target) +/** Builds cache of architecturally defined registers. */ +struct reg_cache *armv7m_build_reg_cache(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - + struct armv7m_common *armv7m = target_to_armv7m(target); int num_regs = ARMV7M_NUM_REGS; - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = calloc(num_regs, sizeof(reg_t)); - armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t)); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); + struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg)); int i; - if (armv7m_core_reg_arch_type == -1) - { - armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg); - } - - register_init_dummy(&armv7m_gdb_dummy_fps_reg); #ifdef ARMV7_GDB_HACKS register_init_dummy(&armv7m_gdb_dummy_cpsr_reg); #endif - register_init_dummy(&armv7m_gdb_dummy_fp_reg); /* Build the process context cache */ cache->name = "arm v7m registers"; @@ -534,29 +524,21 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) arch_info[i].target = target; arch_info[i].armv7m_common = armv7m; reg_list[i].name = armv7m_regs[i].name; - reg_list[i].size = 32; + reg_list[i].size = armv7m_regs[i].bits; reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; - reg_list[i].arch_type = armv7m_core_reg_arch_type; + reg_list[i].type = &armv7m_reg_type; reg_list[i].arch_info = &arch_info[i]; } return cache; } -int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +/** Sets up target as a generic ARMv7-M core */ +int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) { - armv7m_build_reg_cache(target); - - return ERROR_OK; -} - -int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) -{ - /* register arch-specific functions */ + armv7m->common_magic = ARMV7M_COMMON_MAGIC; target->arch_info = armv7m; armv7m->read_core_reg = armv7m_read_core_reg; @@ -565,14 +547,16 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) return ERROR_OK; } -int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +/** Generates a CRC32 checksum of a memory region. */ +int armv7m_checksum_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* checksum) { - working_area_t *crc_algorithm; - armv7m_algorithm_t armv7m_info; - reg_param_t reg_params[2]; + struct working_area *crc_algorithm; + struct armv7m_algorithm armv7m_info; + struct reg_param reg_params[2]; int retval; - uint16_t cortex_m3_crc_code[] = { + static const uint16_t cortex_m3_crc_code[] = { 0x4602, /* mov r2, r0 */ 0xF04F, 0x30FF, /* mov r0, #0xffffffff */ 0x460B, /* mov r3, r1 */ @@ -611,7 +595,7 @@ int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t c } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++) + for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++) if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK) { return retval; @@ -646,23 +630,25 @@ int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t c return ERROR_OK; } -int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) +/** Checks whether a memory region is zeroed. */ +int armv7m_blank_check_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* blank) { - working_area_t *erase_check_algorithm; - reg_param_t reg_params[3]; - armv7m_algorithm_t armv7m_info; + struct working_area *erase_check_algorithm; + struct reg_param reg_params[3]; + struct armv7m_algorithm armv7m_info; int retval; uint32_t i; - uint16_t erase_check_code[] = + static const uint16_t erase_check_code[] = { - /* loop: */ - 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ - 0xEA02, 0x0203, /* and r2, r2, r3 */ - 0x3901, /* subs r1, r1, #1 */ - 0xD1F9, /* bne loop */ - /* end: */ - 0xE7FE, /* b end */ + /* loop: */ + 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ + 0xEA02, 0x0203, /* and r2, r2, r3 */ + 0x3901, /* subs r1, r1, #1 */ + 0xD1F9, /* bne loop */ + /* end: */ + 0xE7FE, /* b end */ }; /* make sure we have a working area */ @@ -672,7 +658,7 @@ int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_ } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++) + for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]); armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; @@ -708,120 +694,195 @@ int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_ return ERROR_OK; } -/* - * Return the debug ap baseaddress in hexadecimal; - * no extra output to simplify script processing - */ -static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t apsel, apselsave, baseaddr; - int retval; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct reg *r = armv7m->core_cache->reg_list + 15; + bool result = false; - apsel = swjdp->apsel; - apselsave = swjdp->apsel; - if (argc > 0) + + /* if we halted last time due to a bkpt instruction + * then we have to manually step over it, otherwise + * the core will break again */ + + if (target->debug_reason == DBG_REASON_BREAKPOINT) { - apsel = strtoul(args[0], NULL, 0); + uint16_t op; + uint32_t pc = buf_get_u32(r->value, 0, 32); + + pc &= ~1; + if (target_read_u16(target, pc, &op) == ERROR_OK) + { + if ((op & 0xFF00) == 0xBE00) + { + pc = buf_get_u32(r->value, 0, 32) + 2; + buf_set_u32(r->value, 0, 32, pc); + r->dirty = true; + r->valid = true; + result = true; + LOG_DEBUG("Skipping over BKPT instruction"); + } + } } - if (apselsave != apsel) - { - dap_ap_select(swjdp, apsel); + + if (inst_found) { + *inst_found = result; } - dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr); + return ERROR_OK; +} - if (apselsave != apsel) - { - dap_ap_select(swjdp, apselsave); +/*--------------------------------------------------------------------------*/ + +/* + * Only stuff below this line should need to verify that its target + * is an ARMv7-M node. + */ + + +/* + * Return the debug ap baseaddress in hexadecimal; + * no extra output to simplify script processing + */ +COMMAND_HANDLER(handle_dap_baseaddr_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; + + if (!is_armv7m(armv7m)) { + command_print(CMD_CTX, "current target isn't an ARM7-M"); + return ERROR_TARGET_INVALID; } - return retval; + return CALL_COMMAND_HANDLER(dap_baseaddr_command, swjdp); } - /* * Return the debug ap id in hexadecimal; * no extra output to simplify script processing */ -extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_dap_apid_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; - return dap_apid_command(cmd_ctx, swjdp, args, argc); + if (!is_armv7m(armv7m)) { + command_print(CMD_CTX, "current target isn't an ARM7-M"); + return ERROR_TARGET_INVALID; + } + + return CALL_COMMAND_HANDLER(dap_apid_command, swjdp); } -static int handle_dap_apsel_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_dap_apsel_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; + + if (!is_armv7m(armv7m)) { + command_print(CMD_CTX, "current target isn't an ARM7-M"); + return ERROR_TARGET_INVALID; + } - return dap_apsel_command(cmd_ctx, swjdp, args, argc); + return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp); } -static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_dap_memaccess_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; + + if (!is_armv7m(armv7m)) { + command_print(CMD_CTX, "current target isn't an ARM7-M"); + return ERROR_TARGET_INVALID; + } - return dap_memaccess_command(cmd_ctx, swjdp, args, argc); + return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp); } -static int handle_dap_info_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_dap_info_command) { - target_t *target = get_current_target(cmd_ctx); - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct swjdp_common *swjdp = &armv7m->swjdp_info; uint32_t apsel; - apsel = swjdp->apsel; - if (argc > 0) - apsel = strtoul(args[0], NULL, 0); - - return dap_info_command(cmd_ctx, swjdp, apsel); -} + if (!is_armv7m(armv7m)) { + command_print(CMD_CTX, "current target isn't an ARM7-M"); + return ERROR_TARGET_INVALID; + } -int armv7m_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm_adi_v5_dap_cmd; - - arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", - NULL, COMMAND_ANY, - "cortex dap specific commands"); - - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", - handle_dap_info_command, COMMAND_EXEC, - "Displays dap info for ap [num]," - "default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", - handle_dap_apsel_command, COMMAND_EXEC, - "Select a different AP [num] (default 0)"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", - handle_dap_apid_command, COMMAND_EXEC, - "Displays id reg from AP [num], " - "default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", - handle_dap_baseaddr_command, COMMAND_EXEC, - "Displays debug base address from AP [num]," - "default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", - handle_dap_memaccess_command, COMMAND_EXEC, - "set/get number of extra tck for mem-ap " - "memory bus access [0-255]"); + switch (CMD_ARGC) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } - return ERROR_OK; + return dap_info_command(CMD_CTX, swjdp, apsel); } + +/* FIXME this table should be part of generic DAP support, and + * be shared by the ARMv7-A/R and ARMv7-M support ... + */ +static const struct command_registration armv7m_exec_command_handlers[] = { + { + .name = "info", + .handler = handle_dap_info_command, + .mode = COMMAND_EXEC, + .help = "display ROM table for MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "apsel", + .handler = handle_dap_apsel_command, + .mode = COMMAND_EXEC, + .help = "Set the currently selected AP (default 0) " + "and display the result", + .usage = "[ap_num]", + }, + { + .name = "apid", + .handler = handle_dap_apid_command, + .mode = COMMAND_EXEC, + .help = "return ID register from AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "baseaddr", + .handler = handle_dap_baseaddr_command, + .mode = COMMAND_EXEC, + .help = "return debug base address from MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "memaccess", + .handler = handle_dap_memaccess_command, + .mode = COMMAND_EXEC, + .help = "set/get number of extra tck for MEM-AP memory " + "bus access [0-255]", + .usage = "[cycles]", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration armv7m_command_handlers[] = { + { + .name = "dap", + .mode = COMMAND_EXEC, + .help = "Cortex DAP command group", + .chain = armv7m_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +};