X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=9740a28c5790e6caafe5537e8d594601e0d84a8c;hp=f0829c61770e62752d4a59b677ca5533f6f65d13;hb=f4f87cb4726fbba4a03e2eda1759faf1c47ab4ba;hpb=1d9fba8c1488c3774c8bde737c2d658b1f525d09 diff --git a/src/target/armv7m.c b/src/target/armv7m.c index f0829c6177..9740a28c57 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -30,6 +30,7 @@ * ARM DDI 0405C (September 2008) * * * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -39,30 +40,39 @@ #include "algorithm.h" #include "register.h" - #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */ -char *armv7m_mode_strings[] = -{ - "Thread", "Thread (User)", "Handler", -}; - -static char *armv7m_exception_strings[] = -{ +static char *armv7m_exception_strings[] = { "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; +/* PSP is used in some thread modes */ +const int armv7m_psp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + +/* MSP is used in handler and some thread modes */ +const int armv7m_msp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + #ifdef ARMV7_GDB_HACKS uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; -struct reg armv7m_gdb_dummy_cpsr_reg = -{ +struct reg armv7m_gdb_dummy_cpsr_reg = { .name = "GDB dummy cpsr register", .value = armv7m_gdb_dummy_cpsr_value, .dirty = 0, @@ -82,7 +92,7 @@ struct reg armv7m_gdb_dummy_cpsr_reg = */ static const struct { unsigned id; - char *name; + const char *name; unsigned bits; } armv7m_regs[] = { { ARMV7M_R0, "r0", 32 }, @@ -115,7 +125,7 @@ static const struct { { ARMV7M_CONTROL, "control", 2 }, }; -#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) +#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) /** * Restores target context using the cache of core registers set up @@ -125,17 +135,17 @@ int armv7m_restore_context(struct target *target) { int i; struct armv7m_common *armv7m = target_to_armv7m(target); + struct reg_cache *cache = armv7m->arm.core_cache; LOG_DEBUG(" "); if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); - for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) - { - if (armv7m->core_cache->reg_list[i].dirty) - { - armv7m->write_core_reg(target, i); + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { + if (cache->reg_list[i].dirty) { + uint32_t value = buf_get_u32(cache->reg_list[i].value, 0, 32); + armv7m->arm.write_core_reg(target, &cache->reg_list[i], i, ARM_MODE_ANY, value); } } @@ -166,30 +176,26 @@ char *armv7m_exception_string(int number) static int armv7m_get_core_reg(struct reg *reg) { int retval; - struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct arm_reg *armv7m_reg = reg->arch_info; struct target *target = armv7m_reg->target; - struct armv7m_common *armv7m = target_to_armv7m(target); + struct arm *arm = target_to_arm(target); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } - retval = armv7m->read_core_reg(target, armv7m_reg->num); + retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode); return retval; } static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) { - struct armv7m_core_reg *armv7m_reg = reg->arch_info; + struct arm_reg *armv7m_reg = reg->arch_info; struct target *target = armv7m_reg->target; uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; @@ -198,47 +204,51 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_OK; } -static int armv7m_read_core_reg(struct target *target, unsigned num) +static int armv7m_read_core_reg(struct target *target, struct reg *r, + int num, enum arm_mode mode) { uint32_t reg_value; int retval; - struct armv7m_core_reg * armv7m_core_reg; + struct arm_reg *armv7m_core_reg; struct armv7m_common *armv7m = target_to_armv7m(target); - if (num >= ARMV7M_NUM_REGS) - return ERROR_INVALID_ARGUMENTS; + assert(num < (int)armv7m->arm.core_cache->num_regs); - armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; - retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®_value); - buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value); - armv7m->core_cache->reg_list[num].valid = 1; - armv7m->core_cache->reg_list[num].dirty = 0; + armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info; + retval = armv7m->load_core_reg_u32(target, + armv7m_core_reg->num, ®_value); + + buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value); + armv7m->arm.core_cache->reg_list[num].valid = 1; + armv7m->arm.core_cache->reg_list[num].dirty = 0; return retval; } -static int armv7m_write_core_reg(struct target *target, unsigned num) +static int armv7m_write_core_reg(struct target *target, struct reg *r, + int num, enum arm_mode mode, uint32_t value) { int retval; uint32_t reg_value; - struct armv7m_core_reg *armv7m_core_reg; + struct arm_reg *armv7m_core_reg; struct armv7m_common *armv7m = target_to_armv7m(target); - if (num >= ARMV7M_NUM_REGS) - return ERROR_INVALID_ARGUMENTS; + assert(num < (int)armv7m->arm.core_cache->num_regs); - reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); - armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; - retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value); - if (retval != ERROR_OK) - { + reg_value = buf_get_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32); + armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info; + retval = armv7m->store_core_reg_u32(target, + armv7m_core_reg->num, + reg_value); + if (retval != ERROR_OK) { LOG_ERROR("JTAG failure"); - armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; + armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); - armv7m->core_cache->reg_list[num].valid = 1; - armv7m->core_cache->reg_list[num].dirty = 0; + + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value); + armv7m->arm.core_cache->reg_list[num].valid = 1; + armv7m->arm.core_cache->reg_list[num].dirty = 0; return ERROR_OK; } @@ -255,7 +265,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int int i; *reg_list_size = 26; - *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); /* * GDB register packet format for ARM: @@ -265,9 +275,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int * - CPSR */ for (i = 0; i < 16; i++) - { - (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; - } + (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i]; for (i = 16; i < 24; i++) (*reg_list)[i] = &arm_gdb_dummy_fp_reg; @@ -279,7 +287,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int /* ARMV7M is always in thumb mode, try to make GDB understand this * if it does not support this arch */ - *((char*)armv7m->arm.pc->value) |= 1; + *((char *)armv7m->arm.pc->value) |= 1; #else (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR]; #endif @@ -287,170 +295,217 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int return ERROR_OK; } -/* run to exit point. return error if exit point was not reached. */ -static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m) +/** Runs a Thumb algorithm in the target. */ +int armv7m_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { - uint32_t pc; int retval; - /* This code relies on the target specific resume() and poll()->debug_entry() - * sequence to write register values to the processor and the read them back */ - if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) - { - return retval; - } - retval = target_wait_state(target, TARGET_HALTED, timeout_ms); - /* If the target fails to halt due to the breakpoint, force a halt */ - if (retval != ERROR_OK || target->state != TARGET_HALTED) - { - if ((retval = target_halt(target)) != ERROR_OK) - return retval; - if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) - { - return retval; - } - return ERROR_TARGET_TIMEOUT; - } + retval = armv7m_start_algorithm(target, + num_mem_params, mem_params, + num_reg_params, reg_params, + entry_point, exit_point, + arch_info); - armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); - if (pc != exit_point) - { - LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc); - return ERROR_TARGET_TIMEOUT; - } + if (retval == ERROR_OK) + retval = armv7m_wait_algorithm(target, + num_mem_params, mem_params, + num_reg_params, reg_params, + exit_point, timeout_ms, + arch_info); - return ERROR_OK; + return retval; } -/** Runs a Thumb algorithm in the target. */ -int armv7m_run_algorithm(struct target *target, +/** Starts a Thumb algorithm in the target. */ +int armv7m_start_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) + void *arch_info) { struct armv7m_common *armv7m = target_to_armv7m(target); struct armv7m_algorithm *armv7m_algorithm_info = arch_info; - enum armv7m_mode core_mode = armv7m->core_mode; + enum arm_mode core_mode = armv7m->arm.core_mode; int retval = ERROR_OK; - uint32_t context[ARMV7M_NUM_REGS]; /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint * at the exit point */ - if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) - { + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV7M target"); return ERROR_TARGET_INVALID; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - /* refresh core register cache */ - /* Not needed if core register cache is always consistent with target process state */ - for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) - { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); - context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); + /* refresh core register cache + * Not needed if core register cache is always consistent with target process state */ + for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) { + + armv7m_algorithm_info->context[i] = buf_get_u32( + armv7m->arm.core_cache->reg_list[i].value, + 0, + 32); } - for (int i = 0; i < num_mem_params; i++) - { - if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) + for (int i = 0; i < num_mem_params; i++) { + /* TODO: Write only out params */ + retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; } - for (int i = 0; i < num_reg_params; i++) - { - struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); -// uint32_t regvalue; + for (int i = 0; i < num_reg_params; i++) { + struct reg *reg = + register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0); +/* uint32_t regvalue; */ - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); + return ERROR_COMMAND_SYNTAX_ERROR; } -// regvalue = buf_get_u32(reg_params[i].value, 0, 32); +/* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */ armv7m_set_core_reg(reg, reg_params[i].value); } - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) - { + if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY && + armv7m_algorithm_info->core_mode != core_mode) { + + /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */ + if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) { + armv7m_algorithm_info->core_mode = ARM_MODE_THREAD; + LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead"); + } + LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, - 0, 1, armv7m_algorithm_info->core_mode); - armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, + 0, 1, armv7m_algorithm_info->core_mode); + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } - retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m); + /* save previous core mode */ + armv7m_algorithm_info->core_mode = core_mode; - if (retval != ERROR_OK) - { - return retval; + retval = target_resume(target, 0, entry_point, 1, 1); + + return retval; +} + +/** Waits for an algorithm in the target. */ +int armv7m_wait_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t exit_point, int timeout_ms, + void *arch_info) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + struct armv7m_algorithm *armv7m_algorithm_info = arch_info; + int retval = ERROR_OK; + uint32_t pc; + + /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint + * at the exit point */ + + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { + LOG_ERROR("current target isn't an ARMV7M target"); + return ERROR_TARGET_INVALID; + } + + retval = target_wait_state(target, TARGET_HALTED, timeout_ms); + /* If the target fails to halt due to the breakpoint, force a halt */ + if (retval != ERROR_OK || target->state != TARGET_HALTED) { + retval = target_halt(target); + if (retval != ERROR_OK) + return retval; + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval != ERROR_OK) + return retval; + return ERROR_TARGET_TIMEOUT; + } + + armv7m->load_core_reg_u32(target, 15, &pc); + if (exit_point && (pc != exit_point)) { + LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32, + pc, + exit_point); + return ERROR_TARGET_TIMEOUT; } /* Read memory values to mem_params[] */ - for (int i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { + for (int i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction != PARAM_OUT) { + retval = target_read_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; - } + } } /* Copy core register values to reg_params[] */ - for (int i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { - struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); + for (int i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { + struct reg *reg = register_get_by_name(armv7m->arm.core_cache, + reg_params[i].reg_name, + 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; + if (reg->size != reg_params[i].size) { + LOG_ERROR( + "BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); + return ERROR_COMMAND_SYNTAX_ERROR; } buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); } } - for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) - { + for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { uint32_t regvalue; - regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); - if (regvalue != context[i]) - { + regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32); + if (regvalue != armv7m_algorithm_info->context[i]) { LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, - armv7m->core_cache->reg_list[i].name, context[i]); - buf_set_u32(armv7m->core_cache->reg_list[i].value, - 0, 32, context[i]); - armv7m->core_cache->reg_list[i].valid = 1; - armv7m->core_cache->reg_list[i].dirty = 1; + armv7m->arm.core_cache->reg_list[i].name, + armv7m_algorithm_info->context[i]); + buf_set_u32(armv7m->arm.core_cache->reg_list[i].value, + 0, 32, armv7m_algorithm_info->context[i]); + armv7m->arm.core_cache->reg_list[i].valid = 1; + armv7m->arm.core_cache->reg_list[i].dirty = 1; } } - armv7m->core_mode = core_mode; + /* restore previous core mode */ + if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) { + LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); + buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, + 0, 1, armv7m_algorithm_info->core_mode); + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + } + + armv7m->arm.core_mode = armv7m_algorithm_info->core_mode; return retval; } @@ -462,13 +517,13 @@ int armv7m_arch_state(struct target *target) struct arm *arm = &armv7m->arm; uint32_t ctrl, sp; - ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); - sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32); + ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); + sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32); LOG_USER("target halted due to %s, current mode: %s %s\n" "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s", debug_reason_name(target), - armv7m_mode_strings[armv7m->core_mode], + arm_mode_name(arm->core_mode), armv7m_exception_string(armv7m->exception_number), buf_get_u32(arm->cpsr->value, 0, 32), buf_get_u32(arm->pc->value, 0, 32), @@ -478,6 +533,7 @@ int armv7m_arch_state(struct target *target) return ERROR_OK; } + static const struct reg_arch_type armv7m_reg_type = { .get = armv7m_get_core_reg, .set = armv7m_set_core_reg, @@ -492,7 +548,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); - struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg)); + struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg)); int i; #ifdef ARMV7_GDB_HACKS @@ -505,13 +561,12 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) cache->reg_list = reg_list; cache->num_regs = num_regs; (*cache_p) = cache; - armv7m->core_cache = cache; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { arch_info[i].num = armv7m_regs[i].id; arch_info[i].target = target; - arch_info[i].armv7m_common = armv7m; + arch_info[i].arm = arm; + reg_list[i].name = armv7m_regs[i].name; reg_list[i].size = armv7m_regs[i].bits; reg_list[i].value = calloc(1, 4); @@ -527,7 +582,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) return cache; } -int armv7m_setup_semihosting(struct target *target, int enable) +static int armv7m_setup_semihosting(struct target *target, int enable) { /* nothing todo for armv7m */ return ERROR_OK; @@ -539,75 +594,74 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) struct arm *arm = &armv7m->arm; armv7m->common_magic = ARMV7M_COMMON_MAGIC; + armv7m->fp_feature = FP_NONE; arm->core_type = ARM_MODE_THREAD; arm->arch_info = armv7m; arm->setup_semihosting = armv7m_setup_semihosting; - /* FIXME remove v7m-specific r/w core_reg functions; - * use the generic ARM core support.. - */ - armv7m->read_core_reg = armv7m_read_core_reg; - armv7m->write_core_reg = armv7m_write_core_reg; + arm->read_core_reg = armv7m_read_core_reg; + arm->write_core_reg = armv7m_write_core_reg; return arm_init_arch_info(target, arm); } /** Generates a CRC32 checksum of a memory region. */ int armv7m_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* checksum) + uint32_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct armv7m_algorithm armv7m_info; struct reg_param reg_params[2]; int retval; - static const uint16_t cortex_m3_crc_code[] = { - 0x4602, /* mov r2, r0 */ - 0xF04F, 0x30FF, /* mov r0, #0xffffffff */ - 0x460B, /* mov r3, r1 */ - 0xF04F, 0x0400, /* mov r4, #0 */ - 0xE013, /* b ncomp */ - /* nbyte: */ - 0x5D11, /* ldrb r1, [r2, r4] */ - 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */ - 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */ - - 0xF04F, 0x0500, /* mov r5, #0 */ - /* loop: */ - 0x2800, /* cmp r0, #0 */ - 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */ - 0xF105, 0x0501, /* add r5, r5, #1 */ - 0x4630, /* mov r0, r6 */ - 0xBFB8, /* it lt */ - 0xEA86, 0x0007, /* eor r0, r6, r7 */ - 0x2D08, /* cmp r5, #8 */ - 0xD1F4, /* bne loop */ - - 0xF104, 0x0401, /* add r4, r4, #1 */ - /* ncomp: */ - 0x429C, /* cmp r4, r3 */ - 0xD1E9, /* bne nbyte */ - 0xBE00, /* bkpt #0 */ - 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */ + /* see contrib/loaders/checksum/armv7m_crc.s for src */ + + static const uint8_t cortex_m3_crc_code[] = { + /* main: */ + 0x02, 0x46, /* mov r2, r0 */ + 0x00, 0x20, /* movs r0, #0 */ + 0xC0, 0x43, /* mvns r0, r0 */ + 0x0A, 0x4E, /* ldr r6, CRC32XOR */ + 0x0B, 0x46, /* mov r3, r1 */ + 0x00, 0x24, /* movs r4, #0 */ + 0x0D, 0xE0, /* b ncomp */ + /* nbyte: */ + 0x11, 0x5D, /* ldrb r1, [r2, r4] */ + 0x09, 0x06, /* lsls r1, r1, #24 */ + 0x48, 0x40, /* eors r0, r0, r1 */ + 0x00, 0x25, /* movs r5, #0 */ + /* loop: */ + 0x00, 0x28, /* cmp r0, #0 */ + 0x02, 0xDA, /* bge notset */ + 0x40, 0x00, /* lsls r0, r0, #1 */ + 0x70, 0x40, /* eors r0, r0, r6 */ + 0x00, 0xE0, /* b cont */ + /* notset: */ + 0x40, 0x00, /* lsls r0, r0, #1 */ + /* cont: */ + 0x01, 0x35, /* adds r5, r5, #1 */ + 0x08, 0x2D, /* cmp r5, #8 */ + 0xF6, 0xD1, /* bne loop */ + 0x01, 0x34, /* adds r4, r4, #1 */ + /* ncomp: */ + 0x9C, 0x42, /* cmp r4, r3 */ + 0xEF, 0xD1, /* bne nbyte */ + 0x00, 0xBE, /* bkpt #0 */ + 0xB7, 0x1D, 0xC1, 0x04 /* CRC32XOR: .word 0x04c11db7 */ }; - uint32_t i; - - if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK) - { - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm); + if (retval != ERROR_OK) + return retval; - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++) - if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK) - { - return retval; - } + retval = target_write_buffer(target, crc_algorithm->address, + sizeof(cortex_m3_crc_code), (uint8_t *)cortex_m3_crc_code); + if (retval != ERROR_OK) + goto cleanup; armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_info.core_mode = ARMV7M_MODE_ANY; + armv7m_info.core_mode = ARM_MODE_ANY; init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -615,58 +669,59 @@ int armv7m_checksum_memory(struct target *target, buf_set_u32(reg_params[0].value, 0, 32, address); buf_set_u32(reg_params[1].value, 0, 32, count); - if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK) - { - LOG_ERROR("error executing cortex_m3 crc algorithm"); - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - target_free_working_area(target, crc_algorithm); - return retval; - } + int timeout = 20000 * (1 + (count / (1024 * 1024))); - *checksum = buf_get_u32(reg_params[0].value, 0, 32); + retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, + crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6), + timeout, &armv7m_info); + + if (retval == ERROR_OK) + *checksum = buf_get_u32(reg_params[0].value, 0, 32); + else + LOG_ERROR("error executing cortex_m3 crc algorithm"); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); +cleanup: target_free_working_area(target, crc_algorithm); - return ERROR_OK; + return retval; } /** Checks whether a memory region is zeroed. */ int armv7m_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* blank) + uint32_t address, uint32_t count, uint32_t *blank) { struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; struct armv7m_algorithm armv7m_info; int retval; - uint32_t i; - static const uint16_t erase_check_code[] = - { + /* see contrib/loaders/erase_check/armv7m_erase_check.s for src */ + + static const uint8_t erase_check_code[] = { /* loop: */ - 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ - 0xEA02, 0x0203, /* and r2, r2, r3 */ - 0x3901, /* subs r1, r1, #1 */ - 0xD1F9, /* bne loop */ - 0xBE00, /* bkpt #0 */ + 0x03, 0x78, /* ldrb r3, [r0] */ + 0x01, 0x30, /* adds r0, #1 */ + 0x1A, 0x40, /* ands r2, r2, r3 */ + 0x01, 0x39, /* subs r1, r1, #1 */ + 0xFA, 0xD1, /* bne loop */ + 0x00, 0xBE /* bkpt #0 */ }; /* make sure we have a working area */ - if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) - { + if (target_alloc_working_area(target, sizeof(erase_check_code), + &erase_check_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) - target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]); + retval = target_write_buffer(target, erase_check_algorithm->address, + sizeof(erase_check_code), (uint8_t *)erase_check_code); + if (retval != ERROR_OK) + return retval; armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_info.core_mode = ARMV7M_MODE_ANY; + armv7m_info.core_mode = ARM_MODE_ANY; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); @@ -677,17 +732,18 @@ int armv7m_blank_check_memory(struct target *target, init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); buf_set_u32(reg_params[2].value, 0, 32, 0xff); - if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK) - { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - target_free_working_area(target, erase_check_algorithm); - return 0; - } + retval = target_run_algorithm(target, + 0, + NULL, + 3, + reg_params, + erase_check_algorithm->address, + erase_check_algorithm->address + (sizeof(erase_check_code) - 2), + 10000, + &armv7m_info); - *blank = buf_get_u32(reg_params[2].value, 0, 32); + if (retval == ERROR_OK) + *blank = buf_get_u32(reg_params[2].value, 0, 32); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -695,7 +751,7 @@ int armv7m_blank_check_memory(struct target *target, target_free_working_area(target, erase_check_algorithm); - return ERROR_OK; + return retval; } int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) @@ -709,16 +765,13 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) * then we have to manually step over it, otherwise * the core will break again */ - if (target->debug_reason == DBG_REASON_BREAKPOINT) - { + if (target->debug_reason == DBG_REASON_BREAKPOINT) { uint16_t op; uint32_t pc = buf_get_u32(r->value, 0, 32); pc &= ~1; - if (target_read_u16(target, pc, &op) == ERROR_OK) - { - if ((op & 0xFF00) == 0xBE00) - { + if (target_read_u16(target, pc, &op) == ERROR_OK) { + if ((op & 0xFF00) == 0xBE00) { pc = buf_get_u32(r->value, 0, 32) + 2; buf_set_u32(r->value, 0, 32, pc); r->dirty = true; @@ -729,9 +782,8 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) } } - if (inst_found) { + if (inst_found) *inst_found = result; - } return ERROR_OK; }