X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=49e50f4da6008c312b4fcce2e79f38a53042c566;hp=02a664aa6517b1e291580798e84aa40616cf8e1b;hb=3541ed3aa3beb93c80bb2a01be429dacdec33919;hpb=8b994145b849c40b0a195c3fb332b9770b2f9097 diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 02a664aa65..49e50f4da6 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -26,7 +26,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * - * ARMv7-M Architecture, Application Level Reference Manual * + * ARMv7-M Architecture, Application Level Reference Manual * * ARM DDI 0405C (September 2008) * * * ***************************************************************************/ @@ -36,17 +36,20 @@ #include "armv7m.h" +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) + #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -char* armv7m_mode_strings[] = +/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */ +char *armv7m_mode_strings[] = { "Thread", "Thread (User)", "Handler", }; -char* armv7m_exception_strings[] = +static char *armv7m_exception_strings[] = { "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", @@ -54,26 +57,18 @@ char* armv7m_exception_strings[] = "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; -char* armv7m_core_reg_list[] = -{ - /* Registers accessed through core debug */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", - "sp", "lr", "pc", - "xPSR", "msp", "psp", - /* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */ - "spec20", +static uint8_t armv7m_gdb_dummy_fp_value[12] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -reg_t armv7m_gdb_dummy_fp_reg = +static reg_t armv7m_gdb_dummy_fp_reg = { "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 }; -uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0}; -reg_t armv7m_gdb_dummy_fps_reg = +static reg_t armv7m_gdb_dummy_fps_reg = { "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 }; @@ -87,40 +82,57 @@ reg_t armv7m_gdb_dummy_cpsr_reg = }; #endif -armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = -{ - /* CORE_GP are accesible using the core debug registers */ - {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - - {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */ - {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ - {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - - /* FIXME the register numbers here are core-specific. - * Numbers 0..18 above work for all Cortex-M3 revisions. - * Number 20 below works for CM3 r2p0 and later. - */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, +/* + * These registers are not memory-mapped. The ARMv7-M profile includes + * memory mapped registers too, such as for the NVIC (interrupt controller) + * and SysTick (timer) modules; those can mostly be treated as peripherals. + * + * The ARMv6-M profile is almost identical in this respect, except that it + * doesn't include basepri or faultmask registers. + */ +static const struct { + unsigned id; + char *name; + unsigned bits; +} armv7m_regs[] = { + { ARMV7M_R0, "r0", 32 }, + { ARMV7M_R1, "r1", 32 }, + { ARMV7M_R2, "r2", 32 }, + { ARMV7M_R3, "r3", 32 }, + + { ARMV7M_R4, "r4", 32 }, + { ARMV7M_R5, "r5", 32 }, + { ARMV7M_R6, "r6", 32 }, + { ARMV7M_R7, "r7", 32 }, + + { ARMV7M_R8, "r8", 32 }, + { ARMV7M_R9, "r9", 32 }, + { ARMV7M_R10, "r10", 32 }, + { ARMV7M_R11, "r11", 32 }, + + { ARMV7M_R12, "r12", 32 }, + { ARMV7M_R13, "sp", 32 }, + { ARMV7M_R14, "lr", 32 }, + { ARMV7M_PC, "pc", 32 }, + + { ARMV7M_xPSR, "xPSR", 32 }, + { ARMV7M_MSP, "msp", 32 }, + { ARMV7M_PSP, "psp", 32 }, + + { ARMV7M_PRIMASK, "primask", 1 }, + { ARMV7M_BASEPRI, "basepri", 8 }, + { ARMV7M_FAULTMASK, "faultmask", 1 }, + { ARMV7M_CONTROL, "control", 2 }, }; -int armv7m_core_reg_arch_type = -1; -int armv7m_dummy_core_reg_arch_type = -1; +#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) + +static int armv7m_core_reg_arch_type = -1; +/** + * Restores target context using the cache of core registers set up + * by armv7m_build_reg_cache(), calling optional core-specific hooks. + */ int armv7m_restore_context(target_t *target) { int i; @@ -133,7 +145,7 @@ int armv7m_restore_context(target_t *target) if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { if (armv7m->core_cache->reg_list[i].dirty) { @@ -148,6 +160,14 @@ int armv7m_restore_context(target_t *target) } /* Core state functions */ + +/** + * Maps ISR number (from xPSR) to name. + * Note that while names and meanings for the first sixteen are standardized + * (with zero not a true exception), external interrupts are only numbered. + * They are assigned by vendors, which generally assign different numbers to + * peripherals (such as UART0 or a USB peripheral controller). + */ char *armv7m_exception_string(int number) { static char enamebuf[32]; @@ -160,7 +180,7 @@ char *armv7m_exception_string(int number) return enamebuf; } -int armv7m_get_core_reg(reg_t *reg) +static int armv7m_get_core_reg(reg_t *reg) { int retval; armv7m_core_reg_t *armv7m_reg = reg->arch_info; @@ -177,7 +197,7 @@ int armv7m_get_core_reg(reg_t *reg) return retval; } -int armv7m_set_core_reg(reg_t *reg, uint8_t *buf) +static int armv7m_set_core_reg(reg_t *reg, uint8_t *buf) { armv7m_core_reg_t *armv7m_reg = reg->arch_info; target_t *target = armv7m_reg->target; @@ -195,7 +215,7 @@ int armv7m_set_core_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int armv7m_read_core_reg(struct target_s *target, int num) +static int armv7m_read_core_reg(struct target_s *target, int num) { uint32_t reg_value; int retval; @@ -204,7 +224,7 @@ int armv7m_read_core_reg(struct target_s *target, int num) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if ((num < 0) || (num >= ARMV7M_NUM_REGS)) return ERROR_INVALID_ARGUMENTS; armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; @@ -216,7 +236,7 @@ int armv7m_read_core_reg(struct target_s *target, int num) return retval; } -int armv7m_write_core_reg(struct target_s *target, int num) +static int armv7m_write_core_reg(struct target_s *target, int num) { int retval; uint32_t reg_value; @@ -225,7 +245,7 @@ int armv7m_write_core_reg(struct target_s *target, int num) /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if ((num < 0) || (num >= ARMV7M_NUM_REGS)) return ERROR_INVALID_ARGUMENTS; reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); @@ -244,6 +264,7 @@ int armv7m_write_core_reg(struct target_s *target, int num) return ERROR_OK; } +/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */ int armv7m_invalidate_core_regs(target_t *target) { /* get pointers to arch-specific information */ @@ -259,6 +280,12 @@ int armv7m_invalidate_core_regs(target_t *target) return ERROR_OK; } +/** + * Returns generic ARM userspace registers to GDB. + * GDB doesn't quite understand that most ARMs don't have floating point + * hardware, so this also fakes a set of long-obsolete FPA registers that + * are not used in EABI based software stacks. + */ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) { /* get pointers to arch-specific information */ @@ -268,6 +295,13 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ *reg_list_size = 26; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + /* + * GDB register packet format for ARM: + * - the first 16 registers are r0..r15 + * - (obsolete) 8 FPA registers + * - (obsolete) FPA status + * - CPSR + */ for (i = 0; i < 16; i++) { (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; @@ -329,7 +363,12 @@ static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, in return ERROR_OK; } -int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +/** Runs a Thumb algorithm in the target. */ +int armv7m_run_algorithm(struct target_s *target, + int num_mem_params, mem_param_t *mem_params, + int num_reg_params, reg_param_t *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; @@ -337,7 +376,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ enum armv7m_mode core_mode = armv7m->core_mode; int retval = ERROR_OK; int i; - uint32_t context[ARMV7NUMCOREREGS]; + uint32_t context[ARMV7M_NUM_REGS]; if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { @@ -353,7 +392,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ /* refresh core register cache */ /* Not needed if core register cache is always consistent with target process state */ - for (i = 0; i < ARMV7NUMCOREREGS; i++) + for (i = 0; i < ARMV7M_NUM_REGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -387,23 +426,20 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ armv7m_set_core_reg(reg, reg_params[i].value); } - /* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present; - * holding a two-bit field. - * - * FIXME need a solution using ARMV7M_T_MSR(). Use it at least for - * earlier cores. - */ - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY - && armv7m->has_spec20) + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, - 24, 2, armv7m_algorithm_info->core_mode); - armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, + 0, 1, armv7m_algorithm_info->core_mode); + armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } + /* REVISIT speed things up (3% or so in one case) by requiring + * algorithms to include a BKPT instruction at each exit point. + * This eliminates overheads of adding/removing a breakpoint. + */ + /* ARMV7M always runs in Thumb state */ if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK) { @@ -453,14 +489,16 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ } } - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { uint32_t regvalue; regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]); - buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, + armv7m->core_cache->reg_list[i].name, context[i]); + buf_set_u32(armv7m->core_cache->reg_list[i].value, + 0, 32, context[i]); armv7m->core_cache->reg_list[i].valid = 1; armv7m->core_cache->reg_list[i].dirty = 1; } @@ -471,31 +509,41 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ return retval; } +/** Logs summary of ARMv7-M state for a halted target. */ int armv7m_arch_state(struct target_s *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; + uint32_t ctrl, sp; + + ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); + sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32); - LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, + LOG_USER("target halted due to %s, current mode: %s %s\n" + "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, + target->debug_reason)->name, armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32), + (ctrl & 0x02) ? 'p' : 'm', + sp); return ERROR_OK; } +/** Builds cache of architecturally defined registers. */ reg_cache_t *armv7m_build_reg_cache(target_t *target) { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - int num_regs = ARMV7NUMCOREREGS; + int num_regs = ARMV7M_NUM_REGS; reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs); + reg_t *reg_list = calloc(num_regs, sizeof(reg_t)); + armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t)); int i; if (armv7m_core_reg_arch_type == -1) @@ -519,11 +567,11 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) for (i = 0; i < num_regs; i++) { - arch_info[i] = armv7m_core_reg_list_arch_info[i]; + arch_info[i].num = armv7m_regs[i].id; arch_info[i].target = target; arch_info[i].armv7m_common = armv7m; - reg_list[i].name = armv7m_core_reg_list[i]; - reg_list[i].size = 32; + reg_list[i].name = armv7m_regs[i].name; + reg_list[i].size = armv7m_regs[i].bits; reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; @@ -536,13 +584,7 @@ reg_cache_t *armv7m_build_reg_cache(target_t *target) return cache; } -int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target) -{ - armv7m_build_reg_cache(target); - - return ERROR_OK; -} - +/** Sets up target as a generic ARMv7-M core */ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) { /* register arch-specific functions */ @@ -554,14 +596,16 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) return ERROR_OK; } -int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +/** Generates a CRC32 checksum of a memory region. */ +int armv7m_checksum_memory(struct target_s *target, + uint32_t address, uint32_t count, uint32_t* checksum) { working_area_t *crc_algorithm; armv7m_algorithm_t armv7m_info; reg_param_t reg_params[2]; int retval; - uint16_t cortex_m3_crc_code[] = { + static const uint16_t cortex_m3_crc_code[] = { 0x4602, /* mov r2, r0 */ 0xF04F, 0x30FF, /* mov r0, #0xffffffff */ 0x460B, /* mov r3, r1 */ @@ -635,7 +679,9 @@ int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t c return ERROR_OK; } -int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) +/** Checks whether a memory region is zeroed. */ +int armv7m_blank_check_memory(struct target_s *target, + uint32_t address, uint32_t count, uint32_t* blank) { working_area_t *erase_check_algorithm; reg_param_t reg_params[3]; @@ -643,15 +689,15 @@ int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_ int retval; uint32_t i; - uint16_t erase_check_code[] = + static const uint16_t erase_check_code[] = { - /* loop: */ - 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ - 0xEA02, 0x0203, /* and r2, r2, r3 */ - 0x3901, /* subs r1, r1, #1 */ - 0xD1F9, /* bne loop */ - /* end: */ - 0xE7FE, /* b end */ + /* loop: */ + 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ + 0xEA02, 0x0203, /* and r2, r2, r3 */ + 0x3901, /* subs r1, r1, #1 */ + 0xD1F9, /* bne loop */ + /* end: */ + 0xE7FE, /* b end */ }; /* make sure we have a working area */ @@ -710,35 +756,36 @@ static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, uint32_t apsel, apselsave, baseaddr; int retval; - apsel = swjdp->apsel; apselsave = swjdp->apsel; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); + switch (argc) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } + if (apselsave != apsel) - { dap_ap_select(swjdp, apsel); - } dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); retval = swjdp_transaction_endcheck(swjdp); command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr); if (apselsave != apsel) - { dap_ap_select(swjdp, apselsave); - } return retval; } - /* * Return the debug ap id in hexadecimal; * no extra output to simplify script processing */ -extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, +static int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -777,13 +824,21 @@ static int handle_dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp = &armv7m->swjdp_info; uint32_t apsel; - apsel = swjdp->apsel; - if (argc > 0) - apsel = strtoul(args[0], NULL, 0); + switch (argc) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } return dap_info_command(cmd_ctx, swjdp, apsel); } +/** Registers commands used to access DAP resources. */ int armv7m_register_commands(struct command_context_s *cmd_ctx) { command_t *arm_adi_v5_dap_cmd;