X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=3d73b295441c44890baeb5ea65e282c0b9a75d7c;hp=60b244aae38b51a879a03ebaea6f148752a636f6;hb=fa765f137460181fd84529df82309a12c376e71a;hpb=eaacb900dd3ce5257dcfec35a8032a873d141b6a

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 60b244aae3..3d73b29544 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -11,6 +11,9 @@
  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
+ *   Copyright (C) 2018 by Liviu Ionescu                                   *
+ *   <ilg@livius.net>                                                      *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -37,6 +40,7 @@
 #include "armv7m.h"
 #include "algorithm.h"
 #include "register.h"
+#include "semihosting_common.h"
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
@@ -201,8 +205,8 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
 		return ERROR_TARGET_NOT_HALTED;
 
 	buf_cpy(buf, reg->value, reg->size);
-	reg->dirty = 1;
-	reg->valid = 1;
+	reg->dirty = true;
+	reg->valid = true;
 
 	return ERROR_OK;
 }
@@ -240,8 +244,8 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
 		buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
 	}
 
-	armv7m->arm.core_cache->reg_list[num].valid = 1;
-	armv7m->arm.core_cache->reg_list[num].dirty = 0;
+	armv7m->arm.core_cache->reg_list[num].valid = true;
+	armv7m->arm.core_cache->reg_list[num].dirty = false;
 
 	return retval;
 }
@@ -279,8 +283,8 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
 			goto out_error;
 	}
 
-	armv7m->arm.core_cache->reg_list[num].valid = 1;
-	armv7m->arm.core_cache->reg_list[num].dirty = 0;
+	armv7m->arm.core_cache->reg_list[num].valid = true;
+	armv7m->arm.core_cache->reg_list[num].dirty = false;
 
 	return ERROR_OK;
 
@@ -318,7 +322,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 int armv7m_run_algorithm(struct target *target,
 	int num_mem_params, struct mem_param *mem_params,
 	int num_reg_params, struct reg_param *reg_params,
-	uint32_t entry_point, uint32_t exit_point,
+	target_addr_t entry_point, target_addr_t exit_point,
 	int timeout_ms, void *arch_info)
 {
 	int retval;
@@ -343,7 +347,7 @@ int armv7m_run_algorithm(struct target *target,
 int armv7m_start_algorithm(struct target *target,
 	int num_mem_params, struct mem_param *mem_params,
 	int num_reg_params, struct reg_param *reg_params,
-	uint32_t entry_point, uint32_t exit_point,
+	target_addr_t entry_point, target_addr_t exit_point,
 	void *arch_info)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
@@ -375,7 +379,8 @@ int armv7m_start_algorithm(struct target *target,
 	}
 
 	for (int i = 0; i < num_mem_params; i++) {
-		/* TODO: Write only out params */
+		if (mem_params[i].direction == PARAM_IN)
+			continue;
 		retval = target_write_buffer(target, mem_params[i].address,
 				mem_params[i].size,
 				mem_params[i].value);
@@ -384,6 +389,9 @@ int armv7m_start_algorithm(struct target *target,
 	}
 
 	for (int i = 0; i < num_reg_params; i++) {
+		if (reg_params[i].direction == PARAM_IN)
+			continue;
+
 		struct reg *reg =
 			register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
 /*		uint32_t regvalue; */
@@ -403,6 +411,23 @@ int armv7m_start_algorithm(struct target *target,
 		armv7m_set_core_reg(reg, reg_params[i].value);
 	}
 
+	{
+		/*
+		 * Ensure xPSR.T is set to avoid trying to run things in arm
+		 * (non-thumb) mode, which armv7m does not support.
+		 *
+		 * We do this by setting the entirety of xPSR, which should
+		 * remove all the unknowns about xPSR state.
+		 *
+		 * Because xPSR.T is populated on reset from the vector table,
+		 * it might be 0 if the vector table has "bad" data in it.
+		 */
+		struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+		buf_set_u32(reg->value, 0, 32, 0x01000000);
+		reg->valid = true;
+		reg->dirty = true;
+	}
+
 	if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
 			armv7m_algorithm_info->core_mode != core_mode) {
 
@@ -415,8 +440,8 @@ int armv7m_start_algorithm(struct target *target,
 		LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
-		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
-		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
 	}
 
 	/* save previous core mode */
@@ -431,7 +456,7 @@ int armv7m_start_algorithm(struct target *target,
 int armv7m_wait_algorithm(struct target *target,
 	int num_mem_params, struct mem_param *mem_params,
 	int num_reg_params, struct reg_param *reg_params,
-	uint32_t exit_point, int timeout_ms,
+	target_addr_t exit_point, int timeout_ms,
 	void *arch_info)
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
@@ -461,7 +486,7 @@ int armv7m_wait_algorithm(struct target *target,
 
 	armv7m->load_core_reg_u32(target, 15, &pc);
 	if (exit_point && (pc != exit_point)) {
-		LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32,
+		LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
 			pc,
 			exit_point);
 		return ERROR_TARGET_TIMEOUT;
@@ -510,8 +535,8 @@ int armv7m_wait_algorithm(struct target *target,
 				armv7m_algorithm_info->context[i]);
 			buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
 				0, 32, armv7m_algorithm_info->context[i]);
-			armv7m->arm.core_cache->reg_list[i].valid = 1;
-			armv7m->arm.core_cache->reg_list[i].dirty = 1;
+			armv7m->arm.core_cache->reg_list[i].valid = true;
+			armv7m->arm.core_cache->reg_list[i].dirty = true;
 		}
 	}
 
@@ -520,8 +545,8 @@ int armv7m_wait_algorithm(struct target *target,
 		LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
 		buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
 			0, 1, armv7m_algorithm_info->core_mode);
-		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
-		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+		armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
 	}
 
 	armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
@@ -536,11 +561,15 @@ int armv7m_arch_state(struct target *target)
 	struct arm *arm = &armv7m->arm;
 	uint32_t ctrl, sp;
 
+	/* avoid filling log waiting for fileio reply */
+	if (target->semihosting && target->semihosting->hit_fileio)
+		return ERROR_OK;
+
 	ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
 	sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
 
 	LOG_USER("target halted due to %s, current mode: %s %s\n"
-		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
+		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
 		debug_reason_name(target),
 		arm_mode_name(arm->core_mode),
 		armv7m_exception_string(armv7m->exception_number),
@@ -548,7 +577,8 @@ int armv7m_arch_state(struct target *target)
 		buf_get_u32(arm->pc->value, 0, 32),
 		(ctrl & 0x02) ? 'p' : 'm',
 		sp,
-		arm->is_semihosting ? ", semihosting" : "");
+		(target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
+		(target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
 
 	return ERROR_OK;
 }
@@ -589,8 +619,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 		if (storage_size < 4)
 			storage_size = 4;
 		reg_list[i].value = calloc(1, storage_size);
-		reg_list[i].dirty = 0;
-		reg_list[i].valid = 0;
+		reg_list[i].dirty = false;
+		reg_list[i].valid = false;
 		reg_list[i].type = &armv7m_reg_type;
 		reg_list[i].arch_info = &arch_info[i];
 
@@ -677,7 +707,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 
 /** Generates a CRC32 checksum of a memory region. */
 int armv7m_checksum_memory(struct target *target,
-	uint32_t address, uint32_t count, uint32_t *checksum)
+	target_addr_t address, uint32_t count, uint32_t *checksum)
 {
 	struct working_area *crc_algorithm;
 	struct armv7m_algorithm armv7m_info;
@@ -726,34 +756,23 @@ cleanup:
 	return retval;
 }
 
-/** Checks whether a memory region is erased. */
+/** Checks an array of memory regions whether they are erased. */
 int armv7m_blank_check_memory(struct target *target,
-	uint32_t address, uint32_t count, uint32_t *blank, uint8_t erased_value)
+	struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
 {
 	struct working_area *erase_check_algorithm;
-	struct reg_param reg_params[3];
+	struct working_area *erase_check_params;
+	struct reg_param reg_params[2];
 	struct armv7m_algorithm armv7m_info;
-	const uint8_t *code;
-	uint32_t code_size;
 	int retval;
 
+	static bool timed_out;
+
 	static const uint8_t erase_check_code[] = {
 #include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
 	};
-	static const uint8_t zero_erase_check_code[] = {
-#include "../../contrib/loaders/erase_check/armv7m_0_erase_check.inc"
-	};
 
-	switch (erased_value) {
-	case 0x00:
-		code = zero_erase_check_code;
-		code_size = sizeof(zero_erase_check_code);
-		break;
-	case 0xff:
-	default:
-		code = erase_check_code;
-		code_size = sizeof(erase_check_code);
-	}
+	const uint32_t code_size = sizeof(erase_check_code);
 
 	/* make sure we have a working area */
 	if (target_alloc_working_area(target, code_size,
@@ -761,40 +780,110 @@ int armv7m_blank_check_memory(struct target *target,
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 
 	retval = target_write_buffer(target, erase_check_algorithm->address,
-			code_size, code);
+			code_size, erase_check_code);
 	if (retval != ERROR_OK)
-		goto cleanup;
+		goto cleanup1;
+
+	/* prepare blocks array for algo */
+	struct algo_block {
+		union {
+			uint32_t size;
+			uint32_t result;
+		};
+		uint32_t address;
+	};
+
+	uint32_t avail = target_get_working_area_avail(target);
+	int blocks_to_check = avail / sizeof(struct algo_block) - 1;
+	if (num_blocks < blocks_to_check)
+		blocks_to_check = num_blocks;
+
+	struct algo_block *params = malloc((blocks_to_check+1)*sizeof(struct algo_block));
+	if (params == NULL) {
+		retval = ERROR_FAIL;
+		goto cleanup1;
+	}
+
+	int i;
+	uint32_t total_size = 0;
+	for (i = 0; i < blocks_to_check; i++) {
+		total_size += blocks[i].size;
+		target_buffer_set_u32(target, (uint8_t *)&(params[i].size),
+						blocks[i].size / sizeof(uint32_t));
+		target_buffer_set_u32(target, (uint8_t *)&(params[i].address),
+						blocks[i].address);
+	}
+	target_buffer_set_u32(target, (uint8_t *)&(params[blocks_to_check].size), 0);
+
+	uint32_t param_size = (blocks_to_check + 1) * sizeof(struct algo_block);
+	if (target_alloc_working_area(target, param_size,
+			&erase_check_params) != ERROR_OK) {
+		retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		goto cleanup2;
+	}
+
+	retval = target_write_buffer(target, erase_check_params->address,
+				param_size, (uint8_t *)params);
+	if (retval != ERROR_OK)
+		goto cleanup3;
+
+	uint32_t erased_word = erased_value | (erased_value << 8)
+			       | (erased_value << 16) | (erased_value << 24);
+
+	LOG_DEBUG("Starting erase check of %d blocks, parameters@"
+		 TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
 
 	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 	armv7m_info.core_mode = ARM_MODE_THREAD;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
-	buf_set_u32(reg_params[0].value, 0, 32, address);
+	buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
 
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
-	buf_set_u32(reg_params[1].value, 0, 32, count);
+	buf_set_u32(reg_params[1].value, 0, 32, erased_word);
 
-	init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
-	buf_set_u32(reg_params[2].value, 0, 32, erased_value);
+	/* assume CPU clk at least 1 MHz */
+	int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
 
 	retval = target_run_algorithm(target,
-			0,
-			NULL,
-			3,
-			reg_params,
-			erase_check_algorithm->address,
-			erase_check_algorithm->address + (code_size - 2),
-			10000,
-			&armv7m_info);
+				0, NULL,
+				ARRAY_SIZE(reg_params), reg_params,
+				erase_check_algorithm->address,
+				erase_check_algorithm->address + (code_size - 2),
+				timeout,
+				&armv7m_info);
+
+	timed_out = retval == ERROR_TARGET_TIMEOUT;
+	if (retval != ERROR_OK && !timed_out)
+		goto cleanup4;
+
+	retval = target_read_buffer(target, erase_check_params->address,
+				param_size, (uint8_t *)params);
+	if (retval != ERROR_OK)
+		goto cleanup4;
 
-	if (retval == ERROR_OK)
-		*blank = buf_get_u32(reg_params[2].value, 0, 32);
+	for (i = 0; i < blocks_to_check; i++) {
+		uint32_t result = target_buffer_get_u32(target,
+					(uint8_t *)&(params[i].result));
+		if (result != 0 && result != 1)
+			break;
+
+		blocks[i].result = result;
+	}
+	if (i && timed_out)
+		LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
 
+	retval = i;		/* return number of blocks really checked */
+
+cleanup4:
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
-	destroy_reg_param(&reg_params[2]);
 
-cleanup:
+cleanup3:
+	target_free_working_area(target, erase_check_params);
+cleanup2:
+	free(params);
+cleanup1:
 	target_free_working_area(target, erase_check_algorithm);
 
 	return retval;
@@ -838,8 +927,5 @@ const struct command_registration armv7m_command_handlers[] = {
 	{
 		.chain = arm_command_handlers,
 	},
-	{
-		.chain = dap_command_handlers,
-	},
 	COMMAND_REGISTRATION_DONE
 };