X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=dde1f23e0f97bb5cd48bb2ac65a1ef602cecf7a5;hp=b23e706555503e43aff2a51c4a44350fb5ffc535;hb=1163435e19f316a4a97fd33f1467f5c1684db654;hpb=7e4f9ac6979029f2cd0fd95d77cc9d8c8b46901b diff --git a/src/target/armv7a.h b/src/target/armv7a.h index b23e706555..dde1f23e0f 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -19,45 +19,11 @@ #ifndef ARMV7A_H #define ARMV7A_H -#include "register.h" -#include "target.h" -#include "log.h" #include "arm_adi_v5.h" -#include "armv4_5.h" +#include "arm.h" #include "armv4_5_mmu.h" #include "armv4_5_cache.h" - -typedef enum armv7a_mode -{ - ARMV7A_MODE_USR = 16, - ARMV7A_MODE_FIQ = 17, - ARMV7A_MODE_IRQ = 18, - ARMV7A_MODE_SVC = 19, - ARMV7A_MODE_ABT = 23, - ARMV7A_MODE_UND = 27, - ARMV7A_MODE_SYS = 31, - ARMV7A_MODE_MON = 22, - ARMV7A_MODE_ANY = -1 -} armv7a_t; - -extern char **armv7a_mode_strings; - -typedef enum armv7a_state -{ - ARMV7A_STATE_ARM, - ARMV7A_STATE_THUMB, - ARMV7A_STATE_JAZELLE, - ARMV7A_STATE_THUMBEE, -} armv7a_state_t; - -extern char *armv7a_state_strings[]; - -extern int armv7a_core_reg_map[8][17]; - -#define ARMV7A_CORE_REG_MODE(cache, mode, num) \ - cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]] -#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \ - cache->reg_list[armv7a_core_reg_map[mode][num]] +#include "arm_dpm.h" enum { @@ -65,18 +31,7 @@ enum ARM_CPSR = 16 } ; -/* offsets into armv4_5 core register cache */ -enum -{ - ARMV7A_CPSR = 31, - ARMV7A_SPSR_FIQ = 32, - ARMV7A_SPSR_IRQ = 33, - ARMV7A_SPSR_SVC = 34, - ARMV7A_SPSR_ABT = 35, - ARMV7A_SPSR_UND = 36 -}; -#define ARMV4_5_COMMON_MAGIC 0x0A450A45 #define ARMV7_COMMON_MAGIC 0x0A450999 /* VA to PA translation operations opc2 values*/ @@ -88,99 +43,140 @@ enum #define V2POWPW 5 #define V2POWUR 6 #define V2POWUW 7 +/* L210/L220 cache controller support */ +struct armv7a_l2x_cache { + uint32_t base; + uint32_t way; +}; -typedef struct armv7a_common_s -{ - int common_magic; - reg_cache_t *core_cache; - enum armv7a_mode core_mode; - enum armv7a_state core_state; - - /* arm adp debug port */ - swjdp_common_t swjdp_info; - armv4_5_mmu_common_t armv4_5_mmu; - armv4_5_common_t armv4_5_common; - void *arch_info; - -// int (*full_context)(struct target_s *target); -// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode); -// int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value); - int (*read_cp15)(struct target_s *target, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t *value); - int (*write_cp15)(struct target_s *target, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, uint32_t value); - - int (*examine_debug_reason)(target_t *target); - void (*pre_debug_entry)(target_t *target); - void (*post_debug_entry)(target_t *target); - - void (*pre_restore_context)(target_t *target); - void (*post_restore_context)(target_t *target); - -} armv7a_common_t; - -typedef struct armv7a_algorithm_s +struct armv7a_cachesize { - int common_magic; + uint32_t level_num; + /* cache dimensionning */ + uint32_t linelen; + uint32_t associativity; + uint32_t nsets; + uint32_t cachesize; + /* info for set way operation on cache */ + uint32_t index; + uint32_t index_shift; + uint32_t way; + uint32_t way_shift; +}; - enum armv7a_mode core_mode; - enum armv7a_state core_state; -} armv7a_algorithm_t; -typedef struct armv7a_core_reg_s +struct armv7a_cache_common { - int num; - enum armv7a_mode mode; - target_t *target; - armv7a_common_t *armv7a_common; -} armv7a_core_reg_t; - -int armv7a_arch_state(struct target_s *target); -reg_cache_t *armv7a_build_reg_cache(target_t *target, - armv7a_common_t *armv7a_common); -int armv7a_register_commands(struct command_context_s *cmd_ctx); -int armv7a_init_arch_info(target_t *target, armv7a_common_t *armv7a); - -/* map psr mode bits to linear number */ -static inline int armv7a_mode_to_number(enum armv7a_mode mode) + int ctype; + struct armv7a_cachesize d_u_size; /* data cache */ + struct armv7a_cachesize i_size; /* instruction cache */ + int i_cache_enabled; + int d_u_cache_enabled; + /* l2 external unified cache if some */ + void *l2_cache; + int (*flush_all_data_cache)(struct target *target); + int (*display_cache_info)(struct command_context *cmd_ctx, + struct armv7a_cache_common *armv7a_cache); +}; + + +struct armv7a_mmu_common { - switch (mode) - { - case ARMV7A_MODE_USR: return 0; break; - case ARMV7A_MODE_FIQ: return 1; break; - case ARMV7A_MODE_IRQ: return 2; break; - case ARMV7A_MODE_SVC: return 3; break; - case ARMV7A_MODE_ABT: return 4; break; - case ARMV7A_MODE_UND: return 5; break; - case ARMV7A_MODE_SYS: return 6; break; - case ARMV7A_MODE_MON: return 7; break; - case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */ - default: - LOG_ERROR("invalid mode value encountered, val %d", mode); - return -1; - } -} + /* following field mmu working way */ + int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */ + uint32_t ttbr0_mask;/* masked to be used */ + uint32_t os_border; + + int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); + struct armv7a_cache_common armv7a_cache; + uint32_t mmu_enabled; +}; -/* map linear number to mode bits */ -static inline enum armv7a_mode armv7a_number_to_mode(int number) + + +struct armv7a_common { - switch(number) - { - case 0: return ARMV7A_MODE_USR; break; - case 1: return ARMV7A_MODE_FIQ; break; - case 2: return ARMV7A_MODE_IRQ; break; - case 3: return ARMV7A_MODE_SVC; break; - case 4: return ARMV7A_MODE_ABT; break; - case 5: return ARMV7A_MODE_UND; break; - case 6: return ARMV7A_MODE_SYS; break; - case 7: return ARMV7A_MODE_MON; break; - default: - LOG_ERROR("mode index out of bounds"); - return ARMV7A_MODE_ANY; - } + struct arm armv4_5_common; + int common_magic; + struct reg_cache *core_cache; + + struct adiv5_dap dap; + + /* Core Debug Unit */ + struct arm_dpm dpm; + uint32_t debug_base; + uint8_t debug_ap; + uint8_t memory_ap; + /* mdir */ + uint8_t multi_processor_system; + uint8_t cluster_id; + uint8_t cpu_id; + + /* cache specific to V7 Memory Management Unit compatible with v4_5*/ + struct armv7a_mmu_common armv7a_mmu; + + int (*examine_debug_reason)(struct target *target); + int (*post_debug_entry)(struct target *target); + + void (*pre_restore_context)(struct target *target); }; +static inline struct armv7a_common * +target_to_armv7a(struct target *target) +{ + return container_of(target->arch_info, struct armv7a_common, + armv4_5_common); +} + +/* register offsets from armv7a.debug_base */ + +/* See ARMv7a arch spec section C10.2 */ +#define CPUDBG_DIDR 0x000 + +/* See ARMv7a arch spec section C10.3 */ +#define CPUDBG_WFAR 0x018 +/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */ +#define CPUDBG_DSCR 0x088 +#define CPUDBG_DRCR 0x090 +#define CPUDBG_PRCR 0x310 +#define CPUDBG_PRSR 0x314 + +/* See ARMv7a arch spec section C10.4 */ +#define CPUDBG_DTRRX 0x080 +#define CPUDBG_ITR 0x084 +#define CPUDBG_DTRTX 0x08c + +/* See ARMv7a arch spec section C10.5 */ +#define CPUDBG_BVR_BASE 0x100 +#define CPUDBG_BCR_BASE 0x140 +#define CPUDBG_WVR_BASE 0x180 +#define CPUDBG_WCR_BASE 0x1C0 +#define CPUDBG_VCR 0x01C + +/* See ARMv7a arch spec section C10.6 */ +#define CPUDBG_OSLAR 0x300 +#define CPUDBG_OSLSR 0x304 +#define CPUDBG_OSSRR 0x308 +#define CPUDBG_ECR 0x024 + +/* See ARMv7a arch spec section C10.7 */ +#define CPUDBG_DSCCR 0x028 + +/* See ARMv7a arch spec section C10.8 */ +#define CPUDBG_AUTHSTATUS 0xFB8 + +int armv7a_arch_state(struct target *target); +int armv7a_identify_cache(struct target *target); +struct reg_cache *armv7a_build_reg_cache(struct target *target, + struct armv7a_common *armv7a_common); +int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); +int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, + uint32_t *val,int meminfo); +int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val); + +int armv7a_handle_cache_info_command(struct command_context *cmd_ctx, + struct armv7a_cache_common *armv7a_cache); + +extern const struct command_registration armv7a_command_handlers[]; #endif /* ARMV4_5_H */